Delay degradation effect in submicronic CMOS inverters

Delay degradation effect in submicronic CMOS inverters J. Juan-Chico1, M. J. Bellido1, A. J. Acosta2, A. Barriga2, M. Valencia1. Instituto de Microelectrónica de Sevilla. Centro Nacional de Microelectrónica. Edificio CICA, Avda. Reina Mercedes s/n, 41012-Sevilla, Spain. 1 Also with Dpto. de Tecnología Electrónica de la Universidad de Sevilla. 2 Also with Dpto. de Electrónica y Electromagnetismo de la Universidad de Sevilla. Tlf. (95) 423 99 23. FAX: (95) 423 18 32 / 462 45 06. E-MAIL: {jjchico, bellido, acojim, barriga, manolov}@imse.cnm.es Abstract. This communication presents the evidence of a degradation effect causing important reductions in the delay of a CMOS inverter when consecutive input transition are close in time. Complete understanding of the effect is demonstrated, providing a quantifying model. Fully characterization as a function of design variables and external conditions is carried out, making the model suitable for using in library characterization as well as simulation at a transistor level. Comparison with HSPICE level 6 simulations shows satisfactory accuracy for timing evaluation. 1. Introduction Timing simulation of digital integrated circuits is a traditional source of doubt for the designer when he has to choose between accuracy of results and simulation time. Event-driven logic simulators provide high speed, and their main disadvantage lies in their lack of precision due to the fact that they usually incorporate an excessively simple propagation delay model. To improve the precision of the simulation results in logic simulators, other effects must be considered: input signal transition time [1, 2, 3, 4]; input to output coupling capacitance and short-circuit currents [3, 4]; reduction of serial connected MOSFETs [5, 6] and input collisions [5, 7]. This paper focuses on glitch type input collisions. As the circuit frequencies goes higher, input transitions begin to happen closer in time, forming narrow pulses. This may cause important delay reductions, as will be shown in this paper. We have called this effect delay degradation or simply degradation effect. Two needs arise: for the IC This work was supported in part by the CICYT under project TIC 95-0094, and by the Laboratoire d'Informatique, de Robotique et de Microéléctronique de Montpellier (LIRMM). designer, the need to know which timing conditions this effect take place in, and for the logic simulator programmer and the cell library characterizer, the need of delay models taking account of this effect. In this paper we present a model to calculate the propagation delay of an inverter under glitch input conditions. It will be shown that significant delay reductions are obtained as the input pulse widths become comparable to a few times the normal propagation delay of the gate. This way, the classical approach establishing a sharp limit between normal propagation delay and pulse filtering is no longer valid and its use can drive to important inaccuracies. The proposed model is fully characterized in terms of inverter size, load capacitance, input transition time and power supply, which make it suitable for cell library characterization and transistor level logic simulation. In sec. 2 we describe the nature of degradation effect and a model for its characterization. In sec. 3, some examples are presented showing the importance of degradation effect and the timing range in which it may occurs. In sec. 4, a complete analysis of degradation parameters in terms of design and external parameters is developed. Simulation results validating the model are included in sec. 5, to finish with some conclusions in sec. 6. 2. Degradation effect modelling. Degradation effect takes place when an input transition arise and the gate has not yet fully switched since the previous transition was propagated. A parameter that reflects the state of the gate when a new transition happens can be simply the elapsed time since the last output transition (T, shown in Fig. 1), where a transition means any signal crossing the 50% of the supply rail (VDD/2). At an electrical level, different cases can be considered. In Fig. 2, in thin line, different input transitions are shown, with the corresponding output transitions in thicker line. Three cases can be observed (a, b and c) corresponding to three different values of T: Case a) if T is large enough (T=T0), the output signal has completely switched when a new input transition occurs and so this will propagate with a delay independent on T (i.e. with normal delay) (Fig. 2a). Case b) if T is small enough (T=T1), the output starts to propagate a transition in the opposite direction when is still switching the previous one (Fig. 2b). This yields a reduced propagation delay compared to the normal one (tHL1<tHL0). This is the case of degradation effect. Case c) for even smaller values of T (T=T2), it is possible that output comes back to the low level before it crosses the logical threshold (Fig. 2c), hence, in this case, and in a logical sense, neither the current, nor the previous transition take place. This behavior is referred as pulse filtering. This behavior provides a continuous reduction in propagation delay as T decreases, giving curves as the one shown in Fig. 3, with three qualitatively different zones: one corresponding to normal propagation, one with different levels of degradation effect and a pulse filtering zone. These curves can be fitted to the following exponential expression: (1) where tHL0 is the normal propagation delay and τHL and THL are the parameters describing the degradation effect that will be referred as degradation parameters. The degradation parameters τHL and THL have a clear physical meaning. To understand this meaning let us consider the input pulse causing degradation effect plotted in Fig. 4, and let us assume that an effective gate's activation threshold voltage exists (VTL) denoting the minimum input voltage needed for a high-to-low output transition to start IN OUT OUTIN T 0 1000 2000 VDD/2 VDD 0 (a) (b) (c) tHL0 tHL1 T1 T2 T0 Vin Vout t (ps) Fig. 1: T parameter Fig. 2: Different behavior depending on T. a) Normal propagation, b) Degradation effect, c) Filtering tHL tHL01e TT HL – τHL ------------------– –    = swinging. This threshold is related to the NMOS threshold voltage (VTN) extracted from the inverter I-V characteristic, but is also affected by the complementary transistor (PMOS) since at the beginning of an output switching, both transistors may drive some current at the same time. In these conditions and after the output transition at instant t0, degradation effect will take place or not depending on T', i.e. the state of the output when the gate is activated. With respect to delay evaluation, we can say that if T' is larger than a given value, say T*, the delay will be essentially equal to the normal propagation delay (e.g. greater than 0.95tHL0). Additionally, if we can express T' as a function of T: (2) where T*HL represents the elapsed time since Vin crosses VTL to it crosses VDD/2 (t2- t1). Thus we obtain: (3) On the other hand, from (1) we derive that: (4) so the following correspondence between (3) and (4) can be established: (5) Fig. 3: tHL vs. T curve showing regions with different behavior Fig. 4: Electrical behavior causing degradation effect. THL T tHL/tHL0 Normal propagationPulse filtering -0.2 0.0 0.2 0.4 0.6 0.8 Degradation effect 1.0 0 VDD/2 VDD 0 Vin Vout t VTL T τIN T' T*HL t0t1t2 T'TT ∗HL –= TT ∗HL –T∗ <tHL 0.95tHL0 <⇒ TT ∗HL –T∗ >tHL 0.95tHL0 >⇒ TT HL –3τHL <tHL 0.95tHL0 <⇒ TT HL –3τHL >tHL 0.95tHL0 >⇒ THL T∗HL ≡ 3τHL T∗ ≡ yielding the following definitions for the degradation parameters: •τHL: A measure of the time required by the gate's output after a logical transition to achieve a steady state. A gate's activation after a time greater than 3τHL since the last logical transition will generate a propagation delay that can be considered normal (tHL > 0.95tHL0). •T HL: the elapsed time since Vin crosses VTL to it crosses VDD/2. A simple analysis based on Fig. 4 gives: (6) where τin is the linearized input transition time. 3. Evaluating degradation effect importance. In this section we show how to quantify the input timing producing significant degradation effect (middle zone in Fig. 3). For quantification purposes it is convenient to define the degradation limit (DL) as (for a high-low transition): (7) This is an appropriate limit between degradation and normal propagation regions, as long as (8) This way, DL is the time to wait after an output transition for a new input transition to propagate with an essentially normal propagation delay. The importance of degradation effect can then be evaluated by the value of DL related to the normal propagation delay. In Table 1 we show fitted degradation parameters as well as the DL to tHL0 ratio for two minimum length CMOS inverter examples, under different input slope conditions. In this table, k is the internal configuration ratio ( ), CL the output loading capacitance, CIN the inverter's equivalent input capacitance, THLS the step response delay [4] and τin the linearized input transition time. Here, k, CIN and THLS are used as convenient normalizing parameters. From these data, an important fact arises: degradation effect is not a marginal effect THL 1 2 ---VTL VDD ----------–    τin = DLHL THL 3τHL += TDL HL >tHL 0.95tHL0 >⇒ WPWN ⁄ since an input transition will propagate with a delay sensibly smaller than the normal propagation delay even if the elapsed time since the last output transition is as large as 2-3 times the normal propagation delay. In order to see this situation from the point of view of a single input pulse entering an inverter, let us assume for the sake of clarity that both tHL0 and tLH0 are equal and that DL/tHL0 is equal to 2. In this case, Fig. 5 shows how the second transition of an input pulse of width will suffer degradation effect and a corresponding width shortening: . This behavior is in clear disagreement with the classical approach in which the only condition for a pulse to propagate with normal delay was while pulses with were eliminated from the output (filtered), yielding to an erroneous discontinuous behavior of the propagation delay. In fact there is a continuous variation as expressed in (1) and plotted in Fig. 3 that extends along a timing region of significant width. 4. Design oriented characterization of degradation parameters. From now on, we will consider minimum length transistors. Regarding equation (1), the parameters to be characterized are the normal propagation delay (tHL0) and the degradation parameters (τHL and THL). tHL0 characterization has been a main issue in delay modelling for years and the case of the inverter has been widely studied in the bibliography [3, 4, 5, 8]. In particular, the model proposed by tHL0 ∼ tLH0 tHL0 Twin IN OUT Twout<Twin Degradation zone Pulse width 3tHL0 Example 1: k=1 τIN/2THLS tHL0 (ps) τHL (ps) THL (ps) DL(ps) DL/tHL0 0.1 121 189 -5.86 561 4.6 2 162 139 79.4 496 3.1 5 187 140 217 637 3.4 Example 2: k=2 τIN/2THLS tHL0 (ps) τHL (ps) THL (ps) DL(ps) DL/tHL0 0.1 183 137 -0.16 411 2.2 2 250 117 76 427 1.7 3 278 108 135 459 1.7 Table 1: DL to tHL0 ratio for several inverter configurations. WN=4µm, CL=4CIN, VDD=5V Fig. 5: Pulse narrowing due to degradation effect on its second transition Twin 3tHL0 < Twout Twin < Twin tHL0 >Twin tHL0 < Daga et. al. includes complete dependence with design parameters for a wide range of values in a submicronic technology, achieving a high accuracy degree. Thus, the present paper will concentrate in the characterization of τHL and THL. Once it is done, the term: (9) might be applied to any previously developed model for tHL0 in order to achieve degradation effect correction (1). Basing on the definitions for τHL given in sec. 2, we propose the following expression for τHL: (10) where Af and Bf are fitting constants characteristic for a given technology. It has been assumed that the product does not depend on changes in supply voltage. This hypothesis will be validated in sec. 5. Regarding THL, we have seen in sec. 2 that it can be modelled as: (11) where is the reduced effective gate's activation threshold voltage defined as , which is closely related to the active transistor threshold voltage (NMOS in this case) as we will see in next section. 5. Simulation results. Validation of the proposed model has been done through HSPICE [9] level 6 simulations for a 0.7µm CMOS process. As mentioned above, all MOSFETs are of minimum length. Several simulations have been performed for typical value ranges of CL,τin, VDD, WN and WP. Curves like the one on Fig. 6 can be obtained measuring the propagation delay (e.g. tHL) for different values of T. On the other hand, a simple transformation of (1) gives: 1e TT HL – τHL ------------------– –    τHLVDD AfBf CL WP ------- += τHLVDD THL 1 2 ---vTL –   τin = vTL vTL VTL VDD ⁄= (12) which allow us to obtain THL and τHL by linear regression. The corresponding fitting is the solid line in Fig. 6. All the studied cases give similar good fittings which validates the proposed equation. This process is done repeatedly for different design and external parameter values to check the validity of (10) and (11). τHL characterization. In Fig. 7 we plot τHLVDD vs. the ratio CL/WP for WN=4µm, VDD=5V and τin=2THLS. Wide ranges of load capacitances and inverter configuration ratios are involved. The linearity obtained in Fig. 7 validates (10) and allow us to calculate the technology characteristic parameters Af and Bf for the ES2 CMOS 0.7µm process: (13) Similar results has been obtained for WN=8µm, VDD=3V and τin up to 10THLS with maximum discrepancies of 5% for Bf and 2% for Af. Thus the product can be considered independent of the mentioned parameters in the range of interest, in agreement with (10). Fig. 6: tHL vs. T simulation data for a sample inverter Fig. 7: τHLVDD vs. CL/WP curve. T (ps) tHL/tHL0 WN = 4 µm VDD = 5 V CL/CIN = 5 k = 1 τin = 4THLS tHL0 = 197 ps 0 500 1000 1500 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 0 10203040 0 0.5 1.0 1.5 2.0 Simulated Fitted VDD = 5 V, CL/CIN = 2...8, k = 1...3, τin = 2THLS slope = 43.7±1.0 intercept = 101±18 corr. coef. = 0.9972 WN = 4µm τHLVDD (pF V) CL/WP (fF/µm) TT HL τHL 1tHL tHL0 ----------–    ln–+= Af96.5 17±()ps V×=Bf43.2 1.0±() ps V µm×× fF --------------------------------- = corr. coef. 0.9973= τHLVDD THL characterization Eq. (11) gives the model for the second degradation parameter, THL. This equation predicts a linear dependence of THL on τin, which is obtained in Fig. 8 for different inverter configurations and load capacitances. The different curves maintain the same slopes even if we duplicate the output load. However, a significant variation in the slope is observed as the value of k increases. This, in turn, means a variation of vTL. This variations are summarized in Table 2, as well as the corresponding values for vTL and the vTL to vTN ratio, being vTN the reduced threshold of the driving transistor (VTN/VDD). It can be observed how vTL increases as the driving capability of the PMOS with respect to the NMOS (represented by k) increases, which is due to the fact that for a stronger PMOS, a higher conduction level is needed in the NMOS to makes the output to start switching. This agrees with the fact that for a relatively weak PMOS (k=1) the effective activation threshold tends to the threshold voltage of the NMOS ( ) as shown in Table 2. Further work should be devoted to analyze vTL dependence on k. At this moment two compromise solutions are proposed as long as only a few values of k are typically considered: the first one is to choose a constant trade-off value for vTL in the range of interest. For example, if , a compromise value would be , which deviation is below 15% in the given range. The second and Table 2: Dependence of vTL on k for VDD=5V and WN=4µm. VTN=1.25V for the current technology [4]. Fig. 8: THL vs. τin curves for different output loads and configuration ratios. 0 500 1000 1500 2000 τin(ps) -50 50 150 250 350 450 THL (ps) WN=4 µm, VDD=5 V, τST=24 ps kCL/CIN 1 1 2 2 3 3 4 8 4 8 4 8 kvTL vTL/vTN 1 0.239 0.261 1.05 2 0.160 0.339 1.35 3 0.130 0.370 1.48 2⁄vTL – vTL vTN ≅ k12,[]∈ vTLcomp vTN ⁄1.2=