Contributions to Modulation and Control Algorithms for Multilevel Converters

Proyecto Fin de Carrera Ingeniería de Telecomunicación Formato de Publicación de la Escuela Técnica Superior de Ingeniería Autor: F. Javier Payán Somet Tutor: Juan José Murillo Fuentes Dep. Teoría de la Señal y Comunicaciones Escuela Técnica Superior de Ingeniería Universidad de Sevilla Sevilla, 2013 Doctoral Dissertation Ingeniería Industrial Contributions to Modulation and Control Algorithms for Multilevel Converters Author: Pablo Montero-Robina Director: Francisco Gordillo Álvarez Ingeniería de Sistemas y Automática Escuela Técnica Superior de Ingeniería Universidad de Sevilla Sevilla, 2021 Doctoral Dissertation Ingeniería Industrial Contributions to Modulation and Control Algorithms for Multilevel Converters Author: Pablo Montero-Robina Director: Francisco Gordillo Álvarez Professor Ingeniería de Sistemas y Automática Escuela Técnica Superior de Ingeniería Universidad de Sevilla 2021 Doctoral Dissertation: Contributions to Modulation and Control Algorithms for Multilevel Converters Author: Pablo Montero-Robina Director: Francisco Gordillo Álvarez El tribunal nombrado para juzgar la Tesis arriba indicada, compuesto por los siguientes doctores: Presidente: Vocales: Secretario: acuerdan otorgarle la calificación de: El Secretario del Tribunal Fecha: A Laura Por su apoyo y empatía en este duro proceso del doctorado. Gracias por inspirarme A mi familia Por su apoyo incondicional A mis amigos Por soportar llantos y quejas y permitirme disfrutar de su compañía A mis compañeros de trabajo Por ser una fuente de inspiración y de apoyo A mi director Por su incesante trabajo, esfuerzo y comprensión Abstract The current trends on electrical energy have encouraged the search of more efficient systems of generation, distribution and consumption of electrical power. Distributed generation, reduction of passive components, high-voltage DC lines, among others are some lines of research that are being fully considered as the future of electrical grid. This is possible thanks to the advances on the field of power electronics. This work aims at providing a brief glimpse on the current state of power electronics in the field of gridconnected power converters along with some contributions to the control of a particular kind of topologies, referred as multilevel converters, that improve the power conversion efficiency. It is expected that this work will assist future researchers on setting a framework on the field, and provide them with inspiring material to develop further improvements on the stated solutions. III XNotation MPC-FCS Model predictive finite control set MPP Maximum power point MPPT Maximum power point tracking MOSFET Metal-oxide semiconductor field-effect transistor NLC Nearest level control NLM Nearest level modulation NPC Neutral-point clamped OL Outer loop OICM Original integrated control and modulation PD-PWM Phase-disposition PWM PhDet Phase detector (used for PLL) PI Proportional integral (controller) PLL Phase-locked loop POD-PWM Phase opposite disposition (type of LS-PWM) PR Proportional resonant (controller) PS-PWM Phase-shift PWM PV Photo-voltaic PWM Pulse-width modulation RMS Root-mean square S&H Sampla & hold SHE Selective harmonic elimination SM Submodule (for MMC) SSA Switching-saving algorithm SOGI Second-order general integrator SV Space vector SVBA Space-vector-based algorithm SVM Space-vector modulation VCO Voltage controlled oscillator (used for PLL) VSC Voltage source converter VSI Voltage source inverter ZOH Zero-order hold 1 Introduction If you want to find the secrets of the universe, think in terms of energy, frequency and vibration. Nikola Tesla This chapter introduces the basis knowledge and state of art that settled the contributions of this work. For this, a brief glimpse in the field of power electronics is firstly given before entering the main theme of this work, multilevel converters. It is expected that this chapter helps future researchers to become acquainted with the state-of-art of grid-connected power converters at the moment this work was written, and assists others in the comprehension of power electronics. In the following, a brief description of the document content is firstly given, along with its objectives and structure. Secondly, a more extended background and state-of-art is provided. 1.1 Document description 1.1.1 Context of the research This research has been carried out under the following projects: • Control no lineal del balance de tensiones en convertidores multinivel (DPI2013- 41891-R). • Control de Sistemas con Entradas Discretas. Aplicación a Convertidores Electrónicos de Potencia (DPI2016-75294-C2-1-R). •ECO-MIR: Estabilidad y COntrol no lineal de MIcRorredes (US-1264655). •Problemas de Estabilidad Global en Microrredes (PID2019-109071RB-I00). The context of this research is placed within the Power Electronics field, which is the application of solid-state electronic devices to the control and conversion of electrical 1 2Chapter 1. Introduction energy. Power Electronics field covers from developing solid-state devices, such as insulated gate bipolar transistor (IGBTs) [1]; arranging them into systems that handle the electrical energy, generally power converters [2]; and designing control strategies to fulfill the objectives for which they have been constructed [3]. Power Electronics has widened considerably in the last decades and there are plenty of research currently available. That is why researchers focus on particular features inside this field. Indeed, the work presented in this thesis is aimed to follow the same scheme, and the contributions presented here are narrowed down to the control of certain topologies of power converters. However, in order to provide a proper framework, the second part of this introduction will cover the background of the current work. Nowadays, the electrical grid uses high-voltage transmission lines to distribute electrical power between distant geographical points. This is so due to the reduced conducting losses that high-voltage transmission lines have in comparison with the low-voltage ones. However, the standard power converters are composed of solid-state devices that do not have the voltage limits high enough to be connected directly to these lines, and therefore an intermediate stage is required to shift the voltage levels, which is usually a transformer device. This solution not only implies additional hardware but also it generates more losses, reducing the overall efficiency of the system. As an alternative [4], the multilevel converter was introduced in the early 90s [5], which overcame the voltage limitations of standard power converters by serializing more than two solid-state devices in such a way that the voltage limits are extended. In this way, the same devices can be used in systems with higher voltage rates without requiring transformers. Additionally, by using several levels, better quality of the phase currents and potential reduction in the filter sizes are achieved. However, due to the increased hardware, the control complexity of the system is also increased. This work aims to present several approaches that overcome this issue. 1.1.2 Objectives The objectives of this work are the following: •About the current state-of-art: –To present the current state-of-art of grid-connected power converters. –To exhibit the basis and foundations of power converters. – To explore the typical approaches for controlling multilevel power converters. •About new contributions: – To present some contributions to the control and modulation of multilevel power converters. These contributions have to consider the topology under study, model its desired behaviour and propose an algorithm that covers the control objectives of such stage. Additionally, the proposed algorithms might take into account some performance indicators in order to develop a more optimal solution. – To depict the benefits of such novel approaches in comparison with the existing ones. For this, some approaches that are already presented in the literature are 1.1 Document description 3 examined and evaluated under the same conditions. In order to depict the benefits some performance indicators are exhibited and used. These comparisons are usually carried out both under simulation and experiments. 1.1.3 Structure The structure of this work is the following 1. This first chapter (Chap. 1) will exhibit the background, some fundamentals and the current state-of-art of power electronics, power converters and control of gridconnected power converters. An introduction to multilevel power converters is also included: topologies, modulation and approaches without modulation stage. 2. The second chapter (Chap. 2) firstly provides a deeper insight into diode-clamped converters and their principle of operation. Afterwards, the main contributions developed for three-level DCC (Sect. 2.2) and five-level DCC (Sect. 2.3) are presented. 3. The third chapter (Chap. 3) introduces the topologies of cascaded and modular converters along with their principle of operation, differences and similarities. Later on, a contribution for cascaded H-bridge topology (Sect. 3.2) and another one for modular multilevel converter (Sect. 3.3) are presented. 4. Lastly, some conclusions are drawn (Chap. 4) about the particular contributions of this work (Sect. 4.1) and possible future works (Sect. 4.2). 1.1.4 List of Publications Published works The following papers and contributions have been published as a result of the current work [1] P. Montero and F. Gordillo, “A modulation algorithm for inter-phase balancing in CHB Converters,” in 2017 11th IEEE International Confer-ence on Compatibility, Power Electronics and Power Engineering (CPE-POWERENG), pp. 133–138, IEEE, 2017. [2] P. Montero-Robina and F. Gordillo, “A Novel Controller for Grid-Interfacing Solar Arrays Through Five-Level Diode-Clamped Converters,” in 2018 IEEE 18th International Power Electronics and Motion Control Conference (PEMC2018), pp. 955–961, IEEE, Aug. 2018. [3] P. Montero-Robina, F. Umbria, F. Salas, and F. Gordillo, “Integrated Control of Five- Level Diode-Clamped Rectifiers,” IEEE Transactions on Industrial Electronics, vol. 66, pp. 6628–6636, Sep. 2019. [4] P. Montero-Robina and F. Gordillo, “A thermal analysis for two modulation and control approaches for five-level diode-clamped rectifiers,” in IECON2019 - 45th Annual Conference of the IEEE Industrial Electronics Society, vol. 2019, pp. 3135– 3141, IEEE, Oct. 2019. [5] P. Montero-Robina, F. Gordillo, F. Gómez-Estern, and F. Salas, “Voltage balance for five-level DCC based on mixed-integer linear programming,” International Journal of Electrical Power &Energy Systems, vol. 124, p. 106302, Jan. 2021. 4Chapter 1. Introduction Submitted papers The following papers were submitted at the moment this dissertation was written [1] P. Montero-Robina, F. Gordillo, F. Cuesta, and F. Gómez-Estern, “Pseudo-optimal Five-Level DCC Modulation Based on Machine Learning,” Submitted to IEEE Transactions on Power Electronics, Jan. 2021. [2] P. Montero-Robina, C. Albea, F. Gómez-Estern Aguilar, and F. Gordillo, “Hybrid modelling and control of Three-level NPC Rectifiers,” Submitted to Control Engineering Practice, May 2021. [3] P. Montero-Robina, K. Rouzbehi, F. Gordillo, J. Pou, "Voltage Source Converters: Current Control Techniques Operating with Unbalanced Voltage Conditions," Submitted to IEEE Open Journal of the Industrial Electronics Society, May 2021. [4] P. Montero-Robina, A. Marquez, M. S. A. Dahidah, S. Vazquez, J. I. Leon, G. Konstantinou, and L. G. Franquelo, “Feed-forward Modulation Technique for more Accurate Operation of Modular Multilevel Converters,” Submitted to IEEE Transactions on Power Electronics, May 2021. 1.2 Background and current state-of-art of grid-connected VSC This section presents the current state-of-art of all fields that constituted the basis from which this dissertation started. They are separated into five subsections that are summarized in the next paragraphs. Firstly, an introduction in the field of power electronics field is given. Solid-state devices and the most common power converters topologies will be exposed. The second subsection is devoted to present the general scheme of the electrical grid, its properties and configurations. There are plenty of assumptions throughout this document that are based on particular conditions of the electrical grid, and thus they will be explained in this subsection. The third subsection exhibits how the power converters are typically controlled. This task generally involves several stages with different control objectives. Besides, the approaches to achieve the power converter control are not unique and their suitability depends on the desired application and performance. The fourth subsection presents the multilevel converter topology, advantages, challenges, common topologies and trends. Note that this document focuses on researching for this kind of power converters, however not all topologies presented in this chapter will be later studied. They are included to show the reader an insight of the field. Lastly, the fifth subsection presents some of the most known modulation techniques for multilevel converter, that is, the way that the control input is integrated in the power converter in order to achieve the desired effect. Some of the modulation techniques require to fulfill additional control objectives when used for multilevel converters, and thus they will be exposed here. 1.2 Background and current state-of-art of grid-connected VSC 5 1.2.1 Power electronics A power electronic system generally follows a scheme composed of a power source, a filtering stage, a power converter, a load and a control circuit [6]. The power source could be of any nature and electrical characteristic, and the main objective is to transfer the generated power from the power source to the load as efficiently as possible. The filter stage is in charge of eliminating those undesired components from the power flow, and thus it can be allocated either after the power source, before the load or in both positions using two filtering stages. The power converter is in charge of manipulating the power flow in such a way that it acquires the characteristics that are desired for the load. This task is carried out by using controlled or uncontrolled solid-state devices that compose the power converter. In the case they are controllable, the switching on/off of the devices is governed by a control circuit, which gets information from the source, the load and the power converter to dictate the power converter how to behave. The nature of this control circuit is discrete—as the gating signals are discrete values—and it can be either a digital algorithm with analog-to-digital (ADC) ports for the measurements or an analog controller integrated in a circuit. A scheme of this type of system is depicted in Fig. 1.1. Figure 1.1 Power electronic system scheme. This work mainly uses the alternating-current (AC) grid as the power source; passive components, such as inductors or capacitors, as filters; controlled power converters with digital controllers; and pure resistive loads. Although, there are some applications that do not follow the same scheme and it will be clarified in those cases. Solid-state devices The solid-state devices are named after its property of being a solid material that can change the flow of charges, i.e. allow the electrical current to pass through or not. In contrast to earlier technologies—gas, vacuum or electro-mechanical devices—there is no change of state, nor any movement within the device when this property changes, allowing them to act as fast switching devices [7]. The main solid-state devices that act as power semiconductors are the following: •Power Diodes 6Chapter 1. Introduction •Thyristors •Bipolar-junction transistors (BJT) •Metal-oxide-semiconductor field-effect transistors (MOSFET) •Insulated-gate-bipolar transistors (IGBT) Power diodes acts similar to signal diodes but for an increased reverse breakdown voltage and increased forward current capability. Thyristors cover a wide family of solid-state devices—Silicon-controlled rectifier (SCR), gate turn-off thyristor (GTO), etc.—that share a similar principle of operation: a bistable mode of operation where either they work in conducting state or not. The operability of them changes from one device to another, but they are able to sustain larger amount of voltages and currents than those other switching devices that are fully operable. BJTs were one of the first fully controllable transistors introduced in the industry whose output current could be controlled from the base. However, the power BJTs have been generally deprecated in power applications by MOSFETs and IGBTs, although there are some applications where BJTs are preferable due to the reduced hardware requirement to switch them, its low cost, its relatively high switching speed, and low switching losses. Power MOSFETs are voltage-controlled devices whose internal disposition slightly differs from its low-power version, increasing their voltage limits and parasitic resistance at the same time. In comparison with IGBTs, the required driving circuit to switch them is simpler and yields lower switching losses. Additionally, their lower switching delays allows them to reach higher switching frequencies when compared to BJTs or IGBTs. Lastly, IGBTs are a combination of the BJTs and power MOSFETs that collects the advantages of both. Thus, it is one of the most used solid-state devices in power applications. They have better conduction characteristics and larger voltage and current limits than power MOSFETs but lower dynamics. They are suitable for power applications with lower switching frequencies (<20 kHz) but larger power magnitudes. Power converters Power converters are the circuits that fulfill the power conditioning objectives of the specific application they were designed for. They are composed of solid-state devices that comply with the magnitude limits of the application. Considering that electricity comes in the form of direct-current (DC) or alternating-current (AC), the topologies of power converters are usually classified according to the input-output nature, i.e. AC-AC, AC-DC, DC-AC or DC-DC. Additionally, each of these topologies have particular characteristics that define their performance, for example, whether they require control actions or not, bidirectional power flow capability, single or three-phase mode of operation for AC, interleaving capabilities for DC, etc. There are plenty of topologies and new ones are being released nowadays, short summaries are exposed in [2,3,6]. AC-DC Converters: They subtract power from an AC source to stabilize a DC output voltage. These are very common converters in low-power applications given the fact that the electrical grid is AC while most of the consumer electronics are fed with DC voltages. Additionally, many 1.2 Background and current state-of-art of grid-connected VSC 7 power converters for aircraft applications are included in this category, as the energy comes from the varying-speed turbines. AC to DC operation is also referred as rectifier mode of operation, and it is common to refer to unidirectional AC-DC power converters as rectifiers. In this regard, the non-controlled diode-rectifier is the simplest construction, which is made up from power diodes that allow the AC current to pass through only in a certain direction, resulting in a positive current delivery. As a consequence, the filtering stage for it is vital given that the current distortion is high, but it does not require external controller. Additionally, there is no control on the reactive power flow which can further increase the considered losses. It is a solution that prioritize compactness and simplicity over performance. Nevertheless, there exists solutions that allow certain degree of control, such that SCR- based rectifiers or power factor correction converters (PFC). These solutions vary in the used devices and capabilities, but they allow the system to modify the output DC voltage within a certain range, and handle the reactive power in some cases. It is worth mentioning that the three-phase voltage source converters (VSCs) are one of the most extended and used topologies due to its bidirectional power flow and its capability of achieving high degree of controllability on the system performance. There is also modular solutions for three-phase applications that consists on combining three single-phase PFCs serialized with a DC-DC converter each, in such a way that each chain contributes to a common DC voltage bus. Alternatively, PFC can be achieved by means of harmonic compensation, which require additional power electronic circuitry to modify the current waveforms. DC-AC Converters: The converters inside this category are also known as inverters, which are capable of transforming a DC magnitude into an AC one. Due to the requirements for the AC output, these converters are always controllable and use gate-controlled power switches. The AC output can be of any phase, magnitude and frequency—within the range of operation of the converter—which makes them suitable for injecting power from a DC source to the electrical grid. Indeed, it is very common to use such converters for renewable energy integration or as grid back-ups when there is shortage of energy production in the electrical grid. Similarly to AC-DC, the voltage source inverters (VSI) are the most used ones. It is very common to catalogue the converter modulation approach inside this topology depending on the type of the AC signal they produce: Square wave, modified square wave and sine wave. For the square wave and modified square wave outputs, the AC signal is produced by using square pulses of the same frequency than the desired AC output, being the filter stage in charge of smoothing out the generated distortion due to this mismatch. In contrast to the simple square wave approach that uses online positive and negative, modified square wave uses positive, zero and negative magnitude pulses, improving the output spectrum quality. Alternatively, thanks to the advancement on power electronics, the so-called true sine wave inverters are possible, which use a modulation technique to generate a more accurate AC signal. DC-DC Converters: The converters within this topology transform the DC voltage magnitude from one value to a different one. On the one hand, this kind of converters are used to guarantee a stable DC-voltage at the output, so they have to handle the variations both in the output power 8Chapter 1. Introduction demand and the DC input magnitude. On the other hand, there are applications that require a variable DC output voltage, where the power converter ’chops’ the input DC voltage to a lower value, and thus they are usually known as choppers. Nevertheless, power switches are employed to fulfill such purpose [8]. Regarding the classification, they are usually segregated by their capability to output a larger and/or lower voltage magnitude. Besides, along this capability, providing an isolated output or not with respect to the input is another factor to consider. The fundamental non-isolated DC-DC converters are usually composed of one switching device, one power diode and one or more passive component (inductor or capacitor). Their performance consists on using the switching device to modify the current flow in such a way that its interaction with the passive component and the diode over a period of time modifies the output voltage. Thus, by modifying the time the switch is closed, the output voltage can be modified accordingly. Typical converters in this category are the buck converter (lower output), boost convert (larger output) and buck-boost converter (both options) [9]. Isolated DC-DC converters use an isolation transformer or coupled inductor to generate an output that is electrically isolated from its input. Similarly to the non-isolated version, they rely on a switching device that, commuting at high frequencies, allows to transfer power from one side to another. Again, the interaction of the coupling agent (transformer or coupled inductor) with the switching of the power device(s) is the factor that modifies the output voltage. Some fundamental topologies of isolated DC-DC converters are the flyback converter, the forward converter, the half-bridge converter and the full-bridge converter [10]. AC-AC Converters: These kind of converters are required in those applications where the power is extracted from an AC source and delivered to another AC system with different characteristics. One flexible way to do so is by using the back-to-back configuration which consists in using an AC-DC connected to a DC-AC converter through the DC stage, usually referred as the dc-link, which contains an energy storage element. These converters can be classified as indirect AC-AC converters with all the properties the involved AC-DC and DC-AC converters have [11]. Nonetheless, there exists one-stage direct AC-AC converters that do not require energy storage elements. The most used ones are the cycloconverter and the matrix converter [12]. The cycloconverters use two controlled rectifiers (composed of SCRs or other kind of thyristors) to modify the injected current in terminals of the load, whereas the matrix converters use k×l bidirectional switches, such as two IGBTs in antiparallel configuration, to connect a k− phase source to a l− phase load. Both configurations do not require large storing elements, but cycloconverters can only modify the frequency at the output, while matrix converters can reduce the voltage magnitude and increase the frequency. 1.2.2 Electrical grid The most basic scheme of the electrical grid is composed of three elements: production, transmission-distribution, and consumption. The characteristics of each element are not unique and they are mainly defined by the scope and context of the actors involved [13]. 1.2 Background and current state-of-art of grid-connected VSC 9 Up to the date, the grid has been mainly developed in alternating current (AC) being the frequency and amplitude magnitude defined by the geographical region it is implemented. The main reason AC has been selected preferably over DC is due to the fact that stepping up and down the voltage magnitude is straightforward by means of a transformer. However, there are some drawbacks, such as additional losses due to parasitic coupling, undesired electromagnetic emissions, and the appearance of the so-called reactive power. The latter is caused by the presence of current distortion and a phase-shift between the fundamental components of the phase voltage and current, which, over a grid period, yields no energy transmission, but the losses associated to the current still remain. In terms of structure, it has kept a traditional scheme of a vertical hierarchy in which energy is transferred from large production centers through transmission lines, and then adapted to be distributed among the consumers. Given that the energy production must match the energy consumption, it is necessary to monitor this condition, and thus the more centralized the grid, the easier to control. However, the introduction of distributed energy generation, specially due to renewable energy, and the intermittent consumers have pushed the industry to look for solutions to stabilize the grid conditions [14]. In this regard, load forecasting models, reactive power compensators, flexible AC transmission systems, etc. have been proposed to provide some means to correct deviations in the desired frequency and voltage amplitude [15–17]. Nonetheless, the principle of using high-voltage lines for large transmission kept unchanged. This is due to the fact that conduction losses are proportional to Irms , being Irms the root mean square (RMS) of the current that is transferred. Considering that a transmitted power (p) that is kept constant in a single line is defined by: p=VrmsIrms,(1.1) where Vrms is the RMS voltage of the grid. The larger the Vrms , the lower the needed Irms to transfer the same active power, and thus the lower the losses. For this, the common scheme is to step-up the voltage before reaching the transmission line, and consequently the losses are reduced in the transportation process. Despite the fact that this process is easily achieved by a transformer thanks to the nature of AC, the transformers are bulky, expensive and generate additional losses, although they are largely compensated by the avoided losses involved in the transportation. For this, it is a fact that AC transmission lines have to be operated at high voltages (HV) and later stepped down to distribution and consumer levels. At this point, the question about why generating power at low voltages when they are later required to be increased arises. Indeed, the generation is usually in the low-voltage side due to the limitations of energy generation drives and power semiconductors, where the elements involved cannot stand such a high voltage. For those cases of large power generation plants, such as nuclear, thermal or hydroelectric, using the transformer seems the most straightforward solution as the generation is very concentrated [18]. However, for distributed generation where lower power sources are geographically spread, using a transformer for each node or gathering all lines into one transformer are economically infeasible solutions. In this context, the concept of multilevel converter arises as a solution that extends the voltage limits of the converter 16 Chapter 1. Introduction Figure 1.5 a) Single-phase full bridge AC-DC converter; b) Three-phase AC-DC VSC. n , is a square wave that goes from 0 to vdc . Due to this and that the modulating signals in three-phase systems are usually 120 ◦ -shifted between phases, the output voltages vi1i2 , measured from phase i1=a,b,c to phase i2=a,b,c , goes from 0 to vdc whenever the modulating signal of phase i1 is bigger than the one of phase i2 , and goes from −vdc to 0 otherwise. There exists other types of carrier-based modulations schemes for multilevel converters that use several carriers. These modulations will be presented later in the multilevel converter section. Space vector modulation in three-phase VSC Instead of considering three separated modulation signals (one per phase), a cartesian vector is used. In this regard, the original signals to be modulated ( vi for phase i=a,b,c ) are represented as a three dimensional vector whose coordinates are known as abc coordinates. However, in a three-phase three-wire system, the common component can be neglected as its effect on AC magnitudes is suppressed, and thus a three-dimension to two-dimension transformation is used. The common transformation that isolates the common component is known as the Clarke transformation Tabc→αβ =r2 3 1−1 2−1 2 0√3 2−√3 2!(1.7) vαβ =Tabc→αβvabc (1.8) Thanks to this, a two-dimension vector in the so-called αβ coordinates is obtained, which can be represented in a plane. With this, the common component lies perpendicular to this plane in the so-called γ component. Three-phase two-level VSC has 8 possible combinations of the switches—three binary signals { Sa 1 , Sb 1 , Sc 1 } = 0,1 yields 23= 8 possibilities—and thus, 8 switching vectors represent the modulation region—referred as switching vectors Sa 1,Sb 1,Sc 1 . Note that these combinations of switches can be positioned in a cube whose axes are abc as shown in Fig. 1.6. The αβ transformation projects these axes in the αβ plane in such a way that the common component ( a = b = c ) is no longer considered. In this way, any abc vector can be represented within this plane neglecting the common component. As a consequence, the switching vectors 000 and 111 appear in the same position, which exhibits that both positions have the same effect on the system performance. 1.2 Background and current state-of-art of grid-connected VSC 17 Following with the modulation approach, the two-dimensional vector is located inside the modulation region in αβ , which turns out to be an hexagon, where all possible switching states are represented. Then, the easiest solution, is to consider the three closest switching states, which are weighted in such a way that the resultant linear combination matches the input vector. This procedure is carried out every switching time ( Ts ), and the selected switching states are sequenced according to this linear combination in such a way that the average value of the output voltage over Tsequals the input one. Figure 1.6 Three-dimensional representation of the αβ transformation from abc coordinates, and corresponding space vector hexagon with one vector in the first sextant as example. Figure 1.6 depicts the αβ plane and its relation with the abc coordinates, along with the space vector hexagon. As an example, in Fig. 1.6, a vector xαβ is located inside the hexagon and the switching vectors ( 100 ), ( 110 ) and ( 000 / 111 ) are linearly combined to represent it. For this, the duty ratios of each switching vector— d1 for vector (100), d2 for vector (110), and d3 for either vector (000) or (111)—must be computed such the following constraints are fulfilled: xαβ =d1d2Tabc→αβ[100]T Tabc→αβ[110]T(1.9) d1+d2+d3= 1,(1.10) where xαβ is the normalized vector of the desired output voltage transformed into the αβ reference frame, i.e. xαβ :=vαβ/vdc from (1.8) —note that the desired output voltage vi is the output of the controller. This normalization comes from considering that signal Si 1= 1 generates an output viN =vdc/2 , and viN =−vdc/2 otherwise (see Fig. 1.2 and Eq. (1.5) ). In this way, the output voltage vector can be normalized by dividing it by vdc , so the duty ratio is directly related to this value. Equation (1.9) guarantees the proper vector modulation, and (1.10) comes from the definition of duty ratio. With this procedure, any vector that lies inside the hexagon can be represented while fulfilling the previous constraints. There is an inherent degree of freedom in this procedure once the switching vectors are selected and its corresponding duty ratios are computed, that is the time-sequencing of such vectors. Usually they are sequenced in time following a clockwise or counter-clockwise scheme in the αβ plane, but some applications present different approaches to achieve additional objectives [29,30]. 18 Chapter 1. Introduction This scheme of SVM can be further extended for converters with more switching states following the same principle. For those cases, the hexagon should include more regions and switching states such that all feasible switching combinations are covered. Additionally, given the increased complexity of these extended converters, the vector selection is not restricted to the three-nearest ones, but any linear combination can be considered as long as the output voltage vector is properly modulated and the sum of all corresponding duty ratios is equal to 1. Optimal PWM schemes There is also a modulator category called optimal PWM schemes, where the switching pattern is computed beforehand using a set of trigonometrical equations. These techniques decide the number of commutations m considered per period, that is the number of instants where the switching devices must commute, and solves a system with m equations such those instants are determined. These strategies are commonly used for high-power applications where low number of commutations are desired due to the large switching losses they may have. In this regard, the larger the m , the more control over the output voltage harmonic spectrum. The most common modulation is the selective harmonic elimination PWM (SHE-PWM), where the switching instants (referred as switching angle over the grid period αm ) are computed such that the main component has a desired amplitude, and m−1 harmonics are removed. Alternatively, other objectives can be sought, such as grid compliance with the selective harmonic minimization (SHM-PWM) method, or overall reduction of the total harmonic distortion with optimal pulse patterns (OPP-PWM). They all use the Fourier decomposition of the periodical waveform to set the system of equations, while the αm variables are obtained through numerical methods—for low values of m —or optimization algorithms such as linear programming or particle swarm optimization—for larger values of m. 1.2.4 Typical controllers for grid-connected power converters This subsection is devoted to present some of the most typical controllers used for power converters—being most of them linear—, their usual control objectives and how they are implemented. As it was stated previously, it is necessary to use a modulator for these approaches as an interface between the continuous output of the controller and the discrete switching input signals of the power converter. As it is shown in Fig. 1.3, it is common to implement a linear feedback controller scheme [31], where a system variable reference var∗ is tracked. For this, the controller inputs the tracking error e and outputs the desired average value of the system output—usually expressed as a normalized value that is related to the duty ratio d . This value is later introduced into the modulator to generate the switching pulses of the system. However, there exists some sources of error represented as disturbances in Fig. 1.7a). In this regard, the disturbances are shown as, on the one hand, f var to represent possible noise that can appear during the measuring process, and, on the other hand, ˜y to represent the modifications caused by the hardware and software implementations (quantization errors, delays, hardware constrains, etc.). To analyze such effects from the control perspective, Fig. 1.7b) is shown, where the system is replaced by its model G(s)and the different input-output relationship can be obtained. 1.2 Background and current state-of-art of grid-connected VSC 19 Figure 1.7 Scheme of the common linear feedback controller with the sources of error represented as external disturbances. (a) Scheme with modulator, power converter, measuring and sources of disturbances; (b) Generic scheme using the system model G(s). In this figure, the measured system variable to regulate is v , whose reference value is v∗ , and tracking error ˆv ; the control input is ¯u ; the control signal that inputs the system is u , and the system output variable is ¯v . The disturbances generated in the control and modulation stages, such as those related to the implementation procedure, are denoted as ˜u ; whereas the disturbances generated in the measuring process or due to modelling errors are denoted as ˜v. Consequently, the following transfer functions can be obtained: v(s) = T(s)v∗(s)+Du(s)˜u(s)+Dv(s)˜v(s),(1.11) where T(s) is the tracking transfer function, Du(s) is the transfer function for disturbances in u , and Dv(s) is the transfer function for disturbances in v . Considering the closed-loop of Fig. 1.7, the transfer functions can be expressed in terms of the controller C(s) and the system model G(s)as: T(s) = C(s)G(s) 1+C(s)G(s)(1.12) Du(s) = G(s) 1+C(s)G(s)(1.13) Dv(s) = 1 1+C(s)G(s).(1.14) These equations exhibit that the controller design determines not only the tracking response, but also the disturbance rejection. For those cases where a modulator is being used, it is worth mentioning that the controller bandwidth is usually much lower than the switching frequency ( fs ) of the system. The reason is twofold: the modulator introduces additional components in the output spectrum around the switching frequency or its multiples, which could affect the response in the closed-loop dynamic if any of these components lies 20 Chapter 1. Introduction within the controller bandwidth; and indirectly due to the fact that digital systems usually synchronize the system execution and sampling with the switching frequency of the PWM, therefore it is desired to have relatively high values of fs. In the following, the most seen linear controllers used in the literature will be presented: the proportional-integral (PI) controller and the proportional-resonant (PR) controller. PI Controller It is one of the most used controllers in control engineering due to its simplicity and good performance. Its continuous and frequency domain well-known expressions are: y(t) = Kpu(t)+KiZt 0 u(τ)dτ , CPI(s) = Kp+Ki s,(1.15) which is the addition of a proportional part of the input and its computed integral over time. Terms Kp and Ki are the controller parameters whose tuning is explained more in detail in subsection 1.2.4. This controller response is well suited for DC or constant magnitudes due to its high gain at low frequencies, while having the proportional gain to handle the transitory. The Bode diagrams of such controller for Kp= 1 and Ki= 1,10,100 are shown in Fig. 1.8. Nevertheless, the limited response of this controller to AC magnitudes, which are very common in grid-connected systems, requires to translate the controller signals from sinusoidal to constant values. For this, the system variables are expressed in the dq reference frame—which stands for direct-quadrature—also called synchronous reference frame. This reference frame rotates at the same frequency than the considered AC magnitude, and thus the magnitude expressed in these axes appears as a DC component. Then, the controller output can be translated back to the stationary reference frame. By including this change of reference frame, the PI controller can be used to compensate certain AC magnitudes. The dq vector is obtained as follows xdq =Tabc→dq xabc , Tabc→dq =r2 3   cos(θ) cos(θ−2π 3) cos(θ+2π 3) −sin(θ)−sin(θ−2π 3)−sin(θ+2π 3) √2 2 √2 2 √2 2   , (1.16) where θis the rotation angle of the AC magnitude. As it was mentioned in the SVM for three-phase VSC section, it is common to express the three-phase magnitudes in αβ following the transformation given in (1.7) . Considering that the αβ components are orthogonal, its transformation to the dq reference frame can be performed by just using the rotation matrix Lrot(θ): xdq =Lrot(θ)xαβ , Lrot(θ) = cos(θ) sin(θ) −sin(θ) cos(θ),(1.17) where xdq is the two-component vector expressed in the synchronous reference frame, and θis the angle of the AC magnitude that synchronizes the dq axes. 1.2 Background and current state-of-art of grid-connected VSC 21 Figure 1.8 (Left) Bode plot of PI Controller with Kp= 1 for different values of Ki= 10,100,1 . (Right) Bode plot of ideal PR Controller with Kp= 1 for different values of Kr= 102,103,10. In any case, the obtainment of such an angle can be performed by means of the application of a phase-locked loop to the grid voltage measurements. The following paragraph describes its most basic implementation. Phase-locked loop (PLL) To obtain the value of θ=ωgt used in (1.16) and (1.17) a phase-locked loop (PLL) scheme is used, which basically tracks the phase angle of the voltage measurements. The basic scheme usually comprises a phase detector (PhDet), a low pass filter (LPF) and a voltage controlled oscillator (VCO) [32]. The phase detector measures the phase difference between the PLL input and output, the low-pass frequency rejects the high-frequency components of this difference, and the VCO generates the output signal based on the filtered difference. The most basic configuration of synchronous reference frame PLL uses the Tabc→dq transformation that outputs the q component as the PhDet, a PI filter as the LPF, and an integrator as the VCO which outputs the grid angle θ that feedbacks the PhDet. This scheme is shown in Fig. 1.9. Figure 1.9 Basic scheme of a PLL for grid synchronization. 22 Chapter 1. Introduction Resonant controller Considering the problematic given by the PI controller for AC magnitudes, an alternative to use the PI and the dq reference frame is to modify the integral action of the PI controller in such a way that it acts as a resonator for a specific frequency ωr . With this, infinite gain in the controller response at ωr is achieved. This stage is known as resonant controller and, together with the proportional part, it has the following transfer function : CPR(s) = Kp+Krs s2+ω2 r ,(1.18) where Kr and ωr are the new control parameters for the resonant part. This controller expression comes from the expression of a PI controller in synchronous reference frame translated to the stationary one. For this, the following expression shows the relation when transforming from one reference frame rotating at ωto the stationary one C(s)Sync. =1 2(C(s+jω)+C(s−jω)).(1.19) where the frequency is shifted ±jω in the s domain. Indeed, a proportional-resonant controller tuned at ω in stationary frame is equivalent of two proportional-integral controllers each one in a synchronous reference frame rotating at ωand −ωrespectively [33] Kp+Ki sSync. =1 2Kp+Ki s+jω +Kp+Ki s−jω  =1 22Kp+2Kis s2+ω2(1.20) However, infinite gain for AC magnitudes could yield instability issues in the closed-loop scheme. Besides, any possible mismatch between the grid fundamental frequency with the established ωr could make the resonant part to not properly track the AC component. For this, the non-ideal PR is used instead, where a non-ideal integrator—previous to be shifted in frequency—is used: 1/s →1/(1+s/ωc) [34]. Therefore, when this integrator is shifted a frequency ωr and combined with the proportional part, the following transfer function for the non-ideal PR controller is obtained: CPRnon-ideal =Kp+Krωcs s2+2ωcs+ω2 r ,(1.21) where ωc is the cut-off frequency of the low-pass filter used for the non-ideal integrator, that is chosen to be ωcωr . As a result, the bandwidth of the resonant part is widened,—the larger the value of ωc , the wider the bandwidth—in spite of its magnitude response being more limited, but it is large enough to track the AC magnitude properly. Frequency-locked loop (FLL) In a similar way that the grid angle θ is required for the synchronous reference frame, the PR controller in stationary frame requires the knowledge of the grid frequency ωg . This can 1.2 Background and current state-of-art of grid-connected VSC 23 be achieved by means of a frequency-locked loop (FLL) which extracts the grid frequency from the grid voltage measurements. There are several FLL schemes. However, the FLL based on the second-order generalized integrator (SOGI) is one of the most accepted ones as it can be used in single-phase systems [35]. The SOGI performs as a band-pass filter with K as its gain and two outputs: one output ( v0 g ) has zero dB magnitude and no phase-shift for a specific resonant frequency, whereas the second one ( qv0 g ) achieves the same attenuation for the same frequency component but delayed 90 ◦ —which is referred as the quadrature output. Consequently, using the measured grid voltage vgα as input, its filtered component at ωg and its 90 ◦ -shifted version v0 gβ are obtained. The FLL scheme is integrated along the SOGI diagram as shown in Fig. 1.10, where a simple auto-tune block with gain γ is implemented to obtain the resonant frequency of the SOGI-QSG, which matches the grid frequency one (ωg). Figure 1.10 Basic scheme of a SOGI-QSG-based FLL for grid frequency obtention. Cascaded configuration This subsection is devoted to present one of the most typical control schemes of three-phase grid-connected VSC. This scheme is the cascaded-control loop shown in Fig. 1.11 where an outer control (OC) loop outputs the references for the inner control (IC) loop [36]. The principle that allows this is the difference between the dynamic responses, as the outer loop control bandwidth is much smaller than the inner loop control one, and thus it allows both controller to track their respective references without interfering in each other’s response. As shown in Fig. 1.11, the outer control loop computes the current references—whether in αβ or in dq reference frame—for the inner control loop, which implements a current controller to track them. The outer control loop can be designed to track the active and reactive power p and q , given their respective references (p∗,q∗) (Block 1). Alternatively, the active power reference p∗ can be regulated using a PI controller to make vdc to track its reference v∗ dc (Block 2). In the latter case, the current references can be computed from p∗and q∗by using the instantaneous power theory (IPT) [37]: p q=vgα vgβ −vgβ vgαiα iβ→i∗ α i∗ β=1 v2 gα +v2 gβ vgα −vgβ vgβ vgα p∗ q∗.(1.22) 24 Chapter 1. Introduction where the instantaneous active and reactive power and their references are denoted as p,q,p∗,q∗ , respectively. The current references inputs the inner control loop that is carried out either in synchronous reference frame such that idq →i∗ dq (Block 3) or in stationary reference frame iαβ →i∗ αβ (Block 4). In the first case, a PI controller is used together with a decoupling term wgL as it will be explained later. In the second case, the PR controller is used as long as the resonant frequency is tuned at the grid-frequency ωg . In any case, the outputs are transformed back to the abc reference frame and a feedforward term of the grid voltages vgabc is added (Block 5) as it will be explained later. Note that the reference frame transformation step inherits one degree of freedom, that is the one associated to the homopolar component, as it involves an R2 to R3 transformation. The resulting variables vabc are the desired output voltages to modulate, which are normalized using the dc-link voltage vdc and are input into the modulator such that the switching signals Sa 1,Sb 1,Sc 1 are generated. It is common to use the outer control loop to compute the current references in such a way that the the dc-link voltage and the reactive power reference are properly tracked, i.e. vdc →v∗ dc and q→q∗ . In the following, the dc-link voltage and AC current models along their typical controllers are exposed. dc-link voltage controller As it is shown in Fig. 1.11, one way to compute the active power reference p∗ is by regulating the dc-link voltage towards its reference. This is the case for AC/DC or DC/AC converters that use a capacitor as the DC storing element in the converter, whose voltage can be regulated adjusting the active power flow. In this regard, any mismatch in the subtracted AC and DC active power would necessarily affect the dc-link voltage value. For example, when the power flow that inputs the converter from the AC side is larger than the one subtracted from the DC side, the dc-link voltage increases. Therefore, the dc-link voltage steady-state condition is reached when the AC and DC power flows match. In order to model the dc-link voltage, it is assumed that the power converter has no losses and it has ideal devices. Therefore the instantaneous capacitor voltage equation results in Cdvdc(t) dt =idc(t) = iaSa 1+ibSb 1+icSc 1, which can be averaged over a switching period Ts using the duty ratio definition di= 1/TsRtk+Ts tkSi 1dτ as Cdvdc dt |Ts=iada+ibdb+icdc. Considering that the stored DC energy is equal to Cv2 dc/2 , the dynamic can be derived in terms of power as d dt Cv2 dc 2=vdcCdvdc dt =vdc(iada+ibdb+icdc) = iava+ibvb+icvc=p, (1.23) 1.2 Background and current state-of-art of grid-connected VSC 25 Figure 1.11 Scheme of the typical cascaded control loop used for grid-connected VSC with CCs at both reference frames, two options for power objectives, and modulation stage. 1: Outer control loop based on external active and reactive power reference. 2: Outer control loop based on external reactive power reference and dc-link voltage regulation. 3: Inner control loop in synchronous reference frame based on PI controller. 4: Inner control loop in stationary reference frame based on PR controller. 5: Grid voltage feedforward term. where vi=divdc was recalled from the normalization step, and the instantaneous active power theory is applied [37]. In this way, the transfer function is given as: Gdc(s) = vdc(s) p(s)=1 VdcCs,(1.24) where vdc can be approximated by the value of Vdc at the desired operating point. Consequently, if it is assumed that the inner control loop would make p→p∗ , variable v2 dc would be regulated towards v∗ dc 2 by means of a PI controller whose output is p∗ . At the same time, variable q∗ can be set externally to fulfill other control objectives without affecting the dc-link voltage. 32 Chapter 1. Introduction Figure 1.14 Bode plot of the IC open-loop of a generic system when no current control is applied, when a PI controller is applied and when a non-ideal PR controller is applied. Lastly, the value of Kr can be obtained by making the minimum desired phase margin of the open-loop around the resonant frequency ( PM∗ res ) to be within [30,60]◦ . Considering the output phase of PR controllers, the minimum phase margin is given immediately after the resonant frequency ωr (see Fig. 1.8, where a peak of -90 ◦ is given on the right hand side of ωg ). Similarly, with non-ideal PR controllers, where the bandwidth is widened by ωc, the minimum phase is given at ωr+ωc. Therefore, making ∠GICol (j(ωr+ωc)) = π−PM∗ res 2π 360,(1.46) would result in a design value for Kr . It is worth mentioning that, for non-ideal resonant controllers, the cut-off frequency ωc for grid-connected converters is recommended to be selected in the range of 5-15 rad/s [41]. A tuning process example using a Bode plot is shown in Fig. 1.14, where the IC open-loop Bode plot of a generic system is shown when no current controller (CC) is implemented. Firstly, the value of ωbw is determined in such a way that PM ∗ bw is achieved for that frequency. At this point, it is common to assume that the resonant term would have no effect on the phase output, despite the fact that the figure shows that the resonant term adds a slight phase-shift at ωbw . Afterwards, the value of Kp is determined to make ωbw the crossover frequency of the open loop. Lastly, Kr is designed to achieve PM ∗ res in the lowest phase around ωg . Note that this model uses a non-ideal resonant controller. Additionally, the open-loop Bode plot when a PI is used is also included. In this case, the Kp and ωbw tuning process follows the same procedure, and Ki is obtained through making Ti=Tcas mentioned in (1.42). dc-link voltage controller 1.2 Background and current state-of-art of grid-connected VSC 33 Using the simplified model of the inner control loop in (1.25), GOCol (s) = (Kps+Ki) s2VdcC(1+3Tss)=Kp(1+Tis) Tis2VdcC(1+3Tss), Ti=Kp Ki ,(1.47) where Ti is the integral time constant. It is worth mentioning that the value of Ti should be tuned to be much larger than the IC time constant. Then, the crossover frequency of GOCol (s) can be designed to be ωco = 1/p3TsTi , as the maximum phase margin will be obtained. Therefore, the control parameters are given by Kp=VdcC p3TsTi , Ki=VdcC q3TsT3 i (1.48) where the integral time constant Ti has to be tuned in such a way that the controller bandwidth lies between 1/50 and 1/10 of the one of the inner control loop, i.e ωco ≈ α/(3Ts)with α∈[1/10,1/50]. Alternatively, [42] addresses this tuning process from several practical perspectives. 1.2.5 Current controller for unbalanced grid voltage conditions It is also worth mentioning that the above analysis is based on a balanced three-phase grid. However an unbalanced three-phase grid voltage may require further considerations in terms of frequency response of the inner control loop. There are some unbalancing compensation strategies that inject non-fundamental components in the current references, and thus, the current controller must be able to track such components. In this regard, [43] reviews the stationary and synchronous current control reference frames for these particular conditions of the electrical grid, and presents a theoretical comparison of the two current controllers explained above and others recently published. This section will exhibit the characteristics of an unbalanced grid, how it is tackled from the control perspective of the converter, and some current controllers that are suitable to work under these grid conditions. Unbalanced grid voltage conditions A balanced three-phase grid is composed of three symmetrical sinusoidal voltage components with the same amplitude that are 120 ◦ -shifted between each other. In that case, their expressions are vga =Vmsin(ωgt), vgb =Vmsin(ωgt−2π 3), vgc =Vmsin(ωgt+2π 3),(1.49) where Vm is the voltage amplitude, and ωg is the grid frequency in rad/s. However, the parasitic resistance of the transmission lines, non-linear characteristic of the loads, different kind of faults, and the unmatched power demand of each phase make a real three-phase grid to present an unbalanced distribution, that is, the previous assumptions are no longer true. Some reasons about why it is important to keep a grid balanced are the following: 34 Chapter 1. Introduction • The sensitivity of certain grid-connected equipments that work under a limited range of voltage and frequency. • Some topologies of drives are synchronized with the grid frequency, and therefore, its performance is highly dependant on the state of the grid balance. • It is common to provide household costumers with single-phase energy, therefore an unbalance could make one or more phases to fail in the proper supply. • Additional losses are generated the larger the unbalance is. For example, the common component, i.e. the component that results from adding the three-phases, is a wellknown source of additional heating for many drives used in the industry. In fact, the grid code standard defines a certain range of allowed unbalance, out of which, the supply might be suspended until the source of the unbalance is corrected. A common approach to model such unbalance is by considering the Fortesque theorem. It states that any set of N unbalanced phasors—a vector with magnitude and phase—can be expressed as the sum of N symmetrical sets of balanced phasors, for values of N that are prime [44]. In this way, any unbalanced three-phase grid voltage can be expressed as the addition of a set of three balanced positive-sequenced voltages, a set of three balanced negative-sequenced voltages, and a set of three zero-sequenced voltages. That is,   vga vgb vgc =  Vasin(ωgt+φa) Vbsin(ωgt+φb) Vcsin(ωgt+φc)  =  Vpsin(ωgt+φp) Vpsin(ωgt+φp−2π 3) Vpsin(ωgt+φp+2π 3)  | {z } Positive +  Vnsin(−ωgt+φn) Vnsin(−ωgt+φn+2π 3) Vnsin(−ωgt+φn−2π 3)  | {z } Negative +  Vz Vz Vz  |{z} Zero ,(1.50) where Va,Vb,Vc and φa,φb,φc are the respective individual amplitude and phase of each phase a,b,c ; whereas Vp,Vn,Vz and φp,φn are the respective amplitude and phases of the balanced phasors in positive, negative and zero sequence. The zero sequence is also referred as common or homopolar component in the literature. With this representation, the ideal scenario is where Vn= 0 and Vz= 0 , and thus, some approaches attempt to compensate the presence of the negative and zero component in such a way that only positive sequence appear in the voltage grid. It is worth mentioning that, despite the formulation (1.50) that has been given for grid voltages, a similar decomposition can be applied to any three-phase variables: phase currents, voltage and current harmonics, etc. Current reference generation for unbalanced grids The only way a VSC can modify the grid voltage at the point of common coupling (PCC) is by interacting with the grid impedance using the injected phase currents. Considering that the flow of current through an impedance generates a voltage drop, the phase currents can be modified accordingly to generate a voltage drop that benefits the unbalance compensation of the grid voltage at the PCC. That is, from the VSC, to inject a certain phase current 1.2 Background and current state-of-art of grid-connected VSC 35 waveform into the grid that interacts with the existing impedance between the VSC and the PCC in such a way that the voltage drop compensates in some extent the negative and zero sequence detected at the PCC. Generally, these strategies are implemented in VSCs working as rectifiers. Recalling the instantaneous power theory [37], which establishes the relation between the instantaneous active and reactive power and the grid voltages and currents, the presence of negative or zero sequence components in the grid affects the power variables as well. Indeed, a balanced phase currents with unbalanced grid voltages yield fluctuations in the power flows. Nonetheless, in a three-phase three-wire system there is no presence of zero sequence as the Kirchhoff’s law has to be fulfilled, i.e. ia+ib+ic= 0 . Applying the same sequence decomposition given in (1.50) to the phase currents—using Ip,In,Izand σp,σn,σz as the positive, negative and zero sequence amplitude and phase of the currents, respectively—, and expanding the instantaneous active power expression, p=vgaia+vgbib+vgcic=3 2(IpVpcos(φp−σp)+InVncos(φn−σn) +IpVncos(φn−σp−2ωgt)+InVpcos(φp−σn+2ωgt)) =3 2(IpVpψpp +InVnψnn +IpVn(ψnp cos(2ωgt)+ϕnp sin(2ωgt)) +InVp(ψpn cos(2ωgt)−ϕpn sin(2ωgt)) (1.51) ψpp =cos(φp−σp); ψnn = cos(φn−σn); ψnp = cos(φn−σp) ϕnp =sin(φn−σp); ψpn = cos(φp−σn); ϕpn = sin(φp−σn) where the zero sequence has been neglected given the explanation above. Note from (1.51) that the presence of a negative sequence component, whether in the voltages ( Vn6= 0 ) or phase currents ( In6= 0 ), generates oscillations in the active power at twice the grid frequency. The same conclusion can be applied to the instantaneous reactive power given that q=v0 gaia+v0 gbib+v0 gcic, where v0 gi refers to the 90◦-lagged version of vgi [45]. Using (1.51) and its analogue for the reactive power, the current reference generation stage can be adapted to take the presence of negative sequence in the grid voltage into account. It is worth mentioning that expression (1.51) , applied to q as well, can be translated to the synchronous reference frame dq as p=3 2((vgdqp)Tidqp+(vgdqn)Tidqn +((vgdqp)Tidqn+(vgdqn)Tidqp)cos(2ωgt) +((Jvgdqp)Tidqn+(vgdqn)TJidqp)sin(2ωgt)) (1.52) q=3 2((vgdqp)TJidqp−(vgdqn)TJidqn +((vgdqp)TJidqn−(vgdqn)TJidqp)cos(2ωgt) +((vgdqp)Tidqn+(vgdqn)Tidqp)sin(2ωgt)) (1.53) 36 Chapter 1. Introduction J=0−1 1 0 . Thus, an unbalanced set of references for a three-phase three-wire system in synchronous reference is composed of four variables: i∗ dp,i∗ qp,i∗ dn,i∗ qn . In the following, several strategies that have been developed in the literature to generate these references pursuing different objectives will be presented. The easiest approach, commonly carried out in microgrids and transmission networks where the effect of grid impedances is more noticeable, is known as the droop control [46]. This technique is more focused on compensating voltage unbalances generated due to grid faults and it only uses positive-sequenced phase currents, i.e. the negative sequence component references are zero. By modifying the reactive power that flows through the line, the phase currents interact with the grid impedance, compensating the voltage drop. This strategy can be formulated as i∗ qp=Kdroop|Vnom −min(Va,Vb,Vc)|·Inom (1.54) Kdroop ≥2, where Kdroop is a fixed value that acts as a control parameter, min is the minimum function, and Vnom and Inom are the nominal phase voltage of the grid—the desired value—and the nominal current of the VSC. Note that iqp is directly related to the reactive power, and therefore this strategy modifies the reactive power reference to compensate the voltage unbalance. Despite the fact that this is a common strategy, it does not take into account the presence of negative sequence components in the grid. Another approach given in [45] considers an unbalanced input impedance—the impedance between the PCC and the VSC connection—and unbalanced grid voltage to formulate the instantaneous active and reactive powers using the so-called unified VSC model. For this, the expressions of the power oscillations at twice the grid frequency are presented as a function of the positive and negative sequence components of the grid voltages and phase currents, and the impedance parameters. This reference also exposes the fact that the expression that multiplies cos(2ωgt) in p has the same magnitude than the one that multiplies sin(2ωgt) in q , and similarly occurs with the term that multiplies sin(2ωgt) in p and the one that multiplies cos(2ωgt) in q (see (1.52) – (1.53) ). In the latter case, both have the same magnitude but opposite signs. Therefore, considering the four degrees of freedom of the current references, four objectives are established: •Fulfilling p=p∗. •Fulfilling q=q∗. •Cancelling the expression that multiplies cos(2ωgt)in (1.52). •Cancelling the expression that multiplies sin(2ωgt)in (1.53). As a result, the current references i∗ dp,i∗ qp,i∗ dn,i∗ qn are obtained—set of equations expressed in (39) in work [45]. This current reference generation method exploits the benefits of defining the current references with no constraints as both power ripples are suppressed. However, harmonics 1.2 Background and current state-of-art of grid-connected VSC 37 at 3ωg and 5ωg will be present in the grid current references. Consequently, the phase current references would not only have positive and negative sequence components, but also harmonics at those frequencies. Additionally, these harmonics have to be properly tracked by the current controller to fulfill the power oscillation suppression, which is an additional challenge for the current control design. Nevertheless, [45] proposes the use of parallel resonant controllers tuned at these frequencies for such purpose. Alternatively, [47] defines a current reference generation strategy where the main objective is the voltage support at the PCC, i.e. the reduction of the negative sequence component in the grid voltage. This reference is based on the proposal given in [48], where the developed analysis is based on a mainly inductive transmission network, and thus it is expected that the phase currents interact with the grid inductance to provide voltage support. In contrast, authors in [47] expand the same analysis by taking into account the resistive-inductive ratio ( R/X ) of the network—while high-voltage networks are mainly inductive ( R/X = 0 ), low-voltage networks are mainly resistive ( R/X 0 ). Nonetheless, both strategies present two inter-dependant tuning parameters k+ and k−= 1−k+ , that act as weighting factors on which voltage sequence to consider for the current reference generation. The expressions are given in the αβ reference frame as i∗ α=2 3p∗ k+vgαp+R √R2+X2(k−vgαn) k+V2 p+R √R2+X2(k−V2 n)+2 3q∗ k+vgβp+X √R2+X2(k−vgβn) k+V2 p+X √R2+X2(k−V2 n)(1.55) i∗ β=2 3p∗ k+vgβp+R √R2+X2(k−vgβn) k+V2 p+R √R2+X2(k−V2 n)+2 3q∗−k+vgαp−X √R2+X2(k−vgαn) k+V2 p+X √R2+X2(k−V2 n), (1.56) where vgαp,vgβp,vgαn,vgβn are the αβ instantaneous grid voltage values for positive and negative sequences, respectively; whereas R and X are the estimated resistance and inductance between the VSC and the PCC. In this way, parameters k+ and k− allow the current reference strategy to tune the amount of negative sequence current injected to the grid to provide voltage support: k+= 1 generates balanced phase currents not providing any voltage support, whereas lower values of k+ increases the negative sequence current injection that interacts with the network impedance providing grid voltage equalization. Sect. VII of work [49] presents the current reference expressions for the negative sequence under different scenarios of grid faults. These expressions are given in the dq reference frame and they aim to neglect the active power ripple in order to avoid ripples in the dc-link voltage. Alternatively, [50] defines two simple current reference generation strategies: the first one aims to provide the desired power with no negative sequence current, while the second one aims to reduce the active power oscillation by means of injecting negative sequence current. Similarly, authors in [51] expand this idea by using a tuning parameter K∈[−1,1] that weights between three possible objectives: reactive power ripple suppression ( K=−1 ), only positive sequence currents ( K= 0 ), and active power ripple suppression ( K= 1 ). The expressions derived for the current reference 38 Chapter 1. Introduction obtention are the followings     i∗ dp i∗ qp i∗ dn i∗ qn    =2 3    vgdp/D vgqp/E vgqp/D −vgdp/E vgdn/D vgqn/E vgqn/D −vgdn/E    p∗ q∗(1.57) D=v2 gdp+v2 gqp−K(v2 gdn+v2 gqn) E=v2 gdp+v2 gqp+K(v2 gdn+v2 gqn). Note that making K= 0 is equivalent to the first strategy presented in [50], while making K= 1 is equivalent to its second strategy. Similar to the previous method, depending on the aimed objective, [52] tunes the conductance g and susceptance b for each sequence to determine the current references from its corresponding grid voltage. That is, the values of g+,g−,b+ and b− are tuned depending on the pursued objective: active power ripple suppression, reactive power ripple suppression, or balanced phase currents. Defining the relation between the negative and positive susceptance and conductance respectively as kg=g−/g+ , kb=b−/b+ , the reference currents are defined i∗ dqp=g+vgdqp−Jb+vgdqp(1.58) i∗ dqn=kgg+vgdqn−Jkbb+vgdqn(1.59) g+=2 3 p V2 p+kgV2 n ;b+=2 3 q V2 p+kbV2 n , where it can be seen that a similar expression than the one shown in (1.57) is given. Indeed, parameters kg and kb can be fixed to pursue the same objectives than the previous strategies: kg=−1,kb= 1 yields no active power ripple, kg= 1,kb=−1 yields no reactive power ripple, and kg= 0,kb= 0 yields balanced phase currents. In contrast to [51], there is an additional degree of freedom given the fact that there are two parameters to be tuned. This degree of freedom is used in this paper to carry out a current limitation strategy where the maximum amplitude of the phase currents is managed by clamping both kg and kb during online operation. Current controllers for unbalanced grid conditions Some of the previous strategies that provide voltage support define a nonzero magnitude for the negative sequence components of the current references ( i∗ dqn6= 0 ). Then, it is expected that the current controller (CC) can track such magnitude when implemented in a closed-loop scheme. For the balanced case, where only positive sequence components of the current references are given, two common CCs were previously explained: the PI controller using synchronous reference frame, and the PR Controller using stationary reference frame. These controllers are valid to track DC magnitudes, in the case of the PI-based, and AC magnitudes at a specific frequency, for the PR-based. However, in the case of unbalanced 1.2 Background and current state-of-art of grid-connected VSC 39 grid voltage, the existence of negative sequence components in the current references requires the frequency response of the CC to offer a high gain at this negative frequency in order to achieve negative-sequence tracking capabilities. CCs in synchronous reference frame In order to implement the PI controller as a CC, the synchronous reference frame dq is used, where the AC magnitudes at the fundamental frequency are transformed to DC magnitudes by means of using a rotating reference frame. However, given that this transformation implies a rotation at the fundamental frequency ωg , any other AC magnitude with different frequency ω is seen in the synchronous reference frame as an AC magnitude with frequency ω−ωg . Then, the negative sequence component appears in the synchronous reference frame as an AC magnitude at 2ωg , and thus the PI controller alone does not suffice to track this magnitude. In this regard, several CC strategies have been proposed in the dq reference frame. Double synchronous reference frame One approach is to use the concept of double synchronous reference frame where the positive and negative sequence components are treated separately as DC magnitudes. Firstly, the measured currents in abc are transformed using two synchronous reference frames: the positive sequence reference frame rotates counter-clockwise (and thus Tabc→dq(θ) is applied), whereas the negative sequence reference frame rotates clockwise (and thus Tabc→dq(−θ) is applied). Afterwards, the 2ωg oscillations that appear in each reference frame due to the opposite component presence should be eliminated. One way is by means of a low-pass filter, but it also filters out the reference components that are above the cut-off frequency and limits the closed-loop control response. Alternatively, notch filters tuned at 2ωg are an effective way to get rid of this specific frequency. In any case, the phase currents, initially measured in abc as AC magnitudes, are separated into the positive and negative sequence components as DC magnitudes in each synchronous reference frame. This process can be expressed mathematically as follows idp iqp=Filter Tabc→dq(ωgt)  ia ib ic  ;idn iqn=Filter Tabc→dq(−ωgt)  ia ib ic  , where Filter is the function that represents the used filter. This process is also known as current decomposition or current sequence separation. Hence, the common strategy of using a PI controller to regulate the currents can be adopted as both sequences are DC magnitudes. Consequently, the double synchronous reference frame uses four PI controllers, two for each component in the positive and negative sequence reference frames [53]. It is worth mentioning that the requirement of the sequence current separation stage introduces additional delays and undesired resonances into the closed-loop control. That is why, some works aimed to implement the same strategy of the double synchronous reference frame but neglecting the sequence current extraction stage as it will be shown later in this section. As an alternative, [53] uses the so-called decoupled dual synchronous reference frame where the ripples from each component are subtracted by means of low-pass filtering and 40 Chapter 1. Introduction rotating the opposite component magnitude. Thanks to this, the required filter is not placed in the forward path of the currents, and it is translated as a feedback path to uncouple each sequence from the opposite. In this way, the dynamic limitation of (1.2.5) is avoided. The expression for this sequence current decomposition is the following idp iqp=Tabc→dq(ωgt) ia ib ic −Lrot(2ωgt)LPFidn iqn (1.60) idn iqn=Tabc→dq(−ωgt) ia ib ic −Lrot(−2ωgt)LPFidp iqp,(1.61) where LPF refers to the low-pass filter function, and Lrot(θ) refers to the rotation matrix given in (1.17) . Note that the bandwidth of each LPF has to be tuned below the 2ωg ripple in such a way that only the DC magnitude is extracted. Therefore, the current references can be properly tracked by means of PI controllers. Another alternative presented in [51] avoids the sequence current decomposition stage while still using the two sequence reference frames. However, instead of considering the references as pure DC magnitudes, it adds the opposite sequence current references. That is, i∗ dp i∗ qp0=i∗ dqp+Lrot(2ωgt)i∗ dqn(1.62) i∗ dn i∗ qn0=i∗ dqn+Lrot(−2ωgt)i∗ dqp(1.63) where i∗ dqp0 , i∗ dqn0 are the computed references with the opposite sequence included that input the CC. This approach skips the sequence current decomposition while still keeping uncoupled the positive sequence component control from the negative one. Note that this approach has ideally the same effect at steady-state on the current tracking error f idq =i∗ dq − idq than the one presented in (1.60) – (1.61) , as LPF(idqp) = i∗ dqp and LPF(idqn) = i∗ dqn are fulfilled whenever the current tracking is properly achieved. Consequently, an oscillatory term (2ωgt) is added to the references. However, the controller is not required to track it, as it is an oscillation that will appear in the current magnitudes given that the opposite sequence DC magnitude is properly tracked. Due to this, PI controllers in the double synchronous reference frame are still good candidates to achieve proper tracking of both positive and negative sequence components. In [51], the closed-loop behaviour of this proposal is analyzed in such a way that the maximum possible gains for the PI controllers are obtained. Lastly, the CC presented in [54] ignores the current reference of the negative sequence components, but instead it tries to compensate the dc-link voltage oscillation. For this purpose, an AC signal with amplitude MAC , phase αAC and frequency 2ωg is added to the angle of the output voltage vector vdq to be modulated. The amplitude MAC is computed from the extracted negative sequence components of the currents—using the 1.2 Background and current state-of-art of grid-connected VSC 41 negative synchronous reference frame plus a notch-filter to reject the 2ωg ripples—which later inputs a PI controller. The term cos(2ωgt+αAC) is computed from the 2ωg ripple extracted from the positive sequence reference frame by means of another notch filter. It is later proved that this oscillation in the output angle compensates for the active power ripple, and thus the dc-link voltage oscillation. Single synchronous reference frame Alternatively to using two synchronous reference frames, PI controllers along with resonant terms can be used to track specific harmonics [33,55] in only one reference frame. In this regard, the negative sequence component appears in the positive synchronous reference frame as a magnitude at 2ωg , and therefore a resonant term at this frequency can be used to achieve tracking capability. Thus, by using (1.62) to integrate both sequence references into one, the previously presented synchronous scheme with PI controller can be used with the addition of a resonant term tuned at 2ωg. i∗ dp i∗ qp0=i∗ dqp |{z} DC magn. +Lrot(2ωgt) DC magn. z}|{ i∗ dqn | {z } AC magn. (1.64) In contrast to [51], this method uses two PI controllers to track the DC magnitudes of i0 dqp , and two resonant terms to track the AC magnitudes, while using only one synchronous reference frame. This scheme can be potentially used to track other harmonic references or to neglect their appearance in the current output. However, it is necessary to consider that a positive harmonic nωg would appear in the positive synchronous reference frame as a (n−1)ωg harmonic, while a negative harmonic nωg would appear as a (n+1)ωg one. Given that the typical low-order harmonics, the 5th and 7th ones, are respectively negative and positive sequences, they appear in the synchronous reference frame as a −6ωg and a 6ωg components. Therefore, two resonant terms are required in order to track/compensate such components. Following the scheme of PI+Res in single reference frame for positive and negative sequence tracking, the CC transfer function results in CC(s) = Kp+Ki s+Krs s2+4ω2 g =(s2+4ω2 g)(Kps+Ki)+Krs s(s2+4ω2 g),(1.65) which applied to the closed-loop transfer function given in (1.34) yields GICcl (s) = ((s2+4ω2 g)(Kps+Ki)+Krs)Tc L(1+1.5Tss)(1+Tcs)s(s2+4ω2 g)+((s2+4ω2 g)(Kps+Ki)+Krs)Tc . (1.66) 48 Chapter 1. Introduction contrary, passive balancing or natural balancing does not require a voltage sensor for each capacitor nor additional control loops by guaranteeing that the duty ratios of each level are evenly distributed [70]. With this, the power flow between different capacitors is naturally balanced, and the analysis of the system dynamics proves that any external disturbance would make the system to converge naturally to a balanced situation. Natural balancing is usually achieved by means of carrier-based modulations. Cascaded and Modular converters Cascaded converter refers to those multilevel configurations that are based on a serial connection of several single-phase converters [71]. In contrast to the previous topologies, each of these converters has its own dc-link, allowing the cascaded configuration to be seen as a serialized set of independent power modules. Some of the most obvious advantages are high modularity and scalability, easy maintenance, replication of control structure and modulation among power cells, and robust operation due to the possible inclusion of redundant power cells [72]. In spite of allowing the use of switching devices with much lower voltage rate, there is an obvious increase in the associated electronic, i.e. gating drives, optical signals, ADCs, etc., which may compromise the benefits of such converters. Needless to say that the power cells inside one phase can be of different topologies leading to hybrid cascaded configurations with some distinctive features of the involved power cells. Regarding the redundancy in the output voltage generation, the power cells that have the same dc-link voltage can be switched indifferently, resulting in a more numerous amount of redundant switching vectors. In fact, it is common to use sorting algorithms that takes the DC voltage of each cell into account and indicate which cells should be prioritized in the connection according to the phase current. Nevertheless, the redundancy in these systems highly depends on the type of cells that are used. Moreover, there exists the so-called asymmetric cascaded converters where the power cells do not have the same dc-link voltage, and thus they can provide more voltage levels. Similarly to the previous FC topology, the use of asymmetric cascaded converters improves the output distortion while increases the complexity of the voltage balancing task. The most typical cascaded converter is the cascaded H-bridge (CHB) converter, which consists of serialized H-bridge cells per phase, where each cell has its own dc-link—either an isolated dc-source or a capacitor. Fig. 1.19 (left) depicts a five-level CHB for one phase i . Given that each H-bridge can output the dc-link voltage positively and negatively, a n level CHB consists of (n−1)/2 H-bridge cells. In [73] an hybrid cascaded converter configuration is presented, which uses a single-phase multilevel VSI—usually DCC or FC topologies—as the dc-link of a H-bridge in such a way that the generated output of the VSI can be modulated positively and negatively thanks to the action of the H-bridge. This scheme is depcited in Fig. 1.19(center) for a generic phase i. Alternatively to the cascaded converter, it is worth mentioning the modular multilevel converter (MMC) as it has become one of the most studied multilevel topology, specially for high-voltage direct current (HVDC) transmission systems. It shares the same principle of the cascaded converter by serializing DC/DC converters with isolated dc-links to provide either a single- or three-phase multilevel output voltage. In contrast to the CHB, the MMC is composed of two arms that connect the phase output with the positive and negative side 1.3 Background on multilevel power converters 49 Figure 1.19 Scheme of two cascaded and one modular converters for one phase: Cascaded H-bridge converters (left), Cascaded inverter with an NPC in the dc-link (center), Modular multilevel converter with half-bridge Submodules (right). Parallel connection of these schemes would build-up a n-phase system. of the dc-link respectively, and two buffer inductors that limit the passing current. The most common module used in MMC is the half-bridge circuit due to its reduced components and simple control. An scheme of a MMC with half-bridge submodules is shown in Fig. 1.19(right). Alternatively, H-bridge circuits, clamp-double circuits, three-level DCC or five-level cross-connected circuits are also considered as modules for MMCs [74]. 1.3.2 Modulation approaches for multilevel power converters This subsection shows some of the most common modulation approaches for multilevel converters, that is, the strategy in charge of commanding the gating of the switching devices. Recalling the modulation strategies exhibited in Sect. 1.2.3, a similar distribution can be made into carrier-based PWM, space vector modulation, and optimal PWM schemes. Carrier-based PWM Carrier-based PWM for multilevel converters are usually based on using several carriers in such a way that the comparison of the modulation signals with each carrier commands the generation of a level, output of a cell or gating of a switching device. Considering the existence of several carriers, their disposition is very determinant in the performance of the system. In this regard, two categories are generally considered: Phase-shift modulation (PS-PWM) and Level-shift modulation (LS-PWM). PS-PWM keeps the same amplitude of the carriers but shifts each additional carrier a certain angle in such a way that the switching signal generation are evenly distributed along the switching period. On the contrary, LS-PWM modifies the amplitude and bias of the carriers such that they are disposed at different levels covering the whole range of the modulating signal, which usually goes from −(N−1)/2 to (N−1)/2 , being N the number of considered levels, when it is normalized with respect to vdc/(2N). Particularly, the angle shift in PS-PWM, when using cascaded converters, depends on the type of power cells that is used. Assuming that unipolar modulation is used for 50 Chapter 1. Introduction H-bridges—two carriers that are 180 ◦ -shifted command the four switching devices of each H-bridge—, each set of carriers is shifted 180 ◦ / M , being M the number of used H-bridge cells. In contrast, MMCs with half-bridge submodules (SM)—only one carrier is required per SM—or H-bridge cells with bipolar modulation would shift each carrier 360 ◦ / M . In other words, PS-PWM shifts the carriers “horizontally”. For this, the power is distributed evenly between power cells as they are switched-on at the same frequency, which benefits the capacitor voltage balancing of cascaded or flying capacitor converters. Moreover, thanks to the phase-shift effect, the effective output switching frequency is N−1 times that of the power cells. The latter is taken into consideration to reduce the switching frequency of each power cell while keeping the same effective output switching frequency. Approach LS-PWM, on the contrary, shifts the carriers “vertically” in such a way that there are N−1 carriers in a N -level converter, each carrier associated to a level. With this, the output is set to the level whose corresponding carrier is immediately below the modulation signal—the lowest level is output in the case all carriers are above. There exist some variations depending on the phase disposition of the carriers, i.e. the “horizontal” disposition [24]: •Phase disposition (PD), where all carriers are in-phase. • Alternative phase opposite disposition (APOD), where the carriers are alternatively 180◦-shifted. • Phase opposite disposition (POD), where the upper half carriers are in-phase, and the lower half are 180◦-shifted. The differences between these depend on the multilevel system, however PD offers the best output harmonic distortion, and POD are especially suitable for limiting the circulating current in MMCs [74]. While PS-PWM is more suited for CHB and FC due to its inherent power flow equalization, which in fact assists on the capacitor voltage balance (natural balancing), LS-PWM can be used for any multilevel converter. An example of both modulations is shown in Fig. 1.20 for a 7-level converter, where the modulation signal, carrier disposition, and output voltage is depicted. The harmonic spectrum of the output waveform is also shown in Fig. 1.21, where it can be seen that the LS-PWM offers an harmonic spectrum centered around the carrier frequency, whereas PS-PWM have lower values of harmonic magnitude but more spread. For this example, the modulation signal is a fundamental component at 50 Hz, with a modulation index of 0.9—an amplitude of 0.9·3=2.7 —, which is properly modulated as it can be seen in the harmonic spectrum. Space-vector modulation for multilevel power converters Following the same principle than SVM for two-level converters, the control region, where all possible switching states are depicted (see Fig. 1.6), can be represented for multilevel converters. For this, the normalized value of the output voltage vector xαβ is considered as xαβ := vαβ/(vdc/(N−1)) , where N is the number of levels that the topology under consideration has. Similarly to the two-level topology, the switching vector represents the level to which each phase is connected in alphabetical order, e.g. ’324’ 1.3 Background on multilevel power converters 51 Figure 1.20 Phase- (left) and Level- (right) shift PWM approaches for a 7-level converter. PS-PWM have carriers with 1/7 k Hz and LS-PWM with 1 k Hz. The output signal is depicted below each set of carriers.. Figure 1.21 Magnitude spectrum of the output signal for Phase- (left) and PD Level-shift (right) PWM approaches shown in Fig. 1.20. means phase a is connected to level 3, phase b to level 2, and phase c to level 4. There is no exact nomenclature for the levels, and the literature usually range them either using [(−N+1)/2,(N−1)/2] , [1,N] or [0,N −1] . Nevertheless, this section will denote the levels from 1, being the negative side of the dc-link or the lowest level of voltage, to N being the positive side of the dc-link or the largest level of voltage. In any case, depending on what the reference for measuring the output voltage vi is, the duty ratio obtention of the switching vector has to be defined accordingly. Given that multilevel converters have more switching positions, the space vector region is no longer composed of 6 regions as previously shown in Fig. 1.6. Instead, the space vector region, seen as the αβ plane, incorporates as many inner hexagons as additional levels in such a way that all switching states are represented and evenly spaced. Again, this disposition comes from positioning each switching vector in the abc space, and then rotating the view such that it lies perpendicular to the αβ plane, so the common component is obviated. Due to the latter, the switching vectors that only differ in the common component, i.e. that yield the same phase-to-phase voltage, are made explicit as 52 Chapter 1. Introduction they lie superposed on the same point. These switching vectors are referred as redundant ones, and thus they can be considered in the output voltage vector modulation as the same one. However, they are specially relevant for capacitor voltage balancing tasks, as it will be mentioned later. Again, the modulation process consists in selecting and sequencing the switching vectors along a switching period to replicate the desired output voltage xαβ . This is achieved by means of computing the duty ratios of each of the involved switching vectors. Using M switching vectors, the following constraints have to be fulfilled 1 = M X m=1 dm(1.71) xα= [d1...dM]   [a1b1c1]TT abc→α . . . [aMbMcM]TT abc→α   ;xβ= [d1...dM]   [a1b1c1]TT abc→β . . . [aMbMcM]TT abc→β   , (1.72) where n= 1,...,N is the index of the N used switching vectors, and [ anbncn ] is the corresponding levels in the considered n switching vector. With this formulation, any number of switching vectors ( M ) can be utilized as long as the duty ratio constraints are fulfilled. Once the switching positions are selected and their duty ratios are computed, the sequencing and the redundant switching vector selection have to be carried out. Indeed, this process is not straightforward, and its proper design can achieve reduced losses, reduced distortion or elimination of common-modes in the output [30]. Every switching vector has a particular effect on the capacitor voltage balancing according to the levels it involves, and thus their selection determines how the voltage balancing is achieved. As it was mentioned previously, the redundant switching vectors achieve the same phase-to- phase output voltage but connect the output to different levels, and therefore the dc-link capacitors are charged/discharged differently. For example, consider switching vector ’221’ and its redundant one in a three-level converter ’332’. The first vector involves levels 2 and 1, whereas the second one involves levels 3 and 2. This means that the first vector will inject/subtract current to/from levels 2 and 1, while the second one will do so to/from the levels 3 and 2. Some SVM strategies base its capacitor voltage balancing in this fact without affecting the modulated output voltage. However, it is worth mentioning that the largest the module of the switching vector, i.e. those that are in the outer limits of the SV hexagon, have no redundant vectors, so the redundant switching vector strategy alone might not be enough to guarantee proper capacitor voltage balancing under some operating conditions [75]. For this, some strategies avoid using the three nearest switching vectors and aim at using more distant ones that have more redundant vectors available, and thus the capacitors can be properly balanced [76]. Alternatively, there exists the concept of virtual space-vector that is based on positioning additional switching vectors—called virtual vectors—that are a combination of other existing vectors, and thus their balancing capabilities can be taken into account [77,78]. 1.3 Background on multilevel power converters 53 In any case, as the amount of levels increases so does the complexity of the SVM as there are more switching vectors and more capacitors to balance. For this, several strategies have been developed to reduce the computational burden of this approach when used with more than three-level topologies [79,80]. To depict this, Fig. 1.22 shows the SVM hexagon for different levels where each point represents a switching vector—and its inherent redundant ones, where each step towards the centre adds one redundant position. Despite the fact that it is more common to find odd multilevel converters—due to the grid code limits for odd harmonics being higher than the even ones—, there exists multilevel converters with even number of levels. Figure 1.22 Multilevel space vector hexagon for different levels. Each crossing point represents one switching position. In spite of considering SVM and carrier-based PWM different modulations, there are several studies that proved that they are different ways of facing the same problematic. Indeed, it is shown that for a particular configuration of the carriers and the injection of a common component in the modulated voltage for CB-PWM, the phase-to-phase output voltage waveforms matches those of SVM [81]. Nevertheless, the SVM makes more explicit the possible alternatives when modulating a three-phase output voltage as there are infinite possibilities of sequencing the switching vectors—by spreading them along the period, changing the sequence order, weighting among different redundant vectors, etc. Obviously, by defining particular objectives—such as reduced output distortion, reduced common-mode, reduced switching losses—the sequencing is selected accordingly [82]. Optimal PWM Schemes This subsection exhibits that the modulations previously referred as Optimal PWM schemes (SHE) can be also used for multilevel converters. For this, the switching angle computation has to consider different level steps, which usually are sequenced consecutively in order to reduce the output voltage distortion [83]. Note that, for the two-level implementation, the switching angles are usually computed offline and stored in a look-up table (LUT), that is later used in online operation using the modulation index and the grid angle as inputs. Therefore, when the capacitor voltage balance task of multilevel converters have to be taken into account, a different LUT might need to be used instead depending on the balancing approach considered. 54 Chapter 1. Introduction Work [84] carries out a comprehensive review of different balancing approaches to be used for SHE. Initially, three stages in the SHE approach are clearly stated: Switching angle acquisition, where the LUT is called and the switching positions are determined; waveform generation, where the output waveform is constructed based on the previous switching angles; and optimal state selection, that selects the more appropriate switching vector according to the cost function defined. Furthermore, it differentiates eight balancing methods: self-balancing control, charge amount regulation, zero-sequence harmonic adjustment, redundant switching angle sets adjustment, angle modification, selective harmonic elimination model predictive control, space voltage vectors adjustment, and redundant states adjustment. The main difference between these balancing approaches lies in the stage where they take place and the variables they modify. If they take place in the first stage, the LUT is usually modified such that the switching angles take the balancing task into account. If they take place in the second stage, the switching angles are slightly modified according to the capacitor voltages and current measurements in order to deal with the balancing. In contrast, if they take place in the third stage, the voltage waveform has been already defined as the output voltage reference and the most suitable switching vector is selected such that it also takes the balancing into account—which is equivalent of using the redundant vector strategy. Nevertheless, finding a generalized and well-performing voltage balance approach for multilevel converters is a challenging task, given the noticeable differences that exist between multilevel topologies. Therefore, the most suitable balancing approach within SHE highly depends on the system topology and it has to be selected according to the target application. 1.3.3 Control without modulation This section exposes some controllers that do not have a modulation stage, i.e. the gating signals of the switching devices are directly generated from the output of the controller. Usually, the controller is designed to select the switching position that yields the lower value of a cost function, or reduce as much as possible a tracking error. In general terms, these controllers achieve faster transient operation at the cost of a more spread harmonic spectrum, in other words, the output frequency spectrum is not centered around particular frequencies—the switching frequency for CB-PWM, for example—but a random distribution is obtained instead. This is mainly due to the fact that the controller does not modify the switching position at a fixed rate, but instead selects the position that achieves the best performance according to the law formulation. For the case of multilevel converters, the voltage balance task is covered by considering how the capacitor voltages may diverge into the state variables that composes the tracking error or the cost function. In the following, some of the most well-known approaches that can be considered inside this category are explained. Hysteresis Control This strategy was originally implemented using analog controllers where the real magnitudes are sampled continuously, although there exists digital implementations nowadays. The most well-known approach is the hysteresis current control, where a hysteresis band is 1.3 Background on multilevel power converters 55 defined around each current tracking error and the switching output of the corresponding phase is changed whenever it crosses this band. Due to this, it requires continuous sampling in order to keep the current error within the band boundaries. However, a digital implementation would not allow a change in the switching action until the next sampling instant, and thus the tracking error of digitally-implemented hysteresis controllers will usually exceed the given boundaries. In the case of multilevel converters, there exists several approaches that arrange the bands differently. Nevertheless, they share the same principle, the use of several bands with different widths around the tracking error—known as the multiband strategy—in such a way that the output level consecutively increments or decrements whenever the tracking error crosses them. Paper [85] presents a compilation of these approaches and exhibits their main benefits and drawbacks. Note that this approach alone does not consider the capacitor voltage balance, and thus an external agent, either by software or hardware, is required. Direct Torque/Power control (DTC/DPC) Similarly to the previous control, the direct torque/power control tracks the torque/power references using hysteresis controllers and a LUT to select the most suitable switching vector according to the current state of the system. Direct torque control was proposed first and it is well-established in the industry due to its simple control structure, fast response and robust operation. Direct power control was proposed afterwards for grid-connected converters to track the active and reactive power directly. Both controllers use the same principle but for the tracked variables and the LUT generation. Obviously, the LUT generation is carried out offline and depends on the system topology. In terms of multilevel converters, the concept remains the same but the LUT generation have to consider all available switching vectors. Note that the principle of using redundant switching vectors for capacitor voltage balance can be applied in this approach [86]. Therefore, once the switching vector position is obtained from the LUT according to the variable tracking error, the more convenient vector among the redundant options can be selected. Alternatively, some approaches avoid the use of LUTs and implements other controllers instead to achieve the same goal. Despite the fact that they usually require a modulator, they have been mentioned in this subsection as they share the same objective than DTC/DPC. This is the case of [87], where a controller gives the optimum output voltage vector that is modulated either using the nearest switching state or through SVM. Similarly, paper [38] develops a model-based direct power control where linear controllers are applied to obtain the optimum output voltage vector that is modulated through SVM or CB-PWM. Again, redundant switching vectors can be used to achieve capacitor voltage balancing in both approaches. Finite-control-set model predictive controller (FCS-MPC) This approach is one of the controllers that is leading the trend in optimal nonlinear controllers due to the development and evolution of digital systems. They are based on 56 Chapter 1. Introduction a cost function that assists on indicating the optimal behaviour, and selecting the best switching vector by predicting the system state using model-based equations. For this, the objectives of the controller, namely dc-link voltage regulation, current tracking, minimum switching losses and capacitor voltage balance, are included in the cost function and all available switching actions are pondered with it, resulting in one switching vector having the minimum value, which is selected as the optimal one. This process is carried out every switching period to update the most suitable switching vector, and thus the controller performance highly depends on the switching frequency. Note that any system constraint or control objective can be formulated in the cost function, which is an advantage over other approaches as different objectives might be pursued [88]. The prediction horizon can be extended up to k switching events, which results in a controller with better performance. In this way, every switching instant, the controller computes the more convenient sequence of switching actions for the next k switching events, and selects the first one as the output. This controller can be easily adapted to multilevel converters by considering all possible switching actions and including the capacitor voltage balance objective inside the cost function [89]. Notice that some control objectives may be contradictory to each other, so it is necessary to tune weighting parameters to ponder the priority of such objectives. This type of controllers are generally used to enhance the system performance over the whole operation range of the system, especially under transient conditions. As a downside, the computational burden of this approach is larger than those that use a modulation stage, specially for multilevel converters as the whole set of switching actions have to be evaluated using the cost function. Besides, the number of required computations exponentially increases with larger values of prediction horizon. For this, some works aim to reduce the computational burden by including some simplifications on the prediction stage or by avoiding the evaluation of some switching vectors when consecutive horizons are considered [90,91]. Hybrid controllers Despite the fact that the controllers exhibited in this section of control without modulation take into account the discrete nature of the system and avoid the use of averaged models, i.e. the use of duty ratios, the approaches inside the category of hybrid controllers explicitly consider the continuous nature of the state variables, i.e. the voltages and currents. Similarly to FCS-MPC, they directly consider the switching actions to control the converter, and therefore they do not require a modulator. The main differences with FCS-MPC is that an embedded control is proposed in the formulation of the hybrid dynamical systems. From the control perspective, the modelling is approached taking into account the hybrid nature of the system, and this framework allows, under some assumptions, to guarantee system stability. Paper [92] implements this type of controller in a half-bridge inverter, where the desired output voltage—usually a sinusoidal waveform—is included in the system dynamics as an exogenous input generated by a time-invariant exosystem. From this, a hybrid dynamical system (HDS) with an embedded control law is considered, guaranteeing the existence 1.3 Background on multilevel power converters 57 of a compact attractor where the tracking error—induced by the previous exogenous input—equals zero. Work [93] presents a hybrid controller for NPC converters. In order to perform the stability analysis under balanced grid voltages, the nonlinear time-varying grid voltages in αβ are modelled inside a polytope—using an circumscribed square whose vertices are the peak values—, which is later used along the nonlinear model to derive a polytopic system. With this approach, the time-varying aspect of the grid voltages can be expressed as a linear combination of constant terms, that facilitates the stability analysis in terms of Lyapunov theory. Then, an embedded control law is considered using the HDS theory and the uniform global asymptotic stability is guaranteed by means of analyzing the previous polytopic system. 64 Chapter 2. Contributions to Diode-Clamped Converters Figure 2.4 Example of three possible redundant switching vectors in a five-level DCC. Space vector region of a five-level DCC with the number of redundant switching vectors for each inner hexagon. to-phase voltage is applied when selecting among redundant switching vectors. A work, presented later in this document, will expose this issue and it will propose a modulation approach that does not assume the capacitor voltages to be equal. This concept of redundant switching vectors is also used in plenty of multilevel converter topologies, being one of the most used method to achieve capacitor voltage balancing. In the following sections, the contributions made for three-level DCC and five-level DCC are exhibited along with the used modelling approach. 2.2 Three-level DCC: Neutral-point clamped (NPC) This section is devoted to the grid-connected three-level topology of the DCC, which is also known as neutral-point clamped (NPC) converter. Several contributions for controlling and modulating grid-connected three-level NPC have already been presented that are not the aim of this work [60,63]. The contribution for NPC exhibited in this work is focused on the hybrid modelling [92] of such a converter working as a rectifier in a grid-connected application [93]. This section presents some modifications of this latter work [93] that improves and allows its experimental validation [98]. Firstly, the main results of [93] in terms of modelling and control laws are introduced, then the developed modifications and experimental results are exhibited. 2.2 Three-level DCC: Neutral-point clamped (NPC) 65 Figure 2.5 Scheme of grid-connected three-level NPC Converter. 2.2.1 System description This subsection describes the converter scheme used to derive the modelling and the proposed control algorithm. The grid-connected NPC converter is shown in Fig. 2.5. The system is interfaced with the grid voltages vgi for i=a,b,c by means of an L -filter with same inductance L and parasitic resistance RLS . The phase currents ia,ib and ic are measured as positive when entering the converter—as depicted in Fig. 2.5. The dc-link is composed of two capacitors C1 and C2 with same capacitance C , whose capacitor voltages are vc1 and vc2 respectively, with an equalization resistor Rp attached in parallel to each of them. Lastly, to emulate some active power consumption, a resistive load R is attached to the dc-link side. Dynamic Model The NPC modelling formulated in [93] is derived and exhibited in this section. Considering Fig. 2.5 as reference, the model of the system dynamics can be formulated by applying Kirchhoff laws on the inductor and dc-link capacitors. In order to reflect the capacitor voltage unbalance between vc1and vc2,vdis defined as vd:=vc1−vc2,(2.6) which allows to express each capacitor voltage as a function of the dc-link voltage and vd as follows vc1=vdc 2+vd 2(2.7) vc2=vdc 2−vd 2,(2.8) where vdc =vc1+vc2. The switching functions defined in (2.3) are used to model the possible switching position of each phase. To model this, the output voltage of each phase i ( vi ), measured with respect to the dc-link neutral point o , is expressed according to the switching functions and (2.7)–(2.8) as follows vi=vc1fip −vc2fin , i =a,b,c (2.9) 66 Chapter 2. Contributions to Diode-Clamped Converters vi=vdc 2(fip −fin)+ vd 2(fip +fin), i =a,b,c (2.10) where fij for j=p,o,n is the switching function—this notation for the levels is adopted according to Fig. 2.5 for the NPC converter—, and vdc =vc1+vc2 . Using the inductor voltage drop equation, the model of the NPC phase currents can be stated as follows Ldia dt =vga −RLSia−2 3va+1 3vb+1 3vc(2.11) Ldib dt =vgb −RLSib−2 3vb+1 3va+1 3vc(2.12) Ldic dt =vgc −RLSic−2 3vc+1 3vb+1 3va(2.13) where a balanced grid voltage vga +vgb +vgc = 0 is assumed. Besides, given that the converter is a three-phase three-wire system, the phase currents have to fulfill ia+ib+ic= 0. Replacing (2.10) into (2.11)–(2.13) Ldia dt =vga −RLSia+vdc 6(−2(fap −fan)+(fbp −fbn)+(fcp −fcn)) +vd 6(−2(fap +fan)+(fbp +fbn)+(fcp +fcn)) (2.14) Ldib dt =vgb −RLSib+vdc 6(−2(fbp −fbn)+(fap −fan)+(fcp −fcn)) +vd 6(−2(fbp +fbn)+(fap +fan)+(fcp +fcn)) (2.15) Ldic dt =vgc −RLSic+vdc 6(−2(fcp −fcn)+(fbp −fbn)+(fap −fan)) +vd 6(−2(fcp +fcn)+(fbp +fbn)+(fap +fan)).(2.16) This dynamic model can be translated to the αβ reference frame by applying the Clarke transformation (1.7) , so the phase currents dynamics can be modelled with two equations Ldiα dt =vgα −RLSiα−vdc 2(fαp −fαn)−vd 2(fαp +fαn)(2.17) Ldiβ dt =vgβ −RLSiβ−vdc 2(fβp −fβn)−vd 2(fβp +fβn)(2.18) The dynamic equations of the dc-link voltage and capacitor voltage error can be derived from the capacitor voltage equation Cdvdc dt =Cdvc1 dt +Cdvc2 dt =X i=a,b,c fipii−vdc R−vc1 Rp−X i=a,b,c finii−vdc R−vc2 Rp =X i=a,b,c (fip −fin)ii−vdc 2 R+1 Rp(2.19) 2.2 Three-level DCC: Neutral-point clamped (NPC) 67 Cdvd dt =Cdvc1 dt −Cdvc2 dt =X i=a,b,c (fip +fin)ii−vd Rp ,(2.20) which can also be translated to the αβ reference frame, resulting in Cdvdc dt =X k=α,β (fkp −fkn)ik−vdc 2 R+1 Rp(2.21) Cdvd dt =X k=α,β (fkp +fkn)ik−vd Rp (2.22) Note that phase current and capacitor voltage dynamics (2.21) – (2.22) use the switching function expressed in the αβ reference frame. These variables are just the original switching functions fij for i=a,b,c expressed in the αβ plane using the Clarke transformation. The previous equations can be transformed to obtain the dynamic model in terms of active ( p ) and reactive ( q ) powers. To do so, the instantaneous power theory is used as shown in Eq. (1.22) . Using these expressions in model (2.17) – (2.18) , the state-space model of the system can be obtained using variables p,q,vdc and vdas state variables     ˙p ˙q ˙vdc ˙vd     |{z} ˙x =     −RLS L−2πf −ξ1 2L−ξ3 2L 2πf −RLS L ξ2 2L ξ4 2L ξ1 CV 2 s−ξ2 CV 2 s−(2 RC +1 RpC) 0 ξ3 CV 2 s−ξ4 CV 2 s0−1 RpC      | {z } Au(m)(t)     p q vdc vd     |{z} x +    V2 s L 0 0 0     |{z} B ,(2.23) where x refers to the state vector, Vs=qv2 gα +v2 gβ is the grid voltage amplitude, f= ωg/(2π) is the grid frequency, and ξ1,ξ2,ξ3 and ξ4 are the variables related to the control inputs that are shown below. Note that terms ±2πf appear due to the time derivative of the grid voltages given that a balanced three-phase grid voltage can be expressed as vgα(t) = Vscos(2πft) = dvgβ dt 1 2πf , vgβ(t) = Vssin(2πft) = −dvgα dt 1 2πf , and therefore, the state-space model derived in (2.23) assumes that the grid voltages are balanced. Variables ξ1,ξ2,ξ3 and ξ4 are the input-related terms that depends on the switching vector position enumerated with the index m . In this way, the state matrix Au(m)(t) depends on the switching vector with index m considered. These variables are defined as follows ξ1=u1vgα(t) + u2vgβ(t), ξ2=u1vgβ(t)−u2vgα(t), ξ3=u3vgα(t) + u4vgβ(t), ξ4=u3vgβ(t)−u4vgα(t). 68 Chapter 2. Contributions to Diode-Clamped Converters where u(m)= [u1u2u3u4]T is the switching vector that is defined from the switching functions as u1=fαp −fαn u2=fβp −fβn u3=fαp +fαn u4=fβp +fβn. The previous expression can be rewritten in a matrix form as     ξ1(t) ξ2(t) ξ3(t) ξ4(t)    =Γ(t) 0 0 Γ(t)u(m),Γ(t) = vgα(t)vgβ(t) vgβ(t)−vgα(t)(2.24) Note that the the state matrix Au(m)(t) is time-dependant due to the fact that variables ξ1,ξ2,ξ3 and ξ4 depend on vgα(t) and vgβ(t) . In this regard, let us recall the space vector region where all possible switching states, i.e. the finite number of control actions, are represented, which, for the NPC converter, are equal to 33= 27 positions. Thus, these positions can be numbered as u(m)∈U:={u(1),...,u(27)} according to the corresponding switching functions they represent. However, considering that the three zero switching states—positions [nnn] , [ooo] and [ppp] —have no difference in the dynamics, two of them can be obviated on the set U, which is reformulated as U:={u(1),...,u(25)}. 2.2.2 Modelling of the grid voltages As it was expressed above, the grid voltages are assumed to be balanced and sinusoidal. Thus, they represent a circumference in the αβ plane whose radius is Vs as shown in Fig. 2.6. Taking advantage of this, they can be embedded into a polytope in the following way Ω:= 4 X p=1 νpΩp,for 0≤νp≤1and 4 X p=1 νp(t)=1,(2.25) where Ωp for p= 1,2,3,4 stands for the vertices of the polytope also shown in Fig. 2.6. The formulation of such vertices in the same αβ plane can be given as follows Ω1=Vs Vs,Ω2=−Vs Vs,Ω3=Vs −Vs,Ω4=−Vs −Vs. In this way, the set that represents the grid voltages Φ = {(vgα,vgβ)∈R2, v2 gα + v2 gβ =V2 s}lies inside Ω. Recalling Γ(t) from (2.24) , it can be rewritten as a linear combination of the four vertices that bound Ωas follows Γ(t) = 4 X p=1 µp(t)Γp, 4 X p=1 µp(t)=1 (2.26) 2.2 Three-level DCC: Neutral-point clamped (NPC) 69 Figure 2.6 Grid voltage and polytope representation [93] in the αβ plane. Γ1=VsVs Vs−Vs,Γ2=−VsVs VsVs,Γ3=Vs−Vs −Vs−Vs,Γ4=−Vs−Vs −VsVs, which applied to the ξdefinition in (2.24) results in     ξ1(t) ξ2(t) ξ3(t) ξ4(t)    = 4 X p=1 µp(t)Γp0 0 Γpu(m)(2.27) 2.2.3 Polytopic system fomulation According to (2.27) , the state matrix Au(m)(t) , which depends on the ξp values, can also be written in a similar way Au(m)(t) = 4 X p=1 µp(t)Au(m)(p),(2.28) where, for every instant of t , the time-dependant state matrix is represented as a linear combination of state matrices that are not time-dependant. State matrices Au(m)(p) are the original state matrix but considering the fixed terms Γp in the definition of ξ1,ξ2,ξ3, and ξ4 . Therefore, state matrix Au(m)(p) can be expanded into matrices M1,M2,M3,M4 that multiply ξ1,ξ2,ξ3,and ξ4, respectively, and a common matrix M0. Thus, Au(m)(p) = M1M2M3M4Γp0 0 Γpu(m)⊗I4+M0(2.29) where ⊗stands for the Kronecker product, and M0=     −RLS L2πf 0 0 −2πf −RLS L0 0 0 0 −(2 RC +1 RpC) 0 0 0 0 −1 RpC      70 Chapter 2. Contributions to Diode-Clamped Converters M1=    0 0 −1 2L0 0 0 0 0 1 CV 2 s0 0 0 0 0 0 0    , M2=    0 0 0 0 0 0 1 2L0 0−1 CV 2 s0 0 0 0 0 0     M3=    0 0 0 −1 2L 0 0 0 0 0 0 0 0 1 CV 2 s0 0 0    , M4=    0 0 0 0 0001 2L 0 0 0 0 0−1 CV 2 s0 0    . Consequently, the nonlinear model exposed in (2.23) is expressed as a polytopic system [93] ˙x= 4 X p=1 µpAu(m)(p)x+B(2.30) Γ(t) = 4 X p=1 µp(t)Γp, 4 X p=1 µp(t)=1 2.2.4 Control objectives The main control objective is to make the state variables to converge towards their references, that is, x→x∗ . These references are given externally to this controller and they are defined as [p∗q∗v∗ dc 0] , where the reference for vd is defined as zero to guarantee proper behaviour of the system. Note that, while the state variables are continuous, the control signals, i.e. u(m)∈U , are discrete. Thus, the proposed controller has to select the more appropriate switching action among the available ones in such a way that the previous objective is fulfilled. Another objective is to guarantee that the commutations do not occur at infinity frequency, that is, that a minimum dwell time occurs between consecutive commutations [99]. 2.2.5 Proposed control law For the control formulation, the hybrid dynamical system (HDS) theory is used, as it takes into consideration both the continuous and discrete nature of the system [100]. On the one hand, the continuous evolution (also called flow in HDS theory) comes from the state variable dynamics as it is expressed in the state-space model. On the other hand, the discrete evolution (also called jumps in HDS theory) is given when a change in the control input uhappens. In this way, the proposed control law can be embedded in the HDS formulation in the form H= (C,f,D,G)as H:=        ˙x ˙u=f(x,u),(x,u)∈C, x+ u+∈G(x,u),(x,u)∈D, (2.31a) 2.2 Three-level DCC: Neutral-point clamped (NPC) 71 f(x,u):=Au(t)x+B 0, G(x,u):="x argmin u(m)∈U ˜xTP(Au(m)(t)x+B)#,(2.31b) C:={(x,u) : ˜xTP(Au(t)x+B)≤−η˜xTQ˜x},(2.31c) D:={(x,u) : ˜xTP(Au(t)x+B)>−η˜xTQ˜x},(2.31d) where C,D are the flow and jump sets, η∈(0,1] is a design parameter, and matrices P,Q ∈S4are defined in such a way that they satisfy Au(m)(p)TP+PAu(m)(p)<−2Q , p = 1,2,3,4, u(m)∈U. (2.32) In [93] it is proved that (2.32) can always be achieved by choosing P and Q using energy-like arguments. The idea of (2.31) is based on the existence of a common Lyapunov function V= ˜xTP˜x such that it decreases according to the selected u(m)∈U . If the present control input u(m) gives a large enough decrement in V , then the same control input is kept, i.e. it flows according to set (2.31c) . In the case it is not—set (2.31d) —, the control input is changed to the one that provides the lowest derivative of V as it is shown in G(x,u) inside (2.31b).Note that parameter η∈(0,1] can be tuned to adjust the number of jumps during transient time, i.e. the lower the η , the lower the number of jumps, and thus the lower frequencies the output voltage spectrum has. It is worth mentioning that this controller do not use a modulator given that the switching function generation is implicit, similarly to FCS-MPC. Therefore, the output voltage spectrum would not be centered around a particular switching frequency as that of CBPWM. Summarizing, some features are required to guarantee that the Lyapunov function decreases enough after each jump, and that the hybrid system (2.31) is uniform global asymptotic stable (UGAS): •For each x∈R4, min u(m)∈U ˜xTP(Au(m)(t)x+B)≤−˜xTQ˜x, (2.33) has to be fulfilled. • There exist a linear combination for the state matrix defined in (2.29) for p= 1,2,3,4 and u(m)∈Usuch that 25 X m=1 4 X p=1 λm,peq Au(m)(p)xe+B= 0 (2.34) holds, where λm,peq ∈[0,1] and P25 m=1 P4 p=1 λm,peq = 1. 72 Chapter 2. Contributions to Diode-Clamped Converters •Pand Qare positive definite. Then, there exists an attractor set A:={(x,u) : x=x∗, u ∈U} that is UGAS for the stated hybrid system [93]. The required proof for the above features and the attractor existence are also exhibited in [93]. In spite of the fact that a minimum dwell time is implicitly induced during transient behaviour ( ˜x6= 0 ) by making Q strictly positive, the avoidance of a Zeno behaviour at steady-state is not guaranteed. For this, a modification in the hybrid system is performed that forces the solution to flow for a minimum time T > 0 , which is equivalent to a minimum dwell time both for transient and steady-state conditions [99]. As a result, and similarly to the previous result, a compact set is established that is UGAS for the modified hybrid system AT:= {(x,u,τ) : k˜xk≤X(T),u ∈U,τ ∈[0,2T]},(2.35) where T reflects the dwell time property, and set AT can be arbitrarily close to A as long as Tis small enough. 2.2.6 Experimental verification This section exhibits the main contributions done to this approach, and it is devoted to the experimental validation of the above-mentioned controller. The motivation for the modifications introduced in the control law is to make the controller practically implementable and improve the steady-state performance, Outer control loop Considering the proposed embedded control law, the state variables references are given externally according to the desired equilibrum point ( x∗ ). Theoretically, in steady-state conditions ˙x= 0 , which dictates that the state variable references cannot be set arbitrarily. Indeed, this is obvious from the power flow perspective, where, in steady-state, the input flow of active power (the one given to the system from the grid) must match the output flow (the one absorbed by the load R in the dc side), otherwise the dc-link voltage would change inevitably. Despite the fact that this issue can be taken into account by making ˙x= 0 and defining x∗ accordingly, in a real experiment there are additional losses, which are not considered in the model and that would make p∗ to differ from the actual active power consumption at steady-state. Then, the previous controller cannot reach the steady-state in a real setup due to this mismatch. For this, it is proposed to resort to the standard approach of VSC where an outer controller is used to set the active power reference p∗ [101]. In this regard, a PI controller outputs the value of p∗ from the quadratic error of the dc-link voltage v∗ dc 2−v2 dc as the input. The tuning process of such controller can follow the standard approach exhibited in the introduction chapter, Sect. 1.2.4. The control parameters are denoted as Kpdc and Kidc . In summary, reference p∗ is no longer defined as a fixed value but it is given as the output of the PI controller, and thus it is not a design parameter. 2.2 Three-level DCC: Neutral-point clamped (NPC) 73 Switching state selection According to the proposed control method in [93], when the current switching state u(m) does not decrease the Lyapunov function below a certain value—which is directly proportional to the value of η —, the jump condition (2.31d) is fulfilled and function G(x,u) is applied (2.31b) . However, function G(x,u) dictates that the next control action u(m) has to be searched within set U∈{u(1),u(2),...,u(25)} , taking the one that yield the minimum value of argmin ˜xTP(Au(m)(t)x+B),u(m)∈U . However, this criterium will always select the control input that reduces the state variable error as much as possible, without taking into account the nature of multilevel converter. Large switching vectors—those that are in the outer boundary of the space vector hexagon ( u(m) for m= 20,...,25 )—have a more immediate effect on the state variables—they have larger values in the derivative of the Lyapunov function—, and thus they are more likely to be selected when a jump is given. In the case this phenomenon occurs frequently, the neutral level (point o ) would not be used and the system would not exploit the benefits of multilevel converters. From a practical point of view, it would be more appropriate to apply any switching action that indeed used the neutral level and that achieved a decrement of the Lyapunov function, if such action existed. The interest behind using the neutral point o lies in the phase current ripple, given that the use of the inner level smooths the phase current chattering, and thus the active and reactive power ones. This effect can be noticed in the state-space model (2.23) by realizing that those switching positions that have any fio 6= 0 also have lower values of ξ1,ξ2,ξ3 and ξ4 . Therefore, lower derivatives of the state variables are expected in comparison with other switching positions. In summary, when a jump is given, a mechanism to prioritize the search of the switching action among the ones that use the neutral point o would improve the steady-state behaviour of the system. For this, a modified set U0∈{u(1),...,u(19)} is defined in such a way that it only includes those switching actions with at least one fio 6= 0 . Then, whenever a jump is given, function G(x,u) is modified to search u within U0 first and, in the case it does not decrease the Lyapunov function enough, the whole set U is considered instead. This can be expressed as follows G(x,u) ="x argmin u(m)∈U0 ˜xTP(Au(m)(t)x+B)#if (x+,u+)∈C else G(x,u) ="x argmin u(m)∈U ˜xTP(Au(m)(t)x+B)#. With this proposal, the UGAS property is not spoiled as the whole control input set is still available for the controller, while an improvement in the switching action selection stage is achieved. 80 Chapter 2. Contributions to Diode-Clamped Converters Figure 2.16 Experimental result: External disturbance of 20 V at t= 0.2 s in the vd variable with η= 0.2 . Figure 2.17 Experimental result: External disturbance of 20 V at t= 0.2 s in the vdvariable with η= 1. applied for the polytope, such as an octogon, which could make the stability analysis less conservative and more affordable. 3. Include additional variables in the Lyapunov function or the state-space model in order to improve certain performance indicators, similarly to the model predictive control. 2.3 Five-level DCC The schematic of a grid-connected five-level DCC is shown in Fig. 2.18. As it has been stated in previous sections, the use of five-level DCC is more uncommon compared to that of the NPC. This is due to its increased complexity in control and the increased hardware, which may outweigh the obtained benefits. Namely, the presence of several capacitors in the dc link, which requires additional control objectives to guarantee a proper voltage sharing among them, and the increased number of possible switching positions are what make the control design challenging for this kind of converter. Regarding the capacitor voltage equalization, the literature uses several approaches that can be primarily divided into the following categories [102]: 1. Using redundant switching vectors along with modulation strategies and control schemes or injecting zero-sequence voltages in the modulation signals of carrierbased modulators. 2. Using additional circuitry. 3. Through external converters connected to the dc-link. 2.3 Five-level DCC 81 4. Applying predictive control strategies based on a discrete-time model. 5. Analyzing the capacitor voltage imbalance issue as a problem of regulating the multiple outputs of a nonlinear system subject to exogenous disturbances [103]. Figure 2.18 Scheme of grid-connected five-level DCC. The first category will be explained at the end of this section as it requires a deeper explanation. Some examples of the second approach are presented in [95,104,105]. However, given that they require additional hardware, they increase the converter cost and volume, and they do not guarantee that the control complexity is reduced or even kept the same. Despite these drawbacks, there are some upsides since the balancing task can be left to the external circuitry, and thus the five-level DCC can be exploited without this concern. The third approach is limited to specific applications where the dc-link is attached to a source capable of regulating active power among the different levels, such as back-to-back converters [106] or active/passive front-ends [107]. Therefore, it is of no use when the dc-link is only composed of a passive element that is not connected to any other element. The fourth approach covers predictive controllers, such as the current controller presented in [108], or the well known finite-control-set model-predictive control (FCSMPC) [89]. However, these approaches usually require to compute some predictions for every possible switching action within the switching period, which in the case of 5-level DCC may be unaffordable. That is why great efforts are being devoted to come up with predictive controllers with reduced computational burden [109]. Note also that the control law exhibited in Sect. 2.2.5 for three-level NPC also relies on model-based computations to obtain the best switching action to select. However, in contrast to predictive controllers, it does not compute predictions but derivatives of the Lyapunov function candidate. The last category is extracted from the proposal [103], where an integrated control and modulation is proposed. In summary, this proposal uses the averaged model to derive several control laws that dictates the behaviour of the modulation. This approach establishes the benchmark for several contributions of the present work, and thus it will be explained later in more detail. 82 Chapter 2. Contributions to Diode-Clamped Converters Recalling the first category, it uses the redundant switching vectors or the injection of zero-sequence component [110,111] to achieve balancing. As explained in subsection 2.1.2 for a n-level general case, this solution exploits the degree of freedom associated with the different switching combinations that achieve the same phase-to-phase converter voltage output. That is, making the phase current to circulate through different capacitors to regulate their own voltage without affecting the current performance. Indeed, given the usual αβ transformation, this strategy is equivalent to the injection of zero-sequence component ( γ component), as the redundant vectors appear superposed in the αβ plane [112]. However, it has been stated that using the zero-sequence injection alone (or its equivalent redundant switching vectors in SVM) does not guarantee capacitor voltage balance when higher modulation indexes are given [113]. This is due to the lack of redundant switching vectors in the boundaries of the space vector region. To overcome this, [114] proposed to separate the space vector region into two regions according to the modulation index and a criteria for switching vector selection is provided. Alternatively, [115] uses the previous concept of duty ratios for each level which allows the control to consider all the degrees of freedom the converter has, that is, using several voltage levels within a switching period. The research on this topology carried out by the author of this dissertation has resulted in five contributions, two of them published in field-related journals [116,117], two published in conferences [118,119], and one that is under review the moment this dissertation was being written [120]. 2.3.1 System Description This section uses the same nomenclature than the one used in the previous section, except for the additional switching devices, capacitors and levels. The dc-link is composed of four capacitors C1 , C2 , C3 and C4 with same capacitance C , whose capacitor voltages are vc1 , vc2 , vc3 and vc4 , respectively. For this topology and in contrast to the previous section, the dc-link equalization resistors and the line parasitic resistors are obviated given that the following proposed control schemes do not rely entirely on the circuit model. The five levels of the converter are numerated in ascending order according to its voltage level, i.e. from bottom to top, as oj for j= 1,...,5 . Similarly to the NPC, the switching signals are numerated for each phase in descending order as Si p , and their counterpart as Si p for i=a,b,c and p= 1,...,4 . Again, a resistive load R is attached to the dc-link side to emulate active power consumption. 2.3.2 Dynamic model Considering the generic model of switching functions and duty ratios given in (2.1.1) , the output voltage of the converter can be formulated in an averaged model ([97]) as vi=−(vc3+vc4)di1−vc3di2+vc2di4+(vc2+vc1)di5, i =a,b,c. (2.38) 2.3 Five-level DCC 83 Assuming that the capacitor voltage balance task is achieved in steady-state conditions, (2.38) can be further simplified by making vc1=vc2=vc3=vc4=vdc/4, resulting in vi=vdc 4(−2di1−di2+di4+2di5), i =a,b,c , (2.39) or equivalently in the αβ reference frame vk=vdc 4(−2dk1−dk2+dk4+2dk5), k =α,β , (2.40) where the capacitor voltage unbalance has no effect given the previous assumption. From Fig. 2.18, the following model can be derived from the Kirchhoff laws and the inductor voltage drop Ldia dt =vga −2 3va+1 3vb+1 3vc(2.41) Ldib dt =vgb −2 3vb+1 3va+1 3vc(2.42) Ldic dt =vgc −2 3vc+1 3vb+1 3va,(2.43) which can be translated to the αβ reference frame resulting in Ldiα dt =vgα −vα=vgα −vdc 4(−2dα1−dα2+dα4+2dα5)(2.44) Ldiβ dt =vgβ −vβ=vgβ −vdc 4(−2dβ1−dβ2+dβ4+2dβ5).(2.45) Following the same procedure and taking into account the DCC capacitor balancing generic formulation given in Sect. 2.1.2, the following averaged model for the capacitor voltages can be derived in αβ reference frame Cdvc1 dt =dα5iα+dβ5iβ−vdc R(2.46) Cdvc2 dt = (dα5+dα4)iα+(dβ5+dβ4)iβ−vdc R(2.47) Cdvc3 dt =−(dα1+dα2)iα−(dβ1+dβ2)iβ−vdc R(2.48) Cdvc4 dt =−dα1iα−dβ1iβ−vdc R.(2.49) It is worth mentioning that: • The power invariant version of the Clarke transformation is the one being used to transform from abc to αβ • The Clarke transformation includes the variables in the γ component. However, given that the system is a three-wire converter, the dynamics on this component can be neglected. Thank to this, there is an inherent degree of freedom in the reverse 84 Chapter 2. Contributions to Diode-Clamped Converters transformation αβ →abc as the γ component can be selected arbitrarily. This feature is indeed related to the concept of using redundant switching vectors as it was mentioned before. Similarly, the obtention of the duty ratios in abc from those defined in αβ can include such degree of freedom to address additional control objectives. The capacitor voltage unbalance are represented through three variables vd1,vd2,vd3 defined as follows vd1=vc4−vc1(2.50) vd2=vc3−vc2(2.51) vd3=vc2−vc1.(2.52) By using (2.46)–(2.49), the dynamics of these variables can be obtained Cdvd1 dt =−(dα5+dα1)iα−(dβ5+dβ1)iβ(2.53) Cdvd2 dt =−(dα5+dα4+dα2+dα1)iα−(dβ5+dβ4+dβ2+dβ1)iβ(2.54) Cdvd3 dt =dα4iα+dβ4iβ.(2.55) The dc-link voltage vdc =P4 p=1 vcp dynamic is expressed from the addition of (2.46) – (2.49), resulting in Cdvdc dt =4 vdc (vαiα+vβiβ)−4idc Ceqvdc dvdc dt =p−vdcidc ,(2.56) where Ceq =C/4 is the equivalent capacitance of the dc-link considering the four capacitors in series. As it can be seen, (2.56) represents the active power flow among the one obtained from the grid ( p ), the one used to increase the dc-link voltage ( Ceqvdc dvdc dt ), and the one absorbed by the dc-link load (vdcidc). 2.3.3 Integrated control and modulation of five-level DCC This section exhibits the controller design presented in [97] and its further improvement and experimental validation [116], which are the contributions of this work. This controller reformulates the control inputs exhibited in (2.44) – (2.45) and (2.53) – (2.55) in such a way that the system control objectives are uncoupled and they can be targeted individually. Afterwards, the degrees of freedom related to the γ component are considered to further improve the system performance. In the following, the controller design, simulation results and experimental validation are exposed. 2.3 Five-level DCC 85 Controller design Inspired from the current dynamic equations (2.44) – (2.45) and from the error signal dynamic equations (2.53)–(2.55), the following change of variables is carried out [97] u1=−2dα1−dα2+dα4+2dα5(2.57) u2=−2dβ1−dβ2+dβ4+2dβ5(2.58) u3=dα5+dα1(2.59) u4=dβ5+dβ1(2.60) u5=dα5+dα4+dα2+dα1(2.61) u6=dβ5+dβ4+dβ2+dβ1(2.62) u7=−dα4(2.63) u8=−dβ4,(2.64) which can be synthesized in matrix form as follows Tk→i=    2 1 −1−2 1 0 0 1 1 1 1 1 0−1 0 0         u1 u3 u5 u7    =Tk→i    dα5 dα4 dα2 dα1    ;    u2 u4 u6 u8    =Tk→i    dβ5 dβ4 dβ2 dβ1    .(2.65) Therefore, the system dynamics result in the following equations Ldiα dt =vgα −vdc 4u1(2.66) Ldiβ dt =vgβ −vdc 4u2(2.67) Cdvd1 dt =−u3iα−u4iβ(2.68) Cdvd2 dt =−u5iα−u6iβ(2.69) Cdvd3 dt =−u7iα−u8iβ(2.70) Therefore, u1 and u2 are the control inputs for the current controller for iα and iβ , respectively, whereas um for m= 3,...,8 can be used to formulate a capacitor voltage balancing controller that is independent from the current controller. Note, however, that it has been assumed equal capacitor voltage in the modelling stage, and thus, during transient periods where an unbalance is present, some distortions may appear in the current control loop. 86 Chapter 2. Contributions to Diode-Clamped Converters Inner controller Recalling the αβ model in the stationary reference frame defined in Eq. (1.29) and comparing them with (2.66) – (2.67) , it is straightforward that the control variables u1 and u2 can take the role of 4v∗ α/vdc and 4v∗ β/vdc , respectively, so any of the control strategies presented in the introduction can be used. In the remaining of this section, the modelbased direct power controller presented in Sect. 1.2.4 is used (1.37) – (1.38) , but with slight modifications in the formulation as follows u1=ueq 1+Kpvgα(p−p∗) + Kivgα Zt o (p−p∗)dτ −Kpvgβ(q−q∗)−Kivgβ Zt o (q−q∗)dτ (2.71) u2=ueq 2+Kpvgβ(p−p∗)+Kivgβ Zt o (p−p∗)dτ +Kpvgα(q−q∗) + Kivgα Zt o (q−q∗)dτ , (2.72) where a PI controller is used instead of a proportional one, so the integral gain compensates for model uncertainties. Consequently, the adaptation gain in (1.37) – (1.38) is no longer necessary—note that the adaptation gain was initially used to estimate the model uncertainties according to the actual measurements. In this way, the equilibrium point (1.38) is redefined ueq 1=4 vdc 1+ ωgLq v2 gα +v2 gβ !vgα +ωgLp v2 gα +v2 gβ vgβ!(2.73) ueq 2=4 vdc 1+ ωgLq v2 gα +v2 gβ !vgβ −ωgLp v2 gα +v2 gβ vgα!.(2.74) Outer controller Considering that a model-based direct power control is used for the IC, the OC should provide the power references p∗ and q∗ for it. In this work, considering the rectifier application of the converter (Fig. 2.18), a PI controller to regulate vdc towards v∗ dc that provides the value of p∗ is used, at the same time that q∗ and v∗ dc are given externally by the user. The control parameters of this PI controller are named as Kdc p for the proportional gain and Kdc ifor the integral gain. Capacitor voltage controller Lastly, the capacitor voltage balance controller, whose aim is to make the error signals vd1, vd2, vd3to go to zero, can be derived from (2.68)–(2.70) as u3=iαk1vd1, u4=iβk1vd1(2.75) u5=iαk2vd2, u6=iβk2vd2(2.76) u7=iαk3vd3, u8=iβk3vd3,(2.77) 2.3 Five-level DCC 87 where k1>0 , k2>0 and k3>0 are the control parameters. With this formulation, (2.68)–(2.70) are transformed to Cdvd1 dt =−k1(i2 α+i2 β)vd1=−k1I2vd1(2.78) Cdvd2 dt =−k2(i2 α+i2 β)vd2=−k2I2vd2(2.79) Cdvd3 dt =−k3(i2 α+i2 β)vd3=−k3I2vd3,(2.80) where I=qi2 α+i2 β≥0 is the instantaneous amplitude of the currents when they are balanced. Nevertheless, given that k1,k2,k3>0 and I > 0 , it is straightforward that variables vd1,vd2,vd3tend to zero. Implementation From the previous sections, the control inputs u1,...,u8 are determined every switching period according to the implemented controller. Then, in order to feed the modulation stage, the duty ratios in abc are required. For this, firstly, the transformation shown in (2.65) is reversed to obtain the αβ values of the duty ratios, then the four degrees of freedom dγ1,dγ2,dγ4,dγ5 are defined, and, lastly, the reverse Clarke transformation is carried out. Accordingly, the reverse of (2.65) is applied T−1 k→i=Ti→k=    1 41 41 42 4 0 0 0 −1 0−1 1 1 −1 43 4−1 4−2 4         dα5 dα4 dα2 dα1    =Ti→k    u1 u3 u5 u7    (2.81)     dβ5 dβ4 dβ2 dβ1    =Ti→k    u2 u4 u6 u8    .(2.82) Afterwards, the values of dγj for j= 1,2,4,5 can be determined aiming at additional control objectives. However, these values should not be selected arbitrarily as there exist several restrictions for the duty ratios in abc that may act as an upper and lower boundary for the value of dγj , that is, P5 j=1 dij = 1 and dij ≥0 for i=a,b,c should be fulfilled at all times. The original proposal [97] carried out some analysis based on the expected steady-state performance and proposed fixed values for these variables in such a way that duty ratio saturation is avoided. Consequently, dγj =kγj for j= 1,2,4,5 . As an alternative, variable dγj values are considered in order to achieve an steady-state improvement which will be explained in the following subsection. 88 Chapter 2. Contributions to Diode-Clamped Converters Once the previous steps have been carried out, the duty ratios can be obtained   daj dbj dcj  =Tαβγ→abc   dαj dβj dγj  for j= 1,2,4,5,(2.83) and the duty ratio of the remaining level is derived from the duty ratio restriction di3= 1−X j=1,2,4,5 dij for i=a,b,c . (2.84) With this, the duty ratios in abc are fully determined and the modulation stage can implement them along a switching period. Algorithm Improvement The four degrees of freedom, which correspond to dγj for j= 1,2,4,5 , are the homopolar component of each level for the three-phase set. They act as a bias for the four duty ratios simultaneously. Consequently, these values have three upper boundaries caused by the corresponding di3 to reach zero—larger values of dγj would make either P5 j=1 dij >1 or di3<0 , which are both infeasible—, and one lower boundary for each level j= 1,2,4,5 that is reached whenever dij = 0 for any phase i —lower values of the corresponding dγj would make, at least, one dij <0. To take this into account, two solutions are proposed: • Using fixed values kγj for j= 1,2,4,5 . This is the solution stated in the control proposal [97] and these values are derived from the expected steady-state behaviour in such a way that the maximum possible range of operation is allowed for the duty ratios. Note that, fixing dγj would translate the upper and lower boundaries to the dαβj , which can be expressed as a delimited range for the control inputs u1,...,u8 . • Using time-variant values in order to fully exploit the range of operation of the duty ratios, while some additional benefits are obtained. This is the case when the dγj values are selected according to their lowest boundary, that is, when one dij = 0 . Not only this keeps the remaining duty ratios the furthest possible from the upper bound, but also it avoids one level to appear in the output voltage, that is, at least one commutation is avoided. This is highlighted as a contribution of this work, and its benefits will be discussed and exhibited in the simulation and experimental section. The second solution offers more benefits due to its flexibility, and thus it will be analyzed in the following. The lower boundary for each dγj comes from the reverse Clarke transformation (2.83) , which results in three possible values, da γj =−Tαβ→adαj dβj =−√2dαj (2.85) db γj =−Tαβ→bdαj dβj =dαj √2−dβjr3 2(2.86) 2.3 Five-level DCC 89 Figure 2.19 The planes represented by eqs. (2.85)–(2.87) in the αβγ region. dc γj =−Tαβ→cdαj dβj =dαj √2+dβjr3 2,(2.87) where di γj stands for the value of dγj that makes the corresponding duty ratio dij of phase i equal to zero. Considering this, and the constraint of dij ≥0 , the lowest boundary of dγj is dγj =maxda γj ,db γj ,dc γj ,(2.88) where max stands for the maximum function. Note that, using (2.88) and given that it is the lowest boundary, if some dij results to be greater than 1, it would mean that duty ratio saturation was unavoidable—some dij is either lower than zero or larger than 1—, i.e. some control signal is out of boundaries. In these cases, it is recommended to prioritize the fulfillment of the inner controller—the power control carried out by defining u1 and u2 —over the capacitor voltage balancing—carried out by u3,...,u8 —, given the slower dynamic of the capacitor voltages, and that the power control fulfillment is a more critical target. The easiest way to achieve this is by making all balancing control variables u3,...,u8 equal to zero such that no effect on the capacitor voltage balancing is expected. Nevertheless, as it will be shown later in simulation and experiments, these cases are rare, and in the worst scenario, they would take place during some particular transient conditions. At this point of the duty ratio obtention, the values dαj and dβj for j= 1,2,4,5 are already defined, and thus applying (2.85) – (2.88) results in the values of dγj . To depict this, equations (2.85) – (2.87) are represented as planes in the αβγ space in Fig. 2.19. For any pair of dαj and dβj values, there always exists one maximum value which dictates the selected value of dγj. As a result of using this tuning algorithm, for levels j= 1,2,4,5 , there would be one phase i whose dij = 0 . However, levels j= 2,4 deserves special attention. This proposal, 96 Chapter 2. Contributions to Diode-Clamped Converters Figure 2.28 Proposed approach that interfaces four solar arrays with the grid with no need of dc-dc stage. The proposed solution is shown in Fig. 2.28 that covers the first two stated objectives. The third and fourth objectives are covered when using the integrated control exhibited in the previous section, however some modifications have to be considered that will be exposed in the following sections. Solar arrays For this approach, the solar arrays are attached individually to each dc-link capacitor with no inclusion of DC-DC stage. An external MPPT (not exhibited in the current work) provides the capacitor voltage controller with the capacitor voltage reference as v∗ c1,v∗ c2,v∗ c3,v∗ c4 . This work do not develop the MPPT implementation but assumes that the reference voltages are given externally and that they do not change abruptly (much slower dynamic than the outer loop controller). Given that the four solar arrays can output different values of active power, the current that goes through them can also be different. For this, following the same notation than (2.50) – (2.52) , the following current differences are defined h1=is4−is1(2.89) h2=is3−is2(2.90) h3=is2−is1,(2.91) which will be used later for the updated modelling of the capacitor voltage dynamic. Corrected model in αβ coordinates The averaged model that uses (2.38) is still considered for this approach, although the equal capacitor voltage balance assumption can not be longer accepted given the nature of the application. For this, (2.44) – (2.45) are modified considering the definition of the error signals vd1,vd2,vd3(2.50)–(2.52) resulting in Ldiα dt =vgα −vdc 4u1+vd1 vdc hd1α+vd2 vdc hd2α+vd3 vdc hd3α(2.92) 2.3 Five-level DCC 97 Ldiβ dt =vgβ −vdc 4u2+vd1 vdc hd1β+vd2 vdc hd2β+vd3 vdc hd3β,(2.93) where u1,u2are the control signals defined in (2.57) and (2.58), and hd1k=−2dk1+dk2−dk4−2dk5(2.94) hd2k=−2dk1−3dk2−dk4−2dk5(2.95) hd3k=−2dk2+2dk4(2.96) for k=α,β . Note that terms hd1k,hd2k,hd3k are included to correct the effect that the error signals will have on the current dynamics. Taking into account this formulation, the fourth objective is considered. It is worth mentioning that the inclusion of these terms that depend on several duty ratios will change the duty ratio obtainment shown in (2.81) – (2.82) as it will be exhibited later. Similarly, the dynamic of the error signals vd1,vd2 and vd3 is modified to include h1 , h2and h3as follows Cdvd1 dt =X k=α,β −(dk5+dk1)ik+h1(2.97) Cdvd2 dt =X k=α,β −(dk5+dk4+dk2+dk1)ik+h2(2.98) Cdvd3 dt =X k=α,β dk4ik+h3(2.99) Adapted controller design In this case, the control signals u3,...,u8 follow the definition given in (2.59) – (2.64) , but u1 and u2 have to take into account the new formulation given in (2.92) and (2.93) . For this, u1and u2are reformulated as u0 1and u0 2as follows u0 1=u1+1 vdc (vd1hd1α+vd2hd2α+vd3hd3α)(2.100) u0 2=u2+1 vdc (vd1hd1β+vd2hd2β+vd3hd3β).(2.101) With this formulation, the αβ current dynamic model results in Ldiα dt =vgα −vdc 4u1 Ldiβ dt =vgβ −vdc 4u2. Consequently, any well-known current controller can be implemented to define the value of u1 and u2 [25]. In the following, a PI current controller in rotating synchronous 98 Chapter 2. Contributions to Diode-Clamped Converters reference frame dq , which has been already explained in the introduction section, is considered here as follows ud=4 vdc kp(i∗ d−id)−iqωgL+kiZt 0 (i∗ d−id)dτ(2.102) uq=4 vdc kp(i∗ q−iq)+idωgL+kiZt 0 (i∗ q−iq)dτ,(2.103) where id , iq are the measured phase currents in dq , i∗ d , i∗ q are their respective references, and ud , uq are the current control signals in dq reference frame that have to be translated to αβ u1=udcos(ωgt)−uqsin(ωgt) u2=udsin(ωgt)+uqcos(ωgt). The outer loop control is kept the same than in the previous approach, and the current references are obtained through the instantaneous power theory as exhibited in the introduction section. Lastly, the capacitor voltage controllers presented in (2.75) – (2.77) have to be modified taking into account the presence of h1,h2and h3, and that the controller no longer aims to regulate the error signal towards zero, i.e. equal capacitor voltages, but to a particular value defined by the capacitor voltage references. In this regard, variables v∗ d1 , v∗ d2 and v∗ d3are defined as references for the error signals v∗ d1=v∗ c4−v∗ c1, v∗ d2=v∗ c3−v∗ c2, v∗ d3=v∗ c2−v∗ c1, v∗ dc =v∗ c1+v∗ c2+v∗ c3+v∗ c4, where v∗ dc is no longer defined by the user, but it is the result of applying the desired capacitor voltage defined by the MPPT algorithms. Consequently, the outer loop regulates vdc towards v∗ dc, whereas the error signal controllers are formulated as follows u3=iαPI(v∗ d1−vd1)(2.104) u4=iβPI(v∗ d1−vd1)(2.105) u5=iαPI(v∗ d2−vd2)(2.106) u6=iβPI(v∗ d2−vd2)(2.107) u7=iαPI(v∗ d3−vd3)(2.108) u8=iβPI(v∗ d3−vd3),(2.109) where PI(x) = kbal px+kbal iRt 0xdτ . The closed-loop dynamics of the error signals result in the following equations dvd1 dt =I2PI(v∗ d1−vd1)+h1 dvd2 dt =I2PI(v∗ d2−vd2)+h2 2.3 Five-level DCC 99 dvd3 dt =I2PI(v∗ d3−vd3)+h3, where each integral term compensates for the corresponding current unbalance h1 , h2 or h3, whereas the proportional terms ensure the capacitor voltage signal error tracking. Modulation stage Similarly to the previous approach, once u1,...,u8 are determined applying the corresponding controller, the duty values dαj and dβj for j= 1,2,4,5 can be obtained by reversing the control variable definitions     dα1 dα2 dα4 dα5    =    −1 4du3 α1du5 α1du7 α1 0−1 1 1 0 0 0 −1 1 4du3 α5du5 α5du7 α5        u1 u3 u5 u7    (2.110)     dβ1 dβ2 dβ4 dβ5    =    −1 4du4 β1du6 β1du8 β1 0−1 1 1 0 0 0 −1 1 4du4 β5du6 β5du8 β5        u2 u4 u6 u8    (2.111)           du3 α1 du5 α1 du7 α1 du3 α5 du5 α5 du7 α5           =1 4vdc Tvd     vd1 vd2 vd3 vdc     ,           du3 β1 du5 β1 du7 β1 du3 β5 du5 β5 du7 β5           =1 4vdc Tvd     vd1 vd2 vd3 vdc     , Tvd=           −3 1 2 3 1−3−2−1 2−2−4−2 3−1−2 1 −1 3 2 1 −2 2 4 2           . From (2.110) – (2.111) , the αβ duty ratios are obtained for levels 1,2,4 and 5. It is worth recalling from the integrated control approach that the duty ratios of level three are later determined from the duty ratio restriction P5 j=1 dij = 1 for each phase i=a,b,c . However, as stated in the integrated control approach, there are still four degree of freedoms associated to the values of dγ1,dγ2,dγ4 and dγ5 . In the previous section, it was assumed that the error signals at steady-state are close to zero, and thus the control variables u3,...,u8 are also close to zero, which means that duty ratios of levels 2 and 4 are almost not used. In this case, this is not longer valid as the control scheme implements a PI controller whose integral term may result in a bias value in steady state. Due to this, the γ duty ratio determination deserves special attention as the dij are more likely to saturate. The algorithm improvement is initially considered but with the aim of avoiding dij saturation. In the following, a guideline to derive the values of dγj for j= 1,2,4,5 is given. The boundaries of dij for each phase iare X j=1,2,4,5 dij ≤1(2.112) 100 Chapter 2. Contributions to Diode-Clamped Converters dij ≥0for j= 1,2,4,5.(2.113) On the one hand, from (2.112) one upper bound for the four levels can be formulated from each phase boundary. Defining, dS γ=Pj=1,2,4,5dγj and considering the reverse Clarke transformation, three limits are given phase a: dS γ≤√3−X j=1,2,4,5 √2dαj (2.114) phase b: dS γ≤√3+ X j=1,2,4,5 dαj √2−r3 2dβj!(2.115) phase c: dS γ≤√3−X j=1,2,4,5 dαj √2+r3 2dβj!.(2.116) On the other hand, from (2.113) one lower bound for each level jcan be derived from the three phase boundaries. phase a: dγj ≥−√2dαj (2.117) phase b: dγj ≥dαj √2−r3 2dβj (2.118) phase c: dγj ≥dαj √2+r3 2dβj.(2.119) Notice that both boundaries are reflected as a set of three equations, but only the most restrictive one would apply. The solution adopted in this work goes through selecting the minimum values of dγ1 and dγ5 that fulfill (2.113) , and then dividing among the three remaining levels j= 2,3,4 the spare value of dS γ until the upper bound is reached (2.112) . The first selection pursues to reduce the commutations similarly to the previously presented algorithm improvement. The second choice is made in order to assure that levels 2,3 and 4 always appear in the output waveform, and thus avoiding large jumps, such as di26= 0,di3= 0,di46= 0 . With this approach, saturation is pushed to the limit, and in the case some dij saturates, that would mean that either saturation was unavoidable for the given conditions or large jumps were necessary to be included. For the sake of simplicity, in the following simulations, those cases would simply be trimmed to [0,1]. In summary, the values of dγj are determined in five steps 1. The most restrictive values of (2.112) and (2.113) are determined. For this, the minimum value of (2.114) – (2.116) is considered and referred as dS γm , while the maximum boundaries given by (2.117) – (2.119) for each level j are considered and referred as dγjm. 2. Levels 1 and 5 are directly assigned considering the maximum boundary: dγ1=dγ1m , dγ5=dγ5m . This is the same procedure than the improved algorithm considered in the previous approach and guarantee that, at least, two commutations are avoided. 2.3 Five-level DCC 101 3. The spare value of dS γm —referred as dγrem —is determined considering the minimum value of dγ2and dγ4from (2.117)–(2.119). That is, dS γrem =dS γm−dγ1−dγ5−dγ2m−dγ4m. 4. Then, dS γrem is divided equally among the three remaining levels (2,3,4) and added to the minimum value in order to make sure that the duty ratios of levels 2,3,4 are not zero: dγ2=dS γrem /3+dγ2mdγ4=dS γrem /3+dγ4m 5. It is checked whether the previous operation was feasible, i.e. dS γrem ≥0 . If so, no change is performed; else, some restriction is violated and the corresponding duty ratio would saturate. In order to reduce this saturation impact as much as possible, it is proposed to make duty ratio of level 3 equal to zero, that is, making dS γrem = 0 in the previous equations and recalculating the values of dγ2and dγ3. To depict an example of this distribution, Fig. 2.29 shows a generic diagram where the cases of no saturation (dS γrem ≥0) and saturation (dS γrem <0) are depicted. Figure 2.29 Sample of dγj distribution for a case where no duty ratio saturation will be produced and for a case where some duty ratios will saturate. At this point, the dγj values for j= 1,2,4,5 are determined and the reverse Clarke transformation can be performed to obtain the equivalent duty ratios in abc . Lastly, the duty ratio constraint for each phase i , P5 j=1 dij = 1 , is considered to obtain di3 . Note that, given to the previous step 4 and when no saturation takes place, it is guaranteed that Pj=1,2,4,5dij <1, and therefore the duty ratio of level 3 will not be zero. Simulation Results This section is devoted to present the simulation results when applying the previous algorithm to the system described in the previous section. The system and control parameters are depicted in Table 2.4. For the solar arrays, variables vMPCp for p= 1,2,3,4 —the 102 Chapter 2. Contributions to Diode-Clamped Converters Table 2.4 5L-DCC system and controller parameters. Parameter Value (Units) Inductor, L2(mH) dc-link Capacitors, C3.3(mF) Grid voltage 220√3(V) Grid frequency, f50 (Hz) Reactive power reference, q∗0 (kVA) Prop. dc-link PI controller, Kdc p0.05 Int. dc-link PI controller, Kdc i1 Prop. current controller, Kp15 Int. current controller, Ki25 Prop. cap. bal. controller, Kbal p0.001 Int. cap. bal. controller, Kbal i0.005 Table 2.5 Values of vMPCp and pmax Cp . Cap. Volt. Power C1260 V 5 kW C2210 V 4 kW C3180 V 3.6 kW C4250 V 4.7 kW Figure 2.30 Three-phase currents in steady-state. capacitor voltages at which the output power is maximized—are given along with the corresponding maximum power achievable pmax Cp in Table 2.5. The solar power curves (Curve p−V ) are emulated for each solar array p as a second-order polynomial equation with a maximum at ( vMPCp ,pmax Cp ) and different bias in order to simulate different behaviors. To evaluate the evolution of the current proposal, the simulations start with v∗ cp = 200 V for p= 1,2,3,4 and, from t= 0.7 and on, these values are updated progressively until they reach vMPCp simultaneously at t= 1. The three-phase currents at steady-state are shown in Fig. 2.30 where the zoomed area depicts the current when the system has reached steady state with its maximum power production. Besides, it can be seen that the current amplitude change along the simulation according to the obtained power. It is worth mentioning that there is a current sag at t= 0.7 s due to power required to increase the capacitor voltages. In this regard, it can be seen how the proposed converter starts increasing the delivered power once the capacitor voltage references have been reached at t= 1 s. The output power of each solar array and the capacitor voltage evolution are shown in Fig. 2.31 and Fig. 2.32, respectively. As expected, the capacitor voltage balance controller is able to track the references while the obtained output power is maximized. Considerably 2.3 Five-level DCC 103 large differences in the capacitor voltage at steady-state conditions are tested, which proves the feasibility of the current proposal to track different capacitor voltages. Besides, note from Fig. 2.27 that the variation of vMPCp for different irradiances is far less noticeable than the change considered in this test, which proves the conservative of these simulations. Lastly, in order to prove the effectiveness of the corrected model and consequent modifications in the duty ratios obtainment, Fig. 2.33 is plotted. Thanks to the corrected model, the capacitor voltage unbalance at steady-state has no effect on the current distortion. Indeed, the THD value is reduced, as shown in Fig. 2.33 (top), due to the increment in the amplitude of the fundamental component, as the output power is increased without generating further distortion. With regard to the output waveform, Fig. 2.33 (bottom) depicts the phase a switching state at steady-state conditions, where it can be seen that during one third of the grid period the five levels are used, whereas no large jumps are produced thanks to the proposed dγdistribution. Conclusions and future lines of research This section exhibits a potential application of the developed integrated control to interface several solar arrays with the grid using only a five-level DCC. With this and considering that no dc-dc stages are required, a potential reduction in size and improved efficiency can be achieved. It is also shown that the maximum power point tracking capability is possible to achieve by providing this algorithm with the references for the capacitor voltage values. The potential lines of research includes the extension of this approach to different topologies and number of levels, the analytical study of the duty ratio saturation and how the dγ distribution affect them, experimental verification, and the effect the ground coupling or current leakage of solar arrays may have on the performance of this approach, among others. Additionally, the inclusion of high-efficient isolating DC-DC stages could be also considered. With this, the solar arrays can be interfaced with the dc-link capacitors in such a way that, combined with the voltage regulation capabilities of this approach, the application offers a wide flexibility in the voltage range of the operating point. Figure 2.31 Evolution of the power extracted from each solar array (pCp =vcpisp) in kW. Figure 2.32 Evolution of the capacitor voltages (solid) and their references (dashed) in V. 104 Chapter 2. Contributions to Diode-Clamped Converters Figure 2.33 THD value of the three-phase currents during the test considered (in % of current amplitude) (top); and switching state of phase a (Output waveform) and its averaged value (bottom). 2.3.5 Thermal analysis of the integrated modulation and control approach. Comparison with the improved algorithm This section presents a contribution of this work that focuses on analyzing the effect the integrated control and modulation approach presented in Sect. 2.3.3 has on the conductive losses [119]. Besides, the algorithm improvement, also presented in Sect. 2.3.3, is included in the analysis and used for comparison. With this, some conclusions are drawn on which approach is more feasible to increase the life expectancy of the switching devices. The switching losses are not included in this analysis due to its dependence with the operating conditions, as it is explained later. Thermal management Device temperature concern is leading a new concept of power converter design known as thermal management [122]. This is due to the undesired effects that high temperature or temperature changes may have on power device reliability and durability. Consequently, temperature is a key point that has to be taken into account in order to extend the expectancy of power device lifetime [123]. The current going through each power device creates a power flow that yields cyclic heating and cooling intervals. Considering the different thermal expansions coefficients of the components inside the power device, these intervals create mechanical stress that are translated to aging and, consequently, reduced lifetime expectancy [124]. Therefore, it is critical to reduce its magnitude in order to reduce long-term expenses [125]. In this sense, active thermal control (ATC) is a technique that takes into account these effects and modifies the overall performance in such a way that the amplitude of these cycles or the averaged temperature level are decreased. 2.3 Five-level DCC 105 In the case of multilevel power converters, this is of special importance as, depending on the topology, some semiconductors might be closed longer than others which entails more conduction losses and therefore bigger thermal aging effects. As a consequence, these devices are more likely to reach its lifetime end than the others, increasing the cost of maintenance. As a result, several studies have been carried out to consider the thermal management into the control of multilevel converters [126–128]. The approach presented in Sect. 2.3.3 uses all levels within a switching period, whereas its improvement can skip some of them. Using several levels could yield higher switching losses than other known approaches for multilevel converters, although it could make the dissipated power to be more equally distributed among the semiconductors, reducing the thermal cycles and aging. The switching losses highly depend on the switching frequency, the point of operation and how the levels are sequenced in the output within a switching period. However, in multilevel converters, as the device blocking voltage is reduced by the introduction of several levels, their magnitude for every device is considerably reduced in comparison with two level topologies that hold the same dc-link voltage. Nevertheless, a tradeoff comparison dependant on the operating point has to be made to determine which is the most suitable approach. Because of this, the switching losses have not been considered in this analysis as it would not yield any straight conclusion. Moreover, using a turn-off snubber circuit translates part of the power dissipation due to switching to the external circuit, and thus it reduces the heating caused by the switching of the device. This section exhibits the two proposed approaches and compares them in terms of thermal effects. Conduction losses The considered modulation approaches will yield different losses profiles as the conducting time and turning-on/off cycles of the power devices differ depending on the levels used. The higher the duty ratio, the higher the conducting time of the power devices. Therefore, the analysis will focus on a generic phase i and the conduction losses of the four upper semiconductors {Si 1,Si 2,Si 3,Si 4} considering that the lower ones will have a symmetrical behaviour. Also, no dead time is considered as it can be emulated as an extension of the duty ratios [129]. It is also worth to mention that the current will not always go through the switching device but through the anti-parallel diode sometimes—whenever the phase current ii>0 — which would change the losses profile. However, considering the periodical behaviour of the phase current and that this section aims for a comparative analysis, only the losses generated in the switching devices are considered, i.e. only when ii≤0 . In this way, a variable called switching device usage Si n ucan be defined as follows 112 Chapter 2. Contributions to Diode-Clamped Converters Optimization problem formulation The optimization formulation is developed for the modulation stage, which is in charge of commanding the switching devices in such a way that the current/power controller output is properly carried out in the system. For this, the formulation is based on the averaged model of the system that uses the duty ratio dij concept, which has been presented in Sect. 2.1.1. Due to the nature of multilevel converters, the capacitor voltage balancing issue has to be addressed as well. Then, the optimization considers as constrains the fulfillment of the desired output voltage (controller output) and the capacitor voltage balance, while the output of such formulation are the duty ratios of every phase i and level j . The optimality is sought in reducing the number of commutations as much as possible, in order to reduce the switching losses, at the same time that some undesired solutions are weighted to be avoided as far as possible. In the following, the optimization problem that has to be solved every sampling time is formulated along with its inputs, contraints and outputs. Constraints Considering that the formulation uses the duty ratios concept, the constraints are the following ones •The sum of the duty cycles for each phase has to be one (equality constraints) 5 X j=1 dij = 1; i=a,b,c. (2.129) • The outputs of the power controller ( u1=uα,u2=uβ ) transformed to abc (referred as ηa,ηb,ηc) have to be attained (equality constraints). Accordingly,   ηa ηb ηc =Tαβ→abc uα uβ(2.130)   ua ub uc =  ηa ηb ηc +x= −2da1−da2+da4+2da5 −2db1−db2+db4+2db5 −2dc1−dc2+dc4+2dc5 (2.131) where x is the degree of freedom that results from the homopolar components, i.e. the dγj values in the integrated control and modulation approach. For the current approach, the dγj values are no longer considered, and variable x is used instead, which will be considered in the optimization formulation. Note that with this formulation, the homopolar component is no longer separated into four variables as it was the case of the integrated control and modulation approach, but represented with only one variable, that is x . In this way, the non-zero duty ratio values that input the modulator can be managed more easily. • The balancing error signals vd1,vd2,vd3 are imposed to go to zero monotonically, i.e. making |dvdp/dt|≤ 0 (inequality constraint) for each error signal p= 1,2,3 . Since the optimization formulation requires a generic formulation and the sign of 2.3 Five-level DCC 113 Figure 2.38 Large jumps index sample. Table 2.8 Large jump notation. Index Levels Index m(jm1,jm2)qm 1 1, 3 1 2 2, 4 1 3 3, 5 1 4 1, 4 2 5 2, 5 2 6 1, 5 3 each vdp is unknown initially, the eight possible cases, corresponding to the eight combinations of signs, have to be considered. Cost function The cost function should be formulated in such a way that it reflects the objectives pursued for the converter from a practical point of view. For this, the optimal result should attend the following considerations • Minimization of the number of commutations, i.e. the duty ratios dij that are different from zero. With this, the switching losses are reduced as much as possible. • Some sets of duty ratios are not desired and they should be penalized. These are the cases of what is referred as large jumps from now on, that is ∃k1,k26= 0∈Ns.t. di(j−k1)6= 0, dij = 0, di(j+k2)6= 0 . Considering that the levels whose duty ratios are not zero will be sequenced by the modulator, it is not desired to have transitions between two non-consecutive levels as they introduce larger output voltage changes, more voltage stress on the switching devices, and larger current ripples. This consideration could be introduced as a constraint, but it may lead to an infeasible optimization problem. Hence, they are included here in the cost function as a penalization. The first consideration is taken into account by introducing a set of integer variables sij ≥0 for every phase i and level j in such a way that sij must be equal to one if dij 6= 0 . By imposing sij to be integer and sij −dij ≥0; sij ≥0,(2.132) the value of sij is forced to be greater than one if dij >0 . Thanks to this, the commutation minimization can be sought by defining the following term of the cost function fcost1=X i=a,b,c 5 X j=1 sij.(2.133) The second consideration can be included in the cost function as follows. Firstly, the large jumps are classified using the index m : there are six possibilities (depicted in Fig. 2.38, where the jumps are depicted from lower levels to higher ones, but the reverse case 114 Chapter 2. Contributions to Diode-Clamped Converters follows the same notation) whose notation and levels involved are shown in Table 2.8. Secondly, they have to be detected, and thirdly, penalized in the cost function. Using variables jm1 and jm2 for the outer levels in the considered jump, the detection stage for phase i must search for the occurrence of dij 6= 0 for j=jm1,jm2 and dij = 0 for jm1< j < jm2 , which would mean that no level is active between the outer levels jm1 and jm2 . This can be accomplished by introducing two additional integer—in fact, binary— variables rim , pim for i=a,b,c and m= 1,...,6 and two additional constraints. Variables rim are used to detect when the border levels ( jm1,jm2 ) are both active for the solution candidate under consideration, while variables pim are used to detect if, additionally to rim = 1 , the intermediate levels are all inactive. In general terms, these two constraints are expressed for every m= 1,...,6and i=a,b,c as: sijm1+sijm2−rim ≤1; rim ≥0(2.134) rim −pim − jm2−1 X j=jm1+1 sij ≤0; pim ≥0(2.135) In this way, the penalization for large jumps can be included in the cost function by penalising the existence of pim = 1 . Furthermore, an additional integer variable qm is used to penalise larger jumps by making it equal to the number of additional switches this large jump implies, that is, qm=jm2−jm1−1(also shown in Table 2.8). In this way, fcost =fcost1+X i=a,b,c 6 X m=1 pimqm. (2.136) In summary, the optimization problem formulation and the involved variables are depicted in Fig. 2.39. Additionally, an example of the variables values associated with a particular case is given for the sake of clarity. Optimization problem On the one hand, with this cost function formulation, the resulting problem has 67 unknowns: •15 variables dij . •15 variables sij . •6 variables rim for each phase i=a,b,c: 18 variables. •6 variables pim for each phase i=a,b,c: 18 variables. •The variable xassociated with the modulation. On the other hand, there are six equality constraints (Eqs. (2.129) and (2.131) ) and fiftyfour inequality constraints (Eqs. (2.132) , (2.134) and (2.135) , and the derivative of the capacitor voltage errors). Besides, the cost function and the constraints are linear, and thus a linear mixed-integer optimization problem is formulated. 2.3 Five-level DCC 115 Figure 2.39 Optimization problem and example of codification for one point. As it was stated at the beginning of this section, this optimization is carried out in the modulation stage, which means that the current/power controllers have already computed the control signals (referred as u1,u2 or uα, uβ in previous sections) in such a way that the dc-link voltage value and power references are tracked. However, the previous optimization problem has a large computational burden to be implemented online in an acceptable sampling rate, and therefore it is proposed the use of look-up tables (LUTs). For this, a steady-state simulation over a grid period considering normalized state variables with N sampling instants is carried out and the resulting control signals are stored. Then, the optimization problem is solved offline with the MATLAB ® Optimization Toolbox, function intlinprog , using these control variables as inputs for every sampling instant. The resulting duty ratios are then stored in the LUTs for further online implementation. Due to the fact that the constraints related to the voltage errors vdp depend on the sign of them, and these signs can change during online operation, even at steady-state conditions— the error signal would fluctuate around 0—, eight optimization problems are solved, one for each combination of these signs, and eight LUTs are stored. At this point, the optimization problem has been solved offline under steady-state conditions for N different points considering eight possible combinations of the voltage error signals. The next section proposes a procedure for the use of the resultant tables in the online control law. Control law implementation According to the information obtained from the steady-state simulations and the offline resolution of the optimization problem, each table is filled with the solution of the optimization problem—the values of dij and the x value—for N sampling instants over a grid period. Given the fact that uα and uβ are assumed to be sinusoidal under steady-state conditions, the LUT can be indexed by the angle θ= arctan(uβ/uα) . In the following, some aspects for the use of these LUTs during online operation are explained: 1) row 116 Chapter 2. Contributions to Diode-Clamped Converters selection, 2) Lookup table interpolation and 3) steady-state improvement in order to further reduce the number of commutations. Row selection Once the combination of sign (vd1) , sign (vd2) and sign (vd3) is known, the corresponding LUT can be selected. Then, it is necessary to locate the row corresponding to the stored information which is closer to the current state of the system. For this, the argument of uα,uβ is used as the index variable, and hence the row with the closest angle value to this one will be chosen. Consequently, the row selection will only depend on the output of the current (or power) controller uα,uβ . The fundamentals behind this is that under steady-state conditions for nominal values of the system, the state variables are expected to behave similarly to the simulation, and thus this approximation can be made. Lookup table interpolation Considering the discrete nature of the gathered samples in the LUT, the selected row will not correspond exactly to the measured data, and therefore, an interpolation algorithm must be used to derive the duty ratio values. A usual linear interpolation procedure could be applied but in this way some hard constraints could be violated. For this, a particular interpolation procedure is applied, whose objectives are ordered in descending priority as follows 1. The sums P5 j=1 dij must be equal to 1 for i=a,b,c . This is a requirement for the modulation and cannot be violated. 2. Variables dij must lay between 0 and 1. This restriction is derived from the definition of duty ratio, whose value has to be within this range in order to be feasible. Failing to comply with it would introduce distortion in the controlled variables. 3. Values uα,uβmust be accomplished according to (2.130)–(2.131). 4. The voltage balance must be fulfilled. This objective is important but can be left unattended during some transients in the case its fulfillment opposes the fulfillment of any of the above objectives. Considering the above, the following procedure is used. It is obtained from the LUT which duty ratios dij are different from zero, i.e. the levels j of those nonzero duties for each phase i . It has been observed that, as a result of the optimization, in most sampling instants there is a phase—referred as i0 —that is fixed at one level without switching, while the other two—referred as i1 and i2 —usually commute using only two levels not necessarily consecutive. There are some marginal cases where there is no phase fixed at one level, and they are obviated in this interpolation procedure without affecting the general system performance as it will be shown later. Due to this assumption, the value of x can be determined using (2.131) by imposing that this characteristic is present in the result, i.e. detect the phase i0 and level j whose di0j= 1 in the LUT, and then obtain the value of x in (2.131) that achieves it. Once x is known, the values of ui1 and ui2 can also be computed using (2.131) . Lastly, ui1 and ui2 are fulfilled considering only the nonzero duty ratios obtained from the LUT for each phase i1 and i2 . Considering that it has been assumed that there is only two nonzero duties in the LUT for phase i1 and i2 , the resultant 2.3 Five-level DCC 117 duty cycles are unequivocal considering the objectives 1,2 and 3 listed. Finally, it may occur that the previous procedure yields some duty cycles outside the interval [0,1] , which is infeasible because of the second objective considered. In such cases, the voltage-balance objective is obviated, as stated is the last objective, and the corresponding ui is achieved by distributing it between the two nearest levels—the levels that are the closest integers to ui. A simplified control scheme of the proposal is depicted in Fig. 2.40. Figure 2.40 Implementation and control scheme of the proposed approach. Steady-state improvement This approach may present an increased harmonic distortion in the grid current in steady state due to sudden changes of balancing criterion from one sampling instant to the next one. Indeed, when the error signals are close to zero, a change of their signs is likely to happen, and it would imply changing the lookup table among the eight entries, probably yielding to an abrupt change in the modulation criterion. This phenomenon is, by itself, acceptable, however, when it occurs several times consecutively, it distorts the grid current as additional commutations are introduced in each transition. Another aspect to take into account is that it is not necessary that the balancing error signals tend to zero but to remain close to zero. Therefore, a modification in the algorithm described above—referred as base algorithm from now on—is proposed. The modification—referred as enhanced algorithm—tries to avoid, in steady state, frequent changes of balancing criterion. In the enhanced algorithm, the change of balancing criteria —change from one of the eight lookup tables to another— is limited to occur only when one of the error signals vdp is large enough. Therefore, a threshold ν is defined in such a way that when the absolute values of the three vdp are smaller than it, the active lookup table is not changed. Only when one of them exceeds ν , the lookup table is changed using the “normal” procedure exposed above. The larger the value of ν is, the lesser the times the change of criterion would occur, but larger values of vdp would be allowed. As a result, the values of vdp 118 Chapter 2. Contributions to Diode-Clamped Converters Table 2.9 Control and System Parameters. Parameter Value Parameter Value Grid freq., fg50 Hz Samp. and swit. freq., fs,fsw 10 kHz Grid volt., vgabc 230VRMS Power factor 1 Filter Ind., L2mH Prop. Pow. Cont., Kp(DPC) 2e−7 dc-link cap., C3300 µF Int. Pow. Cont., Ki(DPC) 2e−5 dc-link load, R120 →60 Ω Prop. Volt. Cont., Kdc p0.05 dc-link volt. ref., v∗ dc 700 →800 V Int. Volt. Cont., Kdc i1 Enhanced band, ν10 V Samp. for LUT gen., N100 will be enclosed inside a band of width 2ν around 0 at the same time that the grid current will present a better harmonic distortion. In the following, the base algorithm and the enhanced one will be compared by means of simulations with other approaches, and between themselves in experiments. Simulation results This section is devoted to present some simulation results carried out in MATLAB- Simulink ® that compares the current optimization approach with some well-known approaches for five-level DCCs with balancing capabilities. The system under consideration is the same than the one presented in previous sections, i.e. a five-level DCC in rectifier configuration. The used simulation and control parameters are shown in Table 2.9, which includes the parameters considered for the LUTs generation. In this regards, N= 100 samples in a grid period were considered for each combination of signs of vdp , which resulted on the resolution of 800 optimization problems. The time needed to solve such number of problems were around 20 secs. Firstly, the LUTs are generated assuming steady-state conditions. The used controllers, either for the LUTs generation and the simulations, follow the general scheme of a cascaded control loop, with the outer loop being a PI controller (parameters Kdc p and Kdc i ) in charge of regulating vdc towards its reference, and the inner loop being the model-based DPC controller (shown in Sect. 2.3.3 with parameters Kpand Ki). For the comparison, two approaches are considered from the literature with balancing capabilities [89,134], in addition to the two approaches presented in Sect. 2.3.3. Paper [134] uses a modification of the well-known SVM and will be referred as space-vector based algorithm (SVBA), paper [89] uses the FCS-MPC to control a grid-connected NPC inverter, whereas the approaches presented in Sect. 2.3.3 will be referred as original integrated control and modulation (OICM), for the base proposal, and modified integrated control and modulation (MICM), for the further improvement. Notice that despite the FCS-MPC presented in [89] is designed for three-level converters, the cost function is modified in this section to be valid for five-level converters, similarly to [135]. Regarding FCS-MPC, as the switches can only occur at the sampling instants, three simulations are presented for different sampling frequencies (fs): 10, 25 and 50 kHz. The phase currents obtained from simulation for these approaches are depicted in Fig. 2.41, and the switching states in Fig. 2.42, both with v∗ dc = 800V and R= 60Ω . Notice that the lookup tables were designed for v∗ dc = 700V . Consequently, these results show 2.3 Five-level DCC 119 Table 2.10 THD value and number of commutations (variation in % respect to base algorithm). Algorithm THD Number of commutations Base 4.63 645 Enhanced 4.05 (-12%) 550 (-15 %) SVBA [134] 7.01 (+51%) 935 (+45 %) FCS-MPC [89] (10 kHz) 13.42 (+190%) 210 (-68 %) FCS-MPC [89] (25 kHz) 5.10 (+10%) 540 (-16 %) FCS-MPC [89] (50 kHz) 2.54 (-45%) 1100 (+70 %) OICM [119] 5.40 (+16 %) 1600 (+148%) MICM [119] 4.20 (-9 %) 1333 (+106%) that this approach is also valid for some operating point that were not considered in the design. The resulting current THD values and number of commutations in a grid period are shown in Table 2.10, where their variation in % with regard to the base algorithm presented in this paper are also highlighted. Notice how the proposed base and enhanced algorithms exhibit lower current distortion and lower number of commutations than SVBA and OICM. On the contrary, MICM achieves slightly better current distortion than the base algorithm at the cost of much larger number of commutations. In terms of the FCS-MPC approach, higher frequencies usually result in less current distortion, larger number of commutations and more demanding computational burden. It can be seen that FCS-MPC with the same fs than the base algorithm yields unacceptable current distortion (13.42 %). In order to achieve a more feasible current distortion, the sampling rate has to be increased from 10 k Hz to 25 k Hz, for which the currents reach a THD value of 5.1 %, which is closer to the value of the base algorithm (4.63 %). At the same time, the number of commutations is increased proportionally to the sampling rate—again, this is true as long as the weights in the cost function of FCS-MPC are not changed—, which, for 25 k Hz, reaches a similar number of commutations than the enhanced algorithm (540 vs 550). Larger sampling rates (50 k Hz) further reduce the current distortion (2.54 %) and increase the commutations (1100). In summary, in terms of current distortion and number of commutations, the base and enhanced algorithms exhibit a better behaviour than SVBA [134] and the previously presented OICM with fs= 10 k Hz, while FCSMPC [89] has to appeal larger sampling rates to achieve similar performance. It is worth to mention that FCS-MPC uses a cost function whose weights can be modified as a tradeoff between current distortion, capacitor voltage balance and number of commutations. These simulations were carried out using the weights that achieve the capacitor voltage differences to be less than ν in steady state. Alternatively, MICM improves the current distortion when compared with the base algorithm (4.2 % vs 4.63 %) at the cost of yielding twice the number of commutations. Nonetheless, the proposed enhanced algorithm further improves the base algorithm performance achieving lower distortion and commutations than MICM. As it has been mentioned, the improvement in the current distortion and number of commutations for the enhanced algorithm is due to the relaxation in steady state of the capacitor voltage balance criterion, as they are not forced to go to zero but to keep around 120 Chapter 2. Contributions to Diode-Clamped Converters Figure 2.41 Three-phase currents in steady state when R= 60Ω and v∗ dc = 800V for the base algorithm (top), the enhanced one ( 2nd ), the SVBA [134] ( 3rd ), the FCS-MPC [89] ( 4th ) considering three sampling rates (10, 25 and 50 k Hz), and the OICM and MICM (bottom). The THD values of these currents are shown in Table 2.10. a band of value ν . In this way, the change of balancing criterion—the selected lookup table (LUT) among the available 8— is done much less frequently as it can be seen in Fig. 2.42. Regarding voltage balancing capabilities, a simulation starting from an unbalanced situation is depicted in Fig. 2.43 ( vd1=−40 , vd2= 60 , vd3=−5 ). At t= 1s , the balancing strategy for every approach is enabled showing the evolution of the capacitor voltages. The FCS-MPC algorithm exhibits the fastest performance but, because of the initial large values of {vd1,vd2,vd3} , the current tracking is not prioritized in the cost function until these values are low enough. Therefore, there exists a transient where 2.3 Five-level DCC 121 Figure 2.42 Switching state of phase a of the converter output with v∗ dc = 800V and R= 60Ω , for the base algorithm ( 1st ), the enhanced one ( 2nd ), the SVBA [134] ( 3rd ), the FCS-MPC [89] ( 4th ) considering three sampling rates (10, 25 and 50 k Hz), and the OICM and MICM (bottom). The number of commutations for each approach is shown in Table 2.10. the current tracking is affected. Besides, due to the same reason, there exist nonzero steady-state errors in the capacitor voltage balancing that depend on the cost function weights considered for the balancing task. Additionally, the larger the sampling frequency, the faster the balancing. The SVBA algorithm shows a slower balancing (around 500 ms to reach steady state) but reaching almost zero steady-state error. The OICM and MICM approaches have three capacitor voltage balancing control parameters ( k1,k2,k3 in Sect. 2.3.3) that determine the speed of the balancing. A higher value would yield a faster balancing response and lower steady-state error at the cost of a worse power tracking transients, similarly to the FCS-MPC. Nevertheless, these simulations used the 128 Chapter 2. Contributions to Diode-Clamped Converters and hp variable, respectively. Considering that the balancing of all capacitors should prioritize the convergence speed of the error signals, these weighting factors are selected such that α1α . Besides, this added term should only be taken into account to select the optimal solution when the original cost function shows no difference between two candidates, and therefore α1α1 . Considering that sign(vdp) is known beforehand, the cost function and all the constraints are still linear, and thus the optimization problem is still linear, mixed-integer. Optimization problem solution Again, the optimization problem must be solved offline due to its large computational burden. For this, the steady-state behaviour of the system under nominal conditions is simulated over a grid period, and N samples are stored for the state variables of the system. The steady-state and nominal conditions involve the following assumptions 1. Sinusoidal phase currents and grid voltages. 2. Dc-link voltage and reactive power equal to their references. 3. Active power equal to the one demanded by the resistive load attached to the dc-link. 4. Capacitor voltages perfectly balanced. The simulation considers the averaged model of the system, which gives the unitary value of the phase currents and the value of the control signals uα , uβ for every sample. Using this information, the optimization problem is solved and the corresponding duty ratios are obtained. Given that the optimization resolution requires the knowledge of the values of sign( vdp ), they are assumed beforehand, resulting in eight possible scenarios for every simulation. Note that, following this procedure, the results obtained are associated with one value of dc-link voltage reference and reactive reference. The previous proposed approach was to store these results in eight LUTs to be used later during online operation. Despite the fact that it proved to give good results for the nominal conditions, large variations of the reactive power makes the balancing error signal to diverge from zero. For this, it is proposed to simulate several conditions of dc-link voltage and reactive power references, to solve the optimization problem for every sample and gather the results in eight different datasets. Similarly to the previous approach, it is noticed that the solution usually has one duty ratio equal to 1, i.e. the corresponding phase is fixed to that level and it does not use any other level, while the remaining phases have only two duty ratios different from zero. Consequently, it is assumed that the adopted solution will follow this principle: One phase fixed to one level, and two phases commuting between two levels each. In order to achieve generality, each result is coded into a variable that takes this principle into account, and it is stored in the previous datasets. The CART algorithm is later trained with these datasets being the coded result the output of such CART. The following subsection will provide more information about the coding of the CART inputs and the results. Fig. 2.49 shows the scheme of the training process. The resultant algorithm (the classification trees) can be implemented online, and given that several operating points are considered, a wide range of operating points is expected to be covered as it will be shown in the simulation and experimental sections. 2.3 Five-level DCC 129 Figure 2.49 Flowchart of the carried out steps to obtain the decision trees based on the optimization problem. CART algorithm As depicted in Fig. 2.49, the input data should represent the potential values of the currents and control signals, and therefore, it is convenient to codify these information in a qualitative manner aiming for generality. Additionally, in order to synthesize the CART output information, the result is coded following a simple rule that is exhibited in this section. Input data for the CART algorithm Considering the grid voltage and current nature and, in order to establish a more generic training dataset for the CART, some qualitative information has to be extracted from them. The qualitative criteria was based on expert knowledge and the analysis of the optimization results for several test cases. Regarding the potential values of the homopolar component x , Eq. (2.131) is recalled, where its limits can be derived by knowing that ui∈[−2,2] . Therefore, these limits are defined and referred as xmin =−2−min(ηa,ηb,ηc) and xmax = 2−max(ηa,ηb,ηc). The considered qualitative data are defined as follows • The sign of the currents ia,ib,ic : −1 for negative values, and 1 for positive values. (3 values) • An integer number for each phase i=a,b,c ( leveli ) that indicates between which two levels the associated voltage reference ηi is found (obtained from the reverse Clarke transformation of uα and uβ for x= 0 ). The code for this number is shown in Table 2.11. (3 values) • A code ( r ) that indicates the order relation among ia,ib and ic . This code is shown in Table 2.12. (1 value) • Variables yij for i=a,b,c and j= 1,2,...,5 are set to 1 when there exists a value of x fulfilling xmin ≤x≤xmax such that the corresponding value of ηi+x is equal to j . This means that, for the current sample data, it is possible to consider a value of the homopolar component x such that ui is equal to level j , while ui∈[−2,2] for i=a,b,c . Therefore, yij = 1 if xmin ≤j−3−ηi≤xmax , and yij = 0 otherwise. (15 values). 130 Chapter 2. Contributions to Diode-Clamped Converters Table 2.11 Integer number to indicate associated levels for ηi. leveliηileveliηi 1 [-2,-1] 3 (0,1] 2 (-1,0] 4 (1,2) Table 2.12 Integer number to indicate current order. rCurrent order rCurrent order 1ia≥ib≥ic4ic≥ib≥ia 2ia≥ic≥ib5ib≥ic≥ia 3ic≥ia≥ib6ib≥ia≥ic Table 2.13 Integer number a1to indicate which dij equals one. a1(i,j)a1(i,j)a1(i,j)a1(i,j)a1(i,j) 1 (a,1) 2 (a,2) 3 (a,3) 4 (a,4) 5 (a,5) 6 (b,1) 7 (b,2) 8 (b,3) 9 (b,4) 10 (b,5) 11 (c,1) 12 (c,2) 13 (c,3) 14 (c,4) 15 (c,5) Table 2.14 Integer number a2/a3to indicate pair of used levels. code levels code levels code levels 11−251−381−4 22−362−492−5 33−473−510 1−5 44−5 Output data for the CART algorithm The decision tree output is coded assuming that the optimization problem resolution will have one phase fixed at one level, while the other two phases commute between two different levels. Among the obtained results of the optimization problem, few of them did not follow this distribution, and therefore, they were not included in the training dataset. A code that captures the assumed information is defined by using three variables a1,a2,a3 : • Variable a1 indicates the pair of values i and j such that dij = 1 , i.e. the phase i that is fixed at level j . These values are shown in Table 2.13 covering 15 possible values. • The other two phases only commute between 2 levels. Consequently, a2 and a3 indicates these pair of levels for each phase. The correspondence of a2 and a3 with the phases follows alphabetical order: for example, if the phase represented with variable a1 is phase b , code a2 corresponds to phase a and code a3 to phase c . The pairs are coded by enumeration as shown in Table 2.14. As a result, variables a2 and a3cover 10 combinations each. Considering the combination of the three variables into one, 15 ×10 ×10 = 1500 possible values are obtained. This variable, referred as output code, is used as the output for the CART algorithm and it is computed as follows Output code : (a1−1) ·102+(a2−1)·10+a3−1,(2.143) 2.3 Five-level DCC 131 Figure 2.50 Example of a decision tree obtained for vd1>0,vd2>0,vd3>0 with the output shown in bold. which represents an unique combination of the three integer variables. Decision trees generation The trees are generated using the recursive partitioning and regression trees technique from the rpart library for R lenguage. The arguments of this function are: the input-output variables defined previously; the classification method, which is set as “class"; the way the decisions are considered, in this case, through the complexity parameter cp , which determines that a split is not carried out if it does not decrease the overall lack of coverage by the value of cp ; and a vector of cost values. The latter vector contains one cost value for each considered input in such a way that the inputs with larger cost values associated would appear less frequently in the decision tree. The value of cp is tuned in such a way that a minimum of 85 % of coverage of the training data set is obtained for every decision tree. In summary, there exist 22 variables to be used as input parameters and one coded integer result whose value could range from 1 to 1500. Gathering all these information for every combination of sign(vdp) into one dataset for all samples within one grid period, the CART algorithm can be trained, and a decision tree is obtained as a result. As an example, the generated tree for the three positive signs of vdp is depicted in Fig. 2.50, where it can be seen that a maximum of nine comparisons are needed in each execution of the tree, which is an easy and fast task for real-time implementation purposes. Decision trees implementation Once the decision trees are obtained, they can be easily implemented into the corresponding control system by means of nested “if...else” statements. During online operation, the qualitative information used for the CART training is extracted from the measurements and control signals uα and uβ , the combination of sign(vdp) determines the corresponding decision tree and it is consulted with this information, resulting in the output code. Then, the following procedure is carried out for the modulation stage 1. Variables a1,a2 and a3 are obtained from the output code. To depict an example of the decoding process, let us consider an output code of 574 from Fig. 2.50, then variables a1,a2,a3are extracted by means of simple integer division as follows a1=floor(code/102)+1 = 6 (2.144) a2=floor((code−a3·102)/10)+1 = 8 (2.145) 132 Chapter 2. Contributions to Diode-Clamped Converters a3=floor((code−a3·102−a2·10))+1 = 5 (2.146) where floor refers to the function that outputs the largest integer that is less than or equal to the input. 2. Using (2.131) and the information provided by a1 (Table 2.13), i.e. which j and i should fulfill dij = 1, the value of xis obtained. 3. By knowing x and the information provided by a2 and a3 , i.e. which pair of j values for each of the remaining phases should fulfill dij 6= 0 , the remaining dij are computed. Note that, as it has been assumed that these phases commute using two levels, the determination of dij is unequivocal. At this point, it could happen that the code obtained from the corresponding decision tree might not be implementable in the considered instant. This is the case when the uα,uβ values cannot be represented using the levels indicated by a1 , a2 and a3 . To cover this issue, the following implementation procedure is proposed: 1. The result is decoded and the levels to be used for each phase are obtained according to a1,a2 and a3 : phase fixed at one level will be referred as ifix and the corresponding level as lfix ; and the other phases—referred as i1 and i2 —are fixed at two different levels, each one referred as j11,j12 and j21,j22 respectively. 2. The indicated fixed phase ( ifix ) should be accomplished at the specific level ( lfix ), that is: xmin ≤lfix −3−ηifix | {z } xfix ≤xmax.(2.147) If this can be accomplished, then x=xfix , otherwise x is saturated to the closest value xmin or xmax such that it is still fixed at one level. 3. Phases i1 and i2 follows a similar idea. For each of them, they should be modulated using the indicated levels taking into account the previous value of x . This is feasible only if the following condition is fulfilled for each phase j11 ≤ηi1+3+x≤j12 (2.148) j21 ≤ηi2+3+x≤j22.(2.149) In the case the condition for the corresponding phase is not fulfilled, the used levels for that phase are modified to the nearest ones, that is the closest integer values above and below of (ηi+3+x). Thanks to this procedure, a more robust implementation is given that prioritizes the constraints associated with uα and uβ(2.131) . This implementation scheme is depicted in Fig. 2.51. Despite the fact that the previous procedure aims for a robust implementation, the obtained duty ratios might not be the optimal values according to the formulated problem, which is the reason why this proposal is referred as pseudo-optimal modulation. Besides, 2.3 Five-level DCC 133 Figure 2.51 Implementation scheme to guarantee proper uα,uβmodulation. there are other potential sources of error that could make the implemented result to diverge from the optimal one: 1. The measured variables, as well as the values of uα and uβ , may not correspond exactly to any of the training data sets, and therefore the result is inferred from the training datasets. 2. The CART algorithm has a coverage error and not all cases used for the training are correctly matched in the output given by the decision trees—The ones created for this work had a minimum coverage above 85 %. 3. Those cases that did not follow the generic rule of one phase fixed to one level and the others using only two levels were neglected from the dataset. Nevertheless, they represented less than 3 % of any of the solved optimization problem. Despite this, simulation and experimental testing show satisfactory results, as it is shown in the following sections. Simulation results Similarly to the LUT-based approach, this proposal is compared in simulation with other modulation approaches in order to exhibit its main differences and similarities. For this, some simulations are carried out in MATLAB-Simulink ® with the converter and control parameters shown in Table 2.15. Due to the fact that this proposal considers that the uα and uβ values are already determined by an inner controller that is out of the aim of the considered objectives, the well-known nonideal PR controller is used [34] for this purpose, with the control parameters depicted in Table 2.15. Similarly, the outer controller in charge of regulating vdc towards v∗ dc is considered to be an standard PI controller. The parameters that are required for the CART generation and training are also shown in Table 2.15. The operating points considered in the generation of the training dataset are shown in Table 2.16. Lastly, the cost values considered for the CART training algorithm are selected and justified as follows 134 Chapter 2. Contributions to Diode-Clamped Converters Table 2.15 Converter Parameters. Parameter Value Parameter Value Grid freq., f50 Hz Sampling freq., fs10 kHz Grid voltage, vgabc 230VRMS Switching freq., fsw 10 kHz Inductance, L2mH Prop. gain PR, kp5 Capacitance, C3300 µF Resonant gain PR, kr200 dc-link load, R[60,inf] Ω Prop. gain dc-link, Kdc p0.05 dc-link voltage reference, v∗ dc [700,800] V Integral gain dc-link, Kdc i1 Samples for optimization, N100 LPF cut-off freq. (PR), ωc2π5rad/s Opt. weighting factor, α10.01 Resonant freq. (PR), ωr2π50 rad/s Opt. weighting factor, α0.001 CART complex param., cp 0.002 Table 2.16 Operations points considered for the training data set. nºvdc (V) p(kW) q(kVA) nºvdc (V) p(kW) q(kVA) 1 800 10 0 2 800 0 10 3 800 0 -10 4 700 10 0 5 700 0 10 6 700 0 -10 • The sign of the currents and their order code ( r ) keep the same value for a large number of samples within one grid period, and thus they should be consulted less frequently: Cost value = 5 • Variables level i are the next considered as they change more frequently: Cost value = 2.5 • Variables yij are the easiest to classify due to their binary nature, and they also provide useful information about the feasible values of x: Cost value = 1. As it was mentioned previously, the larger the cost value assigned to an input, the less frequently they are included in the decision tree. The five additional modulation methods for five-level DCC converters that are simulated in this section, apart from the proposed one (referred as CART), are the following ones: the original proposal of the optimization problem implemented through a look-up table exhibited in the previous section and presented in [117] (LUT), a space-vector based algorithm (SVBA) [134], a model-predictive control based on finite control set (FCSMPC) [89], and the two integrated control and modulation methods proposed previously exhibited and extracted from [116] (OICM and MICM). As it was mentioned in Sect. 2.3.6, the FCS-MPC approach requires larger switching frequencies to achieve a similar switching performance than those PWM-based approaches, as the switching may only take place at those instants. Therefore, three sampling and switching times are considered for the FCS-MPC: 10, 25 and 50 k Hz, similarly to the previous section. See the simulation section (Sect. 2.3.6) of the previous approach for a brief explanation of each one of these approaches. 2.3 Five-level DCC 135 Figure 2.52 Three phase currents at steady-state conditions of the approaches considered. Firstly, the phase currents in steady state ( vdc = 800 V, R= 60Ω , q∗= 0k VA) for each of the modulation methods are depicted in Fig. 2.52. Similarly, the switching output of each of them under the same conditions are depicted in Fig. 2.53. For ease of comparison, the performance indicators: total harmonic distortion (THD) and number of commutations over a grid period, extracted from these figures are shown in Table 2.17. As it is expected, the proposed method achieves similar current distortion value than the LUT-based method, given that both performs under the same optimization formulation, and the operating point is the one considered for the LUT obtention. In terms of number of commutations, the proposed method (CART) achieves a reduction in the number of commutations (550 vs 645). This could be explained from the generalization capability of the CART, which overrides the less frequent cases with another more frequent case when they have the same CART inputs and different outputs. Therefore, simulations show that CART implementation achieves a better performance in steady state compared 136 Chapter 2. Contributions to Diode-Clamped Converters Figure 2.53 Switching state of phase aof the approaches considered. to the LUT–based implementation, even under the conditions for which the LUT was implemented. In terms of comparison with the other approaches, CART implementation achieves better current distortion and lower number of commutations than OICM and SVBA. Alternatively, MICM shows an improvement in the current distortion at the cost of yielding more than twice the number of commutations. Similarly, FCS-MPC requires to increase the sampling frequency to yield lower current distortion, which also comes at the cost of increasing the number of commutations. Nevertheless, at 25 k Hz, FCS-MPC exhibits a similar number of commutations than CART (540 vs 550) but an increased current distortion. Lastly, to depict the capacitor voltage balancing capabilities for the considered methods, Fig. 2.54 is depicted. This figure shows how the capacitor voltages evolve when the balancing start at t= 1 from an unbalanced voltage condition ( vd1=−40,vd2= 60,vd3= −5 for t < 1 ). To evaluate the flexibility of each approach, several tests has been performed 2.3 Five-level DCC 137 Figure 2.54 Capacitor voltages evolution starting from an unbalanced situation vd1= −40,vd2= 60,vd3=−5 for all the considered approaches under different tests whose power references are shown at the top of the figure. vdc = 700 V.