A CMOS 110-dB@40-kS/s programmable-gain chopper-stabilized third-order 2-1 cascade sigma-selta modulator for low-power high-linearity automotive aensor ASICs

2246 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 11, NOVEMBER 2005 A CMOS 110-dB@40-kS/s Programmable-Gain Chopper-Stabilized Third-Order 2-1 Cascade Sigma-Delta Modulator for Low-Power High-Linearity Automotive Sensor ASICs José M. de la Rosa, Member, IEEE, Sara Escalera, Belén Pérez-Verdú, Fernando Medeiro, Member, IEEE, Oscar Guerra, Rocío del Río, Member, IEEE, and Angel Rodríguez-Vázquez, Fellow, IEEE Abstract—This paper describes a 0.35- m CMOS chopper-sta- bilized switched-capacitor 2-1 cascade 61 modulator for automotive sensor interfaces. The modulator architecture has been selected from an exhaustive comparison among multiple topologies in terms of resolution, speed and power dissipation. To obtain a better fitting with the characteristics of different sensor outputs, the circuit can be digitally programmed to yield four input-to-output gain values ( 0 5 1 2 , and 4 ) and has been designed to operate within the stringent environmental conditions of automotive electronics (temperature range of 40 Cto 175 C). In order to relax the amplifier’s dynamic requirements for the different modulator input-to-output gains, switchable capacitor arrays are used for all the capacitors in the first integrator. The design of the building blocks is based on a top-down CAD methodology which combines simulation and statistical optimization at different levels of the modulator hierarchy. The circuit is clocked at 5.12 MHz and the overall power consumption is 14.7 mW from a single 3.3-V supply and occupies 5.7 mm 2 silicon area. Experimental results show a maximum SNR of 87.3 dB within a 20-kHz signal bandwidth and 90.7 dB for 10-kHz signals, and an overall DR of 110 and 113.8 dB, respectively. These performance features place the reported circuit at the cutting edge of state-of-the-art high-resolution 61 modulators. Index Terms—Analog-to-digital conversion, sigma-delta modulation, mixed analog-digital integrated circuits, sampled data circuits. I. INTRODUCTION DURING the last few years there has been a significant increase in the use of electronic sensory systems for the automotive [1]. This is partially fuelled by advances in MEMS technology and the possibility to combine sensors together with DSPs on the same package and even the same chip [2]. Linked to this trend, the necessity arises to design CMOS analog front-ends (AFEs), and specifically analog-to-digital converters (ADCs), capable of coping with the stringent requirements of the automotive industry. Fig. 1 shows a typical conceptual block diagram for an automotive sensor chip. On the one hand, the converter must be compliant with a very large temperature range, typically Manuscript received February 15, 2005; revised July 5, 2005. This work was supported by the EU ESPRIT IST Project 2001-34283/TAMES-2 and by the MCyT Projects TEC2004-01752/MIC and TIC2003-09817-C02-01 (VISTA). The authors are with the Instituto de Microelectrónica de Sevilla, IMSE-CNM (CSIC), 41012-Sevilla, Spain (e-mail: [email protected]. Digital Object Identifier 10.1109/JSSC.2005.857356 ([ 40 C, 175 C]), and with many other hostile environmental issues [3]–[5]. On the other hand, the AFE must cope with weak signals (ranging from microvolts to hundreds of milivolts) in the presence of large temperature and process dependent offset. The changing amplitude range of the input signal can be handled through programmable gain—similar to what happens in multipurpose sensors [5]. Also, large accuracy and bandwidths up to 10–20 kHz are needed at the ADC to increase the quality of the information delivered to the DSP, and hence the smartness of the system [2]. It is advised that -based ADCs are used to handle these challenges due to different reasons: •They are better suited than full Nyquist ADCs to achieve high resolution (16–17 bit) in the band of interest with moderate power consumption [6], [7]. •The action of feedback renders sigma-delta modulators (Ms) very linear, and high linearity is a must for automotive applications. •The behavior of some sensing devices fits well to -based ADCs, thus easing partial or total integration of the sensor within the converter [8], [9]. •Ms can incorporate programmable gain without significant degradation. However, detailed modeling of circuit nonidealities and involved design plans are needed to take advantage of all these potentials while addressing the stringent environmental and robustness requirements. Actually, several Ms that digitize 20–25 kHz signals with medium-to-high resolution have been reported [10]–[13]. To the best of our knowledge, the highest resolution (18.7 bits) is featured by the modulator in [11], whereas the lowest power consumption is reported in [12], which targets 14 bits within a 20-kHz signal bandwidth. In all these cases, the modulator input-to-output gain1was fixed to unity. This paper reports a programmable-gain chopper-stabilized third-order cascade (2-1) M in a 3.3-V 0.35- m CMOS technology. Its design relies upon detailed behavioral modeling and the use of an advanced top-down methodology that combines multilevel behavioral simulation and statistical optimization at different levels of the hierarchy [7]. Experimental results show correct operation in a 20-kHz bandwidth 1In the following, the term “modulator input-to-output gain” will be referred to as “modulator gain”. 0018-9200/$20.00 © 2005 IEEE DE LA ROSA et al.: THIRD-ORDER 2-1 CASCADE SIGMA-DELTA MODULATOR FOR LOW-POWER HIGH-LINEARITY AUTOMOTIVE SENSOR ASICs 2247 Fig. 1. Conceptual block diagram of a “smart”sensor chip. with 110-dB overall dynamic range (DR), and 113.8-dB DR within kHz. These figures locate this circuit at the cutting edge of state-of-the-art CMOS Ms. Also, the herein reported modulator IC is one of the few high-resolution circuits with embedded programmable gain reported to date. This paper is organized as follows. Section II describes general design considerations. Section III applies those considerations to the proper selection of the modulator architecture and obtains a set of optimized specs for the constituent building blocks. These specs are inputs for the electrical design of the circuit cells, which are covered in Section IV. Finally, Section V gives experimental results and compares the performance of the chip with current state-of-the-art designs. II. BASIC DESIGN CONSIDERATIONS We choose expandible cascade architectures to implement the modulator [14]. These architectures are advisable as they do not raise stability issues and permit an input voltage amplitude that is close to the theoretical full-scale (FS) input range of the modulator without causing overloading. Actually, the family of expandible cascades exhibits a signal-to-noise ratio (SNR) peak at 5 dBFS regardless of the actual modulator order [14].2This helps to handle the changing dynamic range of the sensor signals. Besides, cascade architectures can incorporate a multibit quantizer without resorting to dynamic element matching (DEM) or any other linearization technique [7]. Furthermore, they can be designed by following quite modular, prone- to-optimization plans [14]. Finally, cascade architectures constitute a mature technology demonstrated for a variety of industrial cutting-edge designs [5], [10], [16], [17]. The in-band error power of whatever cascade M can be expressed as [7] (1) where stands for the quantization error, for the circuit noise error, for the nonlinearity error, and for the defective settling error. Ms can be designed such that the quantization error dominates, i.e., such that the following condition is fulfilled: (2) 2The use of multibit quantization in every stage of the cascade modulator might result in SNR peaks close to the theoretical FS voltage [15]. However, linearization techniques need to be used in order to reduce the nonlinearity of the internal D/A converters. where the right term shows the quantization error, neglecting leakage, as a function of the modulator order , the oversampling ratio , and the number of bits in the internal quantizer stands for the FS reference voltage of the M. In our case, and given the high accuracy target, to make the quantization error dominate would lead to huge power consumption and area occupation. Instead, it is more efficient to make the design such that . Two basic considerations arise related to this criterion: first, to make a comparative balance among the several circuit error contributions; second, to find expression linking the dominant circuit errors to the circuit design parameters. Regarding the balance and owing to the limited bandwidth it can be assumed that . Besides, since the available supply voltage grants large enough room for signal excursion, it can be assumed that . Under these assumptions, the basic design criterion reduces itself to equalize the quantization error and the circuit noise error, i.e., . Let us now focus on the expression of the circuit noise error as a function of the circuit design parameters. Consider to that purpose the conceptual schematic of the two-branch switched-ca- pacitor (SC) integrator in Fig. 2, where the input branch and the DAC feedback branch employ different capacitors respectively to implement a modulator gain . The main contributors to the noise error are the operational transconductance amplifier (OTA) thermal and flicker noise, and the switch on-re- sistance thermal noise. Also, noise coming from the generation block must be accounted for as a combination of white noise and flicker noise [18]. Flicker noise will be handled at the architectural level by applying chopper techniques [4], [5], so that only white noise remains to dictate electrical design considerations; i.e., . Careful analysis including folding mechanisms shows that the input white noise power spectral density (PSD) at the input of each branch of the fully differential circuitry can be approximated at low frequencies by [19] (3) where is the Boltzman constant, is the absolute temperature, and is the switch on-resistance. The first term in each equation above contains the contribution of all the switches in the 2248 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 11, NOVEMBER 2005 Fig. 2. Two-branch SC integrator. corresponding branch. The second term accounts for the OTA contribution, where (4) is the OTA equivalent load during the integration phase, while is high. When estimating the white noise PSD of the OTA, the contributions of MOS devices other than the input ones are compiled in the factor , which equals the summation of the respective transconductance ratios. The third term in the expression of represents the noise coming from , where is its equivalent noise resistance. By neglecting contributions other than those of the first integrator in the cascade, the M output white noise power is obtained as (5) Quantitative analysis of (5) shows that the white noise power increases with the M gain, . In practice, this means that as the gain increases, the capacitances must be increased as well, and thus does the power consumption. This is worsened because as increases, the OTA equivalent load increases [see (4)] and hence, more power is needed to meet the dynamic requirements. Seeking minimum power consumption dictates setting as close as possible to unity. Actually, for , the two branches in Fig. 2 can be merged into one, thus further reducing and, consequently, . This is the choice commonly found in literature [5]. However, such a choice implies that in a sensor A/D interface like that shown in Fig. 1, the programmability must be incorporated into the preamplifier, rendering its design more complicated. In the application under consideration, the automotive sensor interface must accommodate a huge range of signal amplitudes (130 dB below full scale) within a 20-kHz bandwidth. For this purpose, the preamplifier is designed with a fixed gain of , whereas the modulator can be digitally programmed to yield four gain values—, and . This solution simplifies the architecture and design of the preamplifier, which in this case consists of a resistor-feedback instrumentation topology—a priori a less demanding design than using a programmable-gain ( , and ) amplifier based Fig. 3. Effective number of bits (ENOB) versus oversampling ratio for three 61 Ms: fourth-order 3-bit ( L =4 ;B =3) , third-order 1-bit ( L =3 ;B =1) and second-order 1-bit ( L =2 ;B =1) . on switchable elements (capacitors or resistors), given the stringent noise and linearity requirements. III. ARCHITECTURE SELECTION AND HIGH-LEVEL SIZING Architecture selection involves three parameters, namely oversampling ratio , loop order , and the resolution of the internal quantizer . These three parameters univocally define an instance of the general expandible cascade architecture [14].3 How are the values of these parameters chosen? A first observation is that, for every value of and ,as increases there is a transition from one region where into another where . It is illustrated in Fig. 3, which shows the effective resolution of three Ms as a function of . The same front-end integrator is used for the three cases. For each curve there is a breakpoint where . Above this breakpoint, within the region dominated by white noise, doubling generates a mere 3 dB decrease in the in-band error power. Below this breakpoint the decrease of the error with depends on the 3The term 2 0 1 is used in this paper to denote a L th-order cascade modulator formed by a second-order stage followed by L 0 2 identical first-order stages. DE LA ROSA et al.: THIRD-ORDER 2-1 CASCADE SIGMA-DELTA MODULATOR FOR LOW-POWER HIGH-LINEARITY AUTOMOTIVE SENSOR ASICs 2249 TABLE I OUTCOME OF THE 61 MARCHITECTURE SELECTION PROCEDURE Fig. 4. Block diagram of the programmable-gain 2–1 cascade SC 61 M. actual values of and . The only way to shift the breakpoint up is by enlarging the sampling capacitor. This observation provides rationale supporting the choice of , namely: •within the region dominated by quantization noise, the sampling capacitor, and hence the demands on building block dynamics, area and power, are larger than needed; •within the region dominated by white noise, oversampling becomes less inefficient (only a fraction of the noise power falls into the signal bandwidth) and either or , or both, may allow a reduction without significant impact on resolution. Actually, most state-of-the-art circuits are designed to operate close to but at the right side of this breakpoint [7]. A second qualitative observation is related to the choice of . On the one hand, the condition defines an univocal relationship between each pair and . On the other hand, since the targeted bandwidth is medium to low, constraints on are not strong. This means that there are fairly large degrees of freedom to set and . As a rule of thumb, since the targeted resolution is only moderately high, the oversampling ratio does not need to be extremely high. This means that the breakpoint in Fig. 3 can be moved to the left, providing room for many possible combinations of and . Actual architecture selection is driven by power minimization, based on the following iterative procedure: 1) For given values of , and , calculate and select so that is smaller than the maximum allowed in-band error power. 2) Estimate from (4). Then, use a linear settling model with settling constant to estimate the required OTA transconductance, taking into account that it takes a number of time constants to settle within effective number of bits (ENOB) resolution. 3) Relate the OTA with its power dissipation, for which the candidate OTA topology must be known a priori.A suitable selection is closely linked to the process technology: supply voltage, minimal device length, etc. Potential choices are a folded-cascode OTA up to 3-V supply, and a two-stage amplifier below 2.5 V [20]. 4) Once the first integrator power dissipation is estimated, that of the remaining integrators (in practice with less demanding specifications) can be estimated as a fraction of it. The overall static power is then obtained by adding up all the contributions. For realistic estimation, this procedure is fine-tuned by including the impact of other nonideal effects (such as finite and nonlinear OTA DC-gain, slew-rate, errors in the multibit quantizers, etc.), the power dissipated in other blocks, and the dynamic power dissipation [14], [16]. A. Modulator Architecture Previous design considerations have been applied for the target specs of 40 kS/s and DR dB. A large number of architectures have been compared in terms of the estimated power consumption and silicon area. The outcome of the comparison, summarized in Table I for Ms with a 1-bit internal quantizer, led us to choose the third-order 2-1 cascade M shown in Fig. 4 with . Note from Table I that the 2250 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 11, NOVEMBER 2005 Fig. 5. SC fully differential schematic of the 2–1 cascade SC 61 M in this paper. architecture in Fig. 4 obtains the best results, except for . In this case, the lowest power consumption is obtained by a second-order M with , the third-order cascade being the second one in the ranking. However, the second-order architecture does not qualify for some values of . Also, it requires a four times faster clock than the cascade, thereby increasing the issues related to substrate noise coupling. B. SC Implementation Fig. 5 shows the fully differential SC schematic of the selected M architecture. Note that the SC branch connected to the input signal in the first integrator uses double sampling to achieve an extra gain of 2, without increasing circuit noise [21]. The other branch receives the digital-to-analog converter (DAC) outputs. Making use of the spare connection of this branch, an external DC signal can be applied during to center the sensor signal in the modulator full-scale range. This solution renders unnecessary a third branch for offset compensation; it can therefore be eliminated, and results in no further increase of thermal noise. The second stage of the modulator incorporates an integrator with only two input branches, although three different weights are implemented: , and (see Fig. 4). This can be done because the selection of weights in the designed modulator, considering that , allows the distribution of weight between the two integrator branches, namely and . The modulator operation is controlled by two nonoverlapped clock phases, namely sampling phase and integration phase . In order to attenuate the signal-dependent clock feedthrough, delayed versions of the two phases ( and ) are also provided. As illustrated in Fig. 5, this delay is incorporated only to the falling edges of the clock phases (i.e., to the turn-off of the switches), while the rising edges are DE LA ROSA et al.: THIRD-ORDER 2-1 CASCADE SIGMA-DELTA MODULATOR FOR LOW-POWER HIGH-LINEARITY AUTOMOTIVE SENSOR ASICs 2251 Fig. 6. Programmable capacitors in the first integrator. (a) Capacitor arrays. (b) C implementation. synchronized in order to increase the effective time-slot for the modulator operations [17]. The comparators are activated at the end of phase (using as a strobe signal) to avoid any possible interference due to the transient response of the integrators’outputs at the beginning of the sampling phase. In addition to the master clock phases, and , additional phases are required to control the chopper switches used in the first integrator to attenuate flicker noise. These chopper phases are controlled by a master clock with programmable frequency, as will be described in Section IV. The programmable gain ( and ) has been mapped onto switchable capacitor arrays, each of them formed by a variable number of unitary capacitors ( pF) as shown in Fig. 6. Such numbers are selected for minimum power dissipation, bearing in mind the circuit noise limitation and the maximum temperature target (175 C). In order to keep the amplifier dynamic requirements as relaxed as possible, we propose to switch all unitary capacitors instead of just those forming the sampling capacitors. This is based on the following. •For large gains is larger than . Hence, is amplified with respect to the unity-gain case as it multiplied by [see (5)]. •For low gains the situation is the contrary. Now is attenuated with respect to the unity-gain case, which allows us to decrease the capacitance values, mainly . This strategy also relaxes the required amplifier dynamics because its equivalent load capacitance will also be decreased. •In order to simultaneously handle the modulator gain4 and the first integrator feedback weight (always equal to 0.25), the value of all capacitances must be changed by re-arranging the number of unitary capacitors forming them. C. High-Level Sizing and Building-Block Specifications The modulator specifications have been mapped onto building-block specifications using statistical optimization for design parameter selection, and compiled equations (capturing nonideal building-block behavior) for evaluation. This process is fine-tuned by behavioral simulation using an updated version of ASIDES, an advanced behavioral simulator of SC Ms 4An extra signal gain of 2 is considered as a consequence of using double sampling in the first integrator. [22]. At this step, nonidealities are covered more accurately than when compiled equations are used. Also, worst cases for speed (the largest capacitor values) and for thermal noise (the highest temperature and the lowest capacitor values) are contemplated. The outcome of this sizing process is summarized in Table II, where OPA denotes the opamp used at the first integrator and OPB refers to the opamps used at the second- and third-inte- grator (see Fig. 5). The data in Table II show the specifications of the building blocks that define the starting point for the block sizing that will be described in Section IV. The system-level performance of the modulator has been verified considering the parameters in Table II. Fig. 7 shows the in-band output spectra for the different modulator gains, clocked at MHz and considering a 20-dBV, 5-kHz input sinewave. The in-band error5power is also depicted. The figure shows that the total in-band error is, despite the gain, larger than 100 dB below FS ( V), as required for the proposed application. The DR is boosted by the modulator gain, leading to an overall DR referred to FS (DRFS) larger than 118 dB. IV. DESIGN OF THE BUILDING BLOCKS A. Amplifiers The key features for the design of the amplifiers are their open-loop DC gain, dynamic requirements and output swing. Regarding the latter, the set of integrator weights used for the M in Fig. 5 allow us to relax the output swing requirements to being only slightly larger than the voltage reference (2 V in this case), which is feasible when operating with 3.3-V supply in differential mode. Table II shows that OPA is more demanding than OPB, the reason being that the contribution of the latter to the total in-band error power is attenuated by the gain of the front-end integrator in the signal band. Thus, to reduce power consumption, OPA and OPB are handled as different instances during the design purposes. For this goal, an improved version of the transistor-level sizing tool FRIDGE [22] was used to explore the potentials of a wide catalog of fully differential OTA topologies. A single-stage folded-cascode architecture, shown in Fig. 8, was selected as 5The in-band error power includes noise and distortion caused by circuit error mechanisms. 2252 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 11, NOVEMBER 2005 TABLE II HIGH-LEVEL SIZING OF THE PROGRAMMABLE-GAIN 2–1 61 M Fig. 7. In-band (20 kHz) simulated output spectra of the proposed 61 M (see Fig. 5) for different modulator gains. a convenient choice for both amplifiers. -channel input transistors were employed to take advantage of the twin-well technology feature in removing the body effect of nMOS transistors. The common-mode feedback (CMFB) net has been implemented using a SC circuit, which provides fast linear operation with small power dissipation. Table III shows the full sizing and biasing of OPA and OPB. Table IV summarizes the obtained electrical performance for both amplifiers using HSPICE, regarding the target values imposed during the optimization procedure with FRIDGE. The table depicts the parameter values corresponding to typical operation conditions (typical process parameters, nominal supply DE LA ROSA et al.: THIRD-ORDER 2-1 CASCADE SIGMA-DELTA MODULATOR FOR LOW-POWER HIGH-LINEARITY AUTOMOTIVE SENSOR ASICs 2253 Fig. 8. Fully differential folded-cascode amplifier used in the 61 modulator. TABLE III SIZING AND BIASING OF THE OPAMPS TABLE IV ELECTRICAL PERFORMANCE OF THE OPAMPS (HSPICE) voltage, and room temperature) as well as the worst case value for each parameter in a corner analysis—considering fast and slow device models, 10% variation in the 3.3-V supply, and temperatures in the range [ 40 C, 175 C]. The amplifier nonlinear features (mainly nonlinear DC gain and dynamics) deserve special attention in a high-linear implementation. When the amplifier output swings, the drain-to- source voltage of the output transistors changes, and so does the output impedance. This effect, illustrated in Fig. 9 for the OPA and OPB in the nominal conditions, induces a dependence of the open-loop DC gain on the output voltage; the DC gain reaches its maximum at the central point and decreases as the output approaches the rails. Such a nonlinearity is traditionally modeled by second-order polynomial dependence of the gain on the output voltage [7], but this is only valid for small voltage excursions around the central point. On the contrary, in the proposed 3.3-V implementation, it is expected that small-gain regions of the DC curve (around boundaries of shadowed areas in Fig. 9) are often visited during normal operation of the modulator. In order to accurately account for this nonlinearity during behavioral simulations, we have resorted to a table look-up procedure based on amplifier DC curves obtained by electrical simulation. A similar approach has been employed to validate the actual transient response of the front-end integrator. B. Comparators The specifications for the single-bit quantizers (comparators) at the end of the first and second stages of the modulator are given in Table II. In order to cope with the required resolution time (around 50 ns) and hysteresis (lower than 30 mV) a regenerative latch including a pre-amplifying stage was selected [23]. Fig. 10 shows the selected comparator topology. It consists of a nMOS differential input pair –, a CMOS regenerative latch circuit, and a RS flip-flop. The latch circuit is composed of a nMOS flip-flop –with a pair of nMOS switches –for strobing and a nMOS switch for resetting, and a pMOS flip-flop –with a pair of pMOS precharge switches –). The comparator is activated at the end of the integration phase. At the beginning of the next integration phase, the out- 2254 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 11, NOVEMBER 2005 Fig. 9. DC-gain nonlinearity for (a) OPA and (b) OPB. Fig. 10. Schematic of the comparator. (a) Preamplifier + latch. (b) RS flip-flop. puts of the latch are forced to the low state and the RS flip-flop maintains the comparator output until the next strobbing of the latch. As shown in Fig. 10, different voltage supplies have been used for the pre-amplifier and for the regenerative latch—and , respectively. This has been done in order to reduce the comparator sensitivity to injected digital switching noise and supply bounce effects. The circuit in Fig. 10 has been designed according to the required high-level specifications, while keeping the input capacitance and the power consumption as low as possible. Table V shows the sizes of the transistors and the value of the bias current. MonteCarlo simulations and corner analysis have been done to extract the comparator performance during sizing. Table VI summarizes its electrical performance, showing the worst cases for hysteresis, offset and resolution time together with the power dissipation. As expected, the resolution is dominated by mismatching, the offset being the dominant limitation factor with a worst case value of 9.92 mV, which is compliant with the specifications in Table II. C. Switches The main design issue related to the switches is the finite switch on-resistance, , which is mainly constricted by dy- TABLE V SIZING AND BIASING OF THE COMPARATORS namic considerations. Incomplete settling caused by transmission gates is traditionally reduced by making . In our circuit, values up to 650 (see Table II) can be tolerated with no degradation of the modulator performance. These values can be obtained using CMOS switches with aspect ratios of for the nMOS transistor and for the pMOS, operating with the nominal 3.3-V supply. DE LA ROSA et al.: THIRD-ORDER 2-1 CASCADE SIGMA-DELTA MODULATOR FOR LOW-POWER HIGH-LINEARITY AUTOMOTIVE SENSOR ASICs 2261 Fig. 20. In-band noise power as a function of the input signal amplitude. Fig. 21. (a) SNR and (b) SNDR as a function of the input amplitude for V =1 V. Fig. 22. SNR versus input amplitude for 10-kHz bandwidth: (a) V =1 V; (b) V =2 V. 2262 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 11, NOVEMBER 2005 Fig. 23. Comparison with state-of-the-art 61 Ms. TABLE VIII SUMMARY OF MEASURED PERFORMANCE DE LA ROSA et al.: THIRD-ORDER 2-1 CASCADE SIGMA-DELTA MODULATOR FOR LOW-POWER HIGH-LINEARITY AUTOMOTIVE SENSOR ASICs 2263 TABLE IX PERFORMANCE COMPARISON ( 61 Ms WITH FOM > 200 ) VI. CONCLUSION A 0.35- m CMOS programmable-gain cascade 2-1 M to be included in an automotive sensor interface has been described. The main design considerations have been discussed and applied to select the most appropriate modulator architecture in terms of resolution, speed, and power consumption. The design of the prototype is based on a top-down CAD methodology that combines simulation and statistical optimization at different levels of the modulator hierarchy. Experimental results show that the dynamic range can be highly enhanced by the action of gain programmability. This combined effect places the presented chip at the cutting edge of state-of- the-art Ms for similar applications, achieving the largest figure of merit reported up to now. ACKNOWLEDGMENT The authors would like to thank E. Laes, L. Vandervoorde, and R. Vanhooren of AMI Semiconductors for their constructive comments on the 0.35- m technology process. REFERENCES [1] W. J. Fleming, “Overview of automotive sensors,”IEEE Sensors J., pp. 296–308, Dec. 2001. [2] D. S. Eddy and D. R. Sparks, “Application of MEMS technology in automotive sensors and actuators,”Proc. IEEE, pp. 1747–1755, Aug. 1998. [3] J. E. Johnston, “A 24-bit delta-sigma ADC with an ultra-low noise chopper-stabilized programmable gain instrumentation amplifier,”in Proc. Conf. Advances A/D and D/A Conversion Techniques and Their Applications, 1999, pp. 27–28. [4] P. Malcovati and F. Maloberti, “An integrated microsystem for 3-D magnetic field measurements,”IEEE Trans. Instrum. Meas., vol. 49, no. 2, pp. 341–345, Apr. 2000. [5] C. B. Wang, “A 20-bit 25-kHz delta-sigma A/D converter utilizing a frequency-shaped chopper stabilization scheme,”IEEE J. Solid-State Circuits, vol. 36, no. 3, pp. 566–569, Mar. 2001. [6] S. R. Norsworthy, R. Schreier, and G. Temes, Delta-Sigma Data Converters—Theory, Design and Simulation. New York: IEEE Press, 1997. [7] F. Medeiro, B. Pérez-Verdú, and A. Rodríguez-Vázquez, Top-Down Design of High-Performance Sigma-Delta Modulators. Norwood, MA: Kluwer, 1999. [8] K. A. A. Makinwa and J. H. Huijsing, “A smart CMOS wind sensor,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2002, pp. 432–479. [9] H. Kulah, N. Yazdi, and K. Najafi,“A CMOS switched-capacitor interface circuit for an integrated accelerometer,”Proc. IEEE Midwest Symp. Circuits and Systems, pp. 244–247, Aug. 2002. [10] S. Rabii and B. A. Wooley, “A 1.8-V digital-audio sigma-delta modulator in 0.8-  m CMOS,”IEEE J. Solid-State Circuits, vol. 32, no. 6, pp. 783–796, Jun. 1997. [11] Y. Yang, A. Chokhawala, M. Alexander, J. Melanon, and D. Hester, “A 114-dB 68-mW chopper-stabilized stereo multibit audio ADC in 5.62 mm ,”IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2061–2068, Dec. 2003. [12] L. Yao, M. S. J. Steyaert, and W. Sansen, “A 1-V 140-  W 88-dB audio sigma-delta modulator in 90-nm CMOS,”IEEE J. Solid-State Circuits, vol. 39, no. 11, pp. 1809–1818, Nov. 2004. [13] A. L. Coban and P. E. Allen, “A 1.5 V 1.0 mW audio delta sigma modulator with 98 dB dynamic range,”in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 1999, pp. 50–51. [14] F. Medeiro, R. del Río, J. M. de la Rosa, B. Pérez-Verdú, and A. Rodríguez-Vázquez, “High-Order Cascade Multi-Bit 61 Modulators,”in CMOS Telecom Data Converters, A. Rodríguez-Vázquez, F. Medeiro, and E. Janssens, Eds. Boston, MA: Kluwer Academic, 2003, ch. 9. [15] I. Fujimori, L. Longo, A. Hairapetian, K. Seiyama, S. Kosic, J. Cao, and S. L. Chan, “A 90-dB SNR 2.5-MHz output-rate ADC using cascaded multibit delta-sigma modulation at 8 2 oversampling ratio,”IEEE J. Solid-State Circuits, vol. 35, no. 12, pp. 1820–1828, Dec. 2000. [16] R. del Río, J. M. de la Rosa, B. Pérez-Verdú, M. Delgado-Restituto, R. Domínguez-Castro, F. Medeiro, and A. Rodríguez-Vázquez, “Highly linear 2.5-V CMOS 61 modulator for ADSL+,”IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 1, pp. 47–62, Jan. 2004. [17] A. M. Marques, V. Peluso, M. S. J. Steyaert, and W. Sansen, “A 15-b resolution 2-MHz nyquist rate 16 ADC in a 1-  m CMOS technology,” IEEE J. Solid-State Circuits, vol. 33, no. 7, pp. 1065–1075, Jul. 1998. [18] G. Yin, “High-performance analog-to-digital converters using cascaded 61 modulators,”Ph.D. dissertation, Katholieke Universiteit Leuven, Belgium, 1994. [19] F. V. Fernández, R. del Río, R. Castro-López, O. Guerra, F. Medeiro, and B. Pérez-Verdú,“Design Methodologies for Sigma-Delta Converters,” in CMOS Telecom Data Converters, A. Rodríguez-Vázquez, F. Medeiro, and E. Janssens, Eds. Boston, MA: Kluwer Academic, 2003, ch. 15. [20] B. Razavi, Design of Analog CMOS Integrated Circuits. New York: McGraw-Hill, 2000. [21] C. C. Enz and G. C. Temes, “Circuit techniques for reducing the effects of op-amp imperfections: Autozeroing, correlated double sampling, and chopper stabilization,”Proc. IEEE, vol. 84, no. 11, pp. 1584–1614, Nov. 1996. [22] F. Medeiro, B. Pérez-Verdú, A. Rodríguez-Vázquez, and J. L. Huertas, “A vertically integrated tool for automated design of 61 modulators,” IEEE J. Solid-State Circuits, vol. 30, no. 7, pp. 762–772, Jul. 1995. [23] G. M. Yin, F. Op’t Eynde, and W. Sansen, “A high-speed CMOS comparator with 8-b resolution,”IEEE J. Solid-State Circuits, vol. 27, no. 2, pp. 208–211, Feb. 1992. [24] W. Yu, S. Sen, and B. H. Leung, “Distortion analysis of MOS track-and- hold sampling mixers using time-varying volterra series,”IEEE Trans. Circuits Syst. II, vol. 46, no. 2, pp. 101–113, Feb. 1999. [25] J.-T. Wu and K.-L. Chang, “MOS charge pumps for low-voltage operation,”IEEE J. Solid-State Circuits, vol. 33, no. 4, pp. 592–597, Apr. 1998. 2264 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 11, NOVEMBER 2005 [26] K. Lee and R. G. Meyer, “Low distortion switched-capacitor filter design techniques,”IEEE J. Solid-State Circuits, vol. SC-20, no. 12, pp. 1103–1113, Dec. 1985. [27] J. W. Fattaruso, M. De Wit, G. Warwar, K. S. Tan, and R. K. Hester, “The effect of dielectric relaxation on charge-redistribution A/D converters,” IEEE J. Solid-State Circuits, vol. 25, no. 12, pp. 1550–1561, Dec. 1990. [28] M. F. Snoeij, O. Bajdechi, and J. H. Huijsing, “A fourth-order switched-capacitor sigma-delta A/D converter using a high-ripple chebyshev loop filter,”in Proc. IEEE Int. Symp. Circuits and Systems, 2001, pp. 615–618. [29] O. Nys and R. K. Henderson, “A 19-bit low-power multibit sigma-delta ADC based on data weighted averaging,”IEEE J. Solid-State Circuits, vol. 32, no. 7, pp. 933–942, Jul. 1997. [30] D. A. Kerth, D. B. Kasha, T. G. Mellissinos, D. S. Piasecki, and E. J. Swanson, “A 120-dB linear switched-capacitor delta-sigma modulator,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 1994, pp. 196–197. [31] S. Yan and E. Sánchez-Sincenio, “A continuous-time 61 modulator with 88-dB dynamic range and 1.1-MHz signal bandwidth,”IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 75–86, Jan. 2004. JoséM. de la Rosa (S’96–M’01) received the Licenciado en Física Electrónica (Electronics Physics) degree in 1993 and the Doctor en Ciencias Físicas (Ph.D.) degree in 2000 from the University of Seville, Spain. Since 1994, he has been with the Institute of Microelectronics of Seville (IMSE-CNM, CSIC) of the Spanish Microelectronics Center. He is also with the Department of Electronics and Electromagnetism, School of Engineering, University of Seville, where he is an Associate Professor. His main research interests are in the field of mixed-signal integrated circuits, especially pipeline and sigma-delta analog-to-digital converters, including analysis, behavioral modeling and design automation of such circuits. He has participated in several National and European R&D projects and has co-authored more than 80 international scientific publications, including journal and conference papers, book chapters and the book Systematic Design of CMOS Switched-Current Bandpass Sigma-Delta Modulators for Digital Communication Chips (Springer, 2002). Sara Escalera received the B.S. degree in electronic physics and the M.S. degree in microelectronics from the University of Sevilla, Spain, in 2001 and 2004, respectively. She is currently working toward her Ph.D. degree at the Instituto de Microelectrónica de Sevilla (IMSE-CNM) in the field of sigma-delta analog-to- digital converters testing. Her main areas of interest are test and design of mixed-signal circuits, especially of high-accuracy SC sigma-delta converters. BelénPérez-Verdúhas been an Associate Professor at the University of Seville, Spain, since 1987. She is also with the Institute de Microelectronics of Seville (IMSE-CNM). Her research activities are in the field of mixed-signal integrated circuit design, in particular, sigma-delta modulators, computer-aided design and modeling of analog integrated circuits. She has published two books and more than 70 papers including journal and conference papers. She has participated in several European ESPRIT projects and Spanish CICYT projects. Fernando Medeiro (M’99) was born in Higuera de Vargas, Badajoz, Spain. He received the Licenciado en Física Electrónica degree in 1990 and the Doctor en Física (Ph.D.) degree with honors in 1997, both from the University of Seville, Spain, in 1990 and 1997, respectively. Since 1991, he has been working at the Microelectronics Institute of Seville (IMSE, C.S.I.C.). He is also with the Department of Electronics and Electromagnetism at the Escuela Superior de Ingenieros of the University of Seville, where he is an Associate Professor. His research interest are in the field of sigma-delta converters, including modeling, behavioral simulation and design automation. In this topic, he has participated as a Lecturer in several international courses and has co-au- thored the book Top-Down Design of High-Performance Sigma-Delta Modulators (Springer, 1998). Oscar Guerra received the physics degree in electronics and the Ph.D. degree in the field of analog design automation, from the University of Seville, Spain, in 1995 and 2002, respectively. Since 1997, he has been with the Instituto Nacional de Microelectrónica, Centro Nacional de Microelectrónica (IMSE-CNM), and since 2000, he has also been an Assistant Professor at the University of Seville. His research interests are in the fields of modeling techniques for analog integrated circuit design, with special enphasis on symbolic analysis techniques and design and design-for-testability of high-resolution sigma-delta converters. His work has been developed in the context of eight research projects, ranging from the developement of CAD tools to analog circuit design and built-in self-test techniques. He has been an author or co-author of more than 40 papers in international journals and international proceedings, as well as one chapter in the book CMOS Telecom Data Converters (Kluwer, 2003). Rocío del Río(M’04) received the Licenciado en Fisíca Electrónica and the Ph.D. degree from the University of Seville, Spain, in 1996 and 2004, respectively. She joined the Department of Electronics and Electromagnetism at the University of Seville in 1995, where she is currently an Assistant Professor. Since 1995, she has also been with the Institute of Microelectronics of Seville (IMSE-CNM, CSIC). Her main research interests are in ADCs, especially sigma-delta converters, including modeling, behavioral simulation, and design automation. Angel Rodríguez-Vázquez (M’80–F’96) was born in Seville, Spain. He is a Professor of Electronics at the Department of Electronics and Electromagnetism, University of Seville. He is also a member of the research staff of the Institute of Microelectronics of Seville-Centro Nacional de Microelectrónica (IMSE-CNM), where he is heading a research group on Analog and Mixed-Signal VLSI. His research interests are in the design of analog interfaces for mixed-signal VLSI circuits, CMOS imagers and vision chips, neuro-fuzzy controllers, symbolic analysis of analog integrated circuits and optimization of analog integrated circuits. Dr. Rodríguez-Vázquez served as an Associate Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I, FUNDAMENTAL THEORY AND APPLICATIONS (TCAS-I) from 1993 to 1995, as Guest Editor of the IEEE TCAS-I special issue on Low-Voltage and Low-Power Analog and Mixed-Signal Circuits and Systems (1995), as Guest Editor of the IEEE TCAS-II special issue on “Advances in Nonlinear Electronic Circuits”(1999), and as chair of the IEEE CAS Analog Signal Processing Committee (1996). He was co-recipient of the 1995 Guillemin–Cauer award of the IEEE Circuits and Systems Society, and the best paper award of the 1995 European Conference on Circuit Theory and Design. In 1992, he received the Young Scientist Award of the Seville Academy of Science. In 1996, he was elected to the degree of Fellow of the IEEE for “contributions to the design and applications of analog/digital nonlinear ICs”.