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1 V CMOS subthreshold log domain PDM

Serra Graells, Francesc; Huertas Díaz, José Luis

Abstract

A new CMOS circuit strategy for very low-voltage Pulse-Duration Modulators (PDM) is proposed. Optimization of voltage supply scaling below the sum of threshold voltages is based on Instantaneous Log Companding processing through the MOSFET operating in weak inversion. A 1 V VLSI PDM circuit for very low-voltage audio applications such as Hearing Aids is presented, showing good agreement between simulated and experimental data.

Full text

1V CMOS Sub h eshold Log-Domain Pulse Du a ion Modula o s F ancisco Se a-G aells ([email p o ec ed]) Cen o Nacional de Mic oelec ´onica, Ins i u de Mic oelec `onica de Ba celona Jos´e Luis Hue as ([email p o ec ed]) Cen o Nacional de Mic oelec ´onica, Ins i u o de Mic oelec ´onica de Se illa Abs ac . A new CMOS ci cui s a egy o e y low- ol age Pulse-Du a ion Modula o s (PDM) is p oposed. Op imiza ion o ol age supply scaling below he sum o h eshold ol ages is based on Ins an aneous Log Companding p ocessing h ough he MOSFET ope a ing in weak in e sion. A 1V VLSI PDM ci cui o e y low- ol age audio applica ions such as Hea ing Aids is p esen ed, showing good ag eemen be ween simula ed and expe imen al da a. Keywo ds: Low-Vol age, CMOS, Sub h eshold, Log, PDM 1. In oduc ion Pulse-Du a ion Modula ion (PDM) p ocessing is o special in e es in ou pu powe s ages o Class-D d i ing o low-impedance loads. Pa icula ly, po able low-powe VLSI sys em-on-a-chip applica ions like Hea ing Aids equi e his ype o signal modula ion in o de o ex end ba e y li e. Un o una ely, mos exis ing CMOS solu ions do no allow good-enough low- ol age compa ibili y o eal single ba e y cell ope a ion (down o 1.1V) [1, 2, 3], equi ing supply mul iplie s which end o dec ease powe e iciency, and inc ease bo h ex e nal componen s and Si a ea o e head as well. O he epo ed p oposals make ex ensi e usage o esis o s o bipola de ices [4, 5]. A no el e y low- ol age CMOS ci cui s a egy o PDM is p esen ed he e in he ame o he gene al Ins an aneous Companding heo y[6, 7, 8, 9]. The p oposed implemen a ion is based on he MOS ansis o ope a ing in he weak in e sion egion o op imize bo h he ol age supply scaling and he cu en consump ion. 2. P inciple o Ope a ion In gene al, a PDM signal (you ) can be ob ained om a 1-bi compa i- son be ween he base-band inpu (yin) and a highe equency iangle c °2002 Kluwe Academic Publishe s. P in ed in he Ne he lands. alog990.02. e ised. ex; 6/06/2002; 11:22; p.2 (c) 2003 Kluwe Academic Publishe s h p://dx.doi.o g/10.1023/A:1022545414777 1V CMOS Sub h eshold Log Domain Pulse Du a ion Modula o s 3 wa e o m (y i) as depic ed in Figu e 1. The signal y i may be gene - a ed by in eg a ing a cons an e e ence (ycons ), which is pe iodically in e ed acco ding o an ou pu window (y hmin,y hmax). (Place o Figu e 1) Due o he e y low- ol age capabili ies wan ed o he ci cui , a Log Companding app oach is selec ed he e o comp ess he in e nal ol age dynamic ange. A his poin , he MOS ansis o ope a ing in sub h eshold egion is p oposed as he main basic building block o implemen such ype o signal p ocessing. In pa icula , he Ga e- D i en (GD) law om he gene al s udy p esen ed by hese au ho s in [10] will be used he e as he companding unc ion (F): I=F(V) = ISe− VT O+nVbias nU eV nU IS= 2nβU2 (1) whe e he Th eshold Vol age (VT O), Cu en Fac o (β), Sub h esh- old Slope (n) and Speci ic Cu en (IS) a e de ined acco ding o he EKV de ice model [11]. Now, he ex e nally linea desc ip ion in he y-domain (i.e. cu en I) o Figu e 1 mus be ansla ed in o he com- p essed in e nal signal (i.e. ol age V). Since compa a o s a e easily implemen ed in cu en mode, e o s a e ocused on he syn hesis in he comp essed V-domain o he ollowing in eg a o equa ion: dI i d =±Icons τI hmin < I i < I hmax (2) whe e τs ands o a gene ic Time Cons an . A e applying he Companding unc ion F om (1), he abo e s a e-space equa ion is ansla ed o: dV i d =±nU τe Vcons −V i nU (3) In case o s o ing he comp essed signal V i ac oss a g ounded lin- ea capaci o (C), exp ession (3) can be unde s ood as a non-linea ansconduc ance d i ing C: CdV i d | {z } Icap =±I une Vcons −V i nU I un . =nU C τ(4) whe e I un s ands o he uning cu en , which con ols he pe iod o he iangula oscilla o (T i) acco ding o: T i = 2nU C I un µI hmax −I hmin Icons ¶(5) alog990.02. e ised. ex; 6/06/2002; 11:22; p.3 4F.Se a-G aells and J.L.Hue as 3. Low-Vol age CMOS Implemen a ion The in eg a o equa ion in (4) can be implemen ed h ough he basic building blocks de eloped by hese au ho s in [10], which a e a gene al- iza ion o [12]. Howe e , in ou pa icula case o cons an inpu (Icons ), a mo e compac ealiza ion is p oposed in Figu e 2, whe e all ma ked MOS pai s a e assumed o ope a e in weak in e sion sa u a ion. (Place o Figu e 2) The iangle gene a o is displayed a he uppe pa o he igu e and buil h ough ansis o s M1 o M18. This oscilla o consis s o : he inpu comp esso M1 gene a ing he comp essed cons an inpu Vcons , he non-linea ansconduc ance pai M4-M5 d i ing he in eg a o capaci o C, and he ou pu expande M2 ha gene a es he iangle wa e o m I i. In o de o ob ain he desi ed I i, he expande equi es he same e e ence le el V e o he comp esso (i.e. same sou ce ol - ages be ween M1 and M2). Such low-impedance ol age copy is supplied by M3 and M12. T ansis o M11 is used o ensu e p ope ope a ion o g ounded de ices M12 and M13. Oscilla ion is o ced by he eedback window compa a o M15-M16, which al e na i ely changes he sign o he slope s o ed in a D- ype lip- lop (DFF). A sa e s a up signal (Vs a ) should be equi ed a he lip- lop o a p ope ini ializa ion. Such memo y elemen se s he cha ge and discha ge phases o he capaci o Cby swi ching he mi o M9-M10, so Icap =±ID4. The esul ing Log comp essed and expanded iangle wa e o m can be seen in Figu e 3. (Place o Figu e 3) An ope a ional ans esis ance ampli ie , made o de ices M19 o M24 in he lowe pa o Figu e 2, is also included o ensu e low-enough inpu impedance. Such ea u e is o special in e es in case o equi ing an addi ional V/Icon e sion o he incoming signal, which can be pe - o med wi h jus a simple se ies esis o (and e en ually a decoupling capaci o ) as indica ed in he same igu e in dashed lines. The ou pu PDM signal (VP DM ) is compu ed om he 1-bi ol age quan iza ion o (I i −Iin). A p ope quiescen bias Ibias = (I hmax +I hmin)/2 mus be designed o ob ain a 50% PDM ou pu in silence. Also, a ypical s uc u e o audio applica ions is depic ed in Figu e 2, whe e a digi al bu e s age is ed by he VP DM signal o ope a e he ou pu ecei e in Class D. alog990.02. e ised. ex; 6/06/2002; 11:22; p.4 1V CMOS Sub h eshold Log Domain Pulse Du a ion Modula o s 5 4. Design Example Based on he ci cui s a egy p oposed in p e ious sec ion, a 100KHz Class-D ou pu s age o 1.1V VLSI Hea ing-Aids-on-a-chip has been implemen ed. In his case, a single slope (i.e. saw oo h) oscilla o has been buil wi h design pa ame e s Ibias = 1µA, I un = 100nA, C= 5pF and I h = 4µA. The comple e PDM ci cui has been in eg a ed in a 1.2µm VLSI CMOS double-me al double-polySi p ocess as depic ed in Figu e 4, whe e de ice a ea is abou 0.10mm2wi hou conside - ing digi al powe bu e s. Bo h BSIM3 simula ed and expe imen al pe o mances a e epo ed in Table I unde ac ual ba e y supply op- e a ion (1.1V o 1.5V). All boxed de ices in Figu e 2 we e sized a 10 ×40µm 3µm o ensu e weak in e sion ope a ion o he wan ed ange o cu en s. On he o he hand, he emaining MOS ansis o s we e designed wi h aspec a ios as long as allowed by he supply ol age o imp o e D ain-cu en ma ching be ween de ices, so ou pu o se s. In his sense, bo h Mon eca lo simula ions and expe imen al da a e u n du y-cycle de ia ions (2σ) o less han 1%. Due o he a ge applica ion in he ield o Hea ing Aids (i.e. low empe a u e- ange, low- ol age supplies and ecei e s impedances >50Ω), he esul ing s a ic-powe consump ion is qui e accep able (i.e. <100µA). In case o equi ing na owe du y-cycle de ia ions, some eedback can be applied om he ou pu bu e s o he inpu o he p oposed modula o in o de o p o ide a sel -biasing mechanism, like [13]. Finally, an elec ical PDM s imulus sample and he co esponding acous ic ou pu a he ecei e a e displayed in Figu e 5. The ha monic dis o ion measu ed is qui e sa is ac o y o in eg a ed audio applica ions. (Place o Figu e 4) (Place o Table I) (Place o Figu e 5) 5. Conclusions The new CMOS design s a egy p oposed o implemen PDM modu- la o s allows s ong ol age supply scaling-down below VT ON +|VT OP |. A compac ci cui s uc u e has been epo ed wo king a e y low alog990.02. e ised. ex; 6/06/2002; 11:22; p.5 6F.Se a-G aells and J.L.Hue as cu en . The ci cui was ully in eg a ed in s anda d CMOS echnology and i s expe imen al da a was ound in good ag eemen wi h simula- ion. As a esul , his modula o is sui able o e y low- ol age VLSI audio applica ions like Hea ing-Aids-on-a-chip (1.1V o 1.5V). Acknowledgemen s Resea ch pa ially suppo ed by Spanish CICYT-TIC97-1159, CICYT- TIC99-1084 and Eu opean ESPRIT-FUSE-23068 p ojec s. Re e ences [1] K.Philips, J. an den Hombe g, and C.Dijkmans: 1999, ‘Powe DAC: A Single- Chip Audio DAC wi h a 70%-E icien Powe S age in 0.5µm CMOS’. In: P oceedings o he In e na ional Solid-S a e Ci cui s Con e ence. pp. 154–155. [2] M.T.Tan, J.S.Chang, Z.H.Cheng, and Y.C.Tong: 1998, ‘A No el Sel -E o Co ec ion Pulse Wid h Modula o o a Class D Ampli ie o Hea ing In- s umen s’. In: P oceedings o he In e na ional Symposium on Ci cui s and Sys ems, Vol. I. pp. 261–264. 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[13] J.S.Chang, B.H.Gwee, Y.S.Long, and M.T.Tan: 2001, ‘A No el Low-Powe Low-Vol age Class D Ampli ie wi h Feedback o Imp o ing THD, Powe E - iciency and Gain Linea i y’. In: P oceedings o he In e na ional Symposium on Ci cui s and Sys ems, Vol. I. pp. 635–638. alog990.02. e ised. ex; 6/06/2002; 11:22; p.7 8F.Se a-G aells and J.L.Hue as Lis o Tables I Typical esul s o he modula o a oom empe a u e. 9 alog990.02. e ised. ex; 6/06/2002; 11:22; p.8 1V CMOS Sub h eshold Log Domain Pulse Du a ion Modula o s 9 Table I. Typical esul s o he modula o a oom empe a u e. Pa ame e Simula ed Expe imen al Uni s Min. Supply Vol age 1.1 1.1 V Max. VT ON +|VT OP |1.3 1.2 V Powe Consump ion 45 <50 µW PDM Fac o 2.6 2.7 µs/µA Inpu Full Scale 4 3.9 µApp Dynamic Range >70 >63 dB THD @90% Full Scale <2.8 <3 % Pulse F equency 102 104 KHz Du y-cycle De ia ions (2σ)<1<1 % alog990.02. e ised. ex; 6/06/2002; 11:22; p.9 10 F.Se a-G aells and J.L.Hue as Lis o Figu es 1 Gene al design app oach o PDM gene a ion. 11 2 Simpli ied schema ic o he PDM modula o . 12 3 Simula ed ol age ac oss in eg a o capaci o (uppe ) and ou pu cu en (lowe ) ope a ing a 1.0V supply. 13 4 Mic oscope pho og aph o he PDM modula o . 14 5 Expe imen al di e en ial PDM and acous ic audio signal a ecei e o Iin=2µApp@4KHz. 15 alog990.02. e ised. ex; 6/06/2002; 11:22; p.10 1V CMOS Sub h eshold Log Domain Pulse Du a ion Modula o s 17 Add ess o O p in s: D .F ancisco Se a-G aells mail o:[email p o ec ed] h p://www.cnm.es/~pse a Tel: +34 93 594 77 00 Fax: +34 93 580 14 96 Cen o Nacional de Mic oelec ´onica Ins i u de Mic oelec `onica de Ba celona Campus UAB 08193 Bella e a Spain alog990.02. e ised. ex; 6/06/2002; 11:22; p.17 alog990.02. e ised. ex; 6/06/2002; 11:22; p.18