Trivium hardware implementations for power reduction

T i ium ha dwa e implemen a ions o powe educ ion J. M. Mo a-Gu ié ez* ,† , C.J. Jiménez-Fe nández and M. Valencia-Ba e o Ins i u e o Mic oelec onics o Se ille (IMSE-CNM), CSIC–Uni e si y o Se ille, Se ille, Spain SUMMARY This pape desc ibes he use o pa alleliza ion echniques o educe dynamic powe consump ion in ha d- wa e implemen a ions o he T i ium s eam ciphe . T i ium is a synch onous s eam ciphe based on a combina ion o h ee non-linea eedback shi egis e s. In 2008, i was chosen as a finalis o he ha dwa e p ofile o he eSTREAM p ojec . So ha hei powe consump ion alues can be compa ed and e ified, he p oposed low-powe T i ium designs we e implemen ed and cha ac e ized in 350-nm s anda d-cell echnol- ogy wi h bo h ansis o s and ga e-le el models, in o de o pe mi bo h elec ical and logical simula ions. The esul s show ha he wo designs dec eased a e age powe consump ion by be ween 15% and 25% wi h i ually no pe o mance loss and only a sligh o e head (abou 5%) in a ea. KEY WORDS: T i ium; s eam ciphe ; low powe ; ligh weigh c yp og aphy; ha dwa e implemen a ion 1. INTRODUCTION In he coming yea s, mos communica ions sys ems in low-complexi y de ices wi h applica ions in po able heal h ca e o he In e ne o hings will use c yp og aphic echniques o ensu e in iolabili y and confiden iali y in da a managemen . Ha dwa e implemen a ion in applica ion-specific in eg a ed ci cui (ASIC) de ices will equi e no only c yp og aphic algo i hms bu also algo i hms o ligh weigh c yp og aphy [1]. And in ha dwa e implemen a ions, he impo an measu emen s o e alua ing ligh weigh p ope ies a e chip size and powe consump ion [2, 3]. Ciphe s used in his ype o c yp og aphy include block ciphe s and s eam ciphe s [4]. This a icle ocuses on he la e . S eam ciphe s a e gene ally much as e han block ciphe s, and hey use less ha dwa e esou ces, making hem an ideal al e na i e when high h oughpu , low ga e coun s, and low powe consump ion a e p io i y equi emen s. The ini ia i e known as eSTREAM [5] iden ified and published h ee new algo i hms specially designed o ensu e good pe o mance in ha dwa e (G ain, Mickey, and T i ium). These s eam ciphe s a e al eady being used in embedded sys ems [1], wi eless communica ions [6], and ba e y-powe ed and passi ely powe ed de ices [7], whe e i is c i ical o ha e an algo i hm ha minimizes powe consump ion. The objec i e o his wo k is o p opose low-powe ASIC implemen a ions o T i ium based on s anda d-cell lib a ies in complemen a y me al–oxide–semiconduc o (CMOS) p ocess echnology. Analysis o he T i ium algo i hm sugges s ha pa alleliza ion is he mos app op ia e echnique o achie e a educ ion in powe consump ion [8]. The pa alleliza ion echnique was in oduced by Schneide , Von Kaenen, and Pique in 1995 [9]. In li e a u e, ew con ibu ions abou analyzing and educing T i ium powe consump ion ha e been published. In field-p og ammable ga e a ay implemen a ions, some summa ies o powe esul s o eSTREAM candida es including T i ium we e epo ed in [10, 11], bu no echniques specifically aimed a educing i s powe consump ion we e applied. In ASIC implemen a ion, powe esul s o a T i ium in a 130-nm CMOS echnology we e desc ibed in [12, 13] whe e 227 and 175μWo a e age powe we e ob ained a 10MHz. Ano he se o powe esul s o a T i ium in 130 and 350nm was shown in [14], whe e 337 and 641μW we e ob ained a 5MHz. In [15], powe consump ion in a adix-16 T i ium op imized o passi ely powe ed de ices was educed by applying clock ga ing [16] and sleep mode logic as a means o educing he e ec i e clock equency. Twen y- wo clock cycles we e needed o gene a e a 16-bi key s eam, and sou ce cu en alues below 1μA a 100KHz and 1.5V we e ob ained in 350-nm echnology. This pape ocuses on T i ium ha dwa e implemen a ions o low-powe applica ions, desc ibing wo di e en pa alleliza ion al e na i es. The fi s al e na i e was he mixed-pa allel low-powe (MPLP) T i ium implemen a ion, whe e pa alleliza ion was applied o flip-flops una ec ed by non- linea eedback pa hs. The second was he ull-pa allel low-powe (FPLP) implemen a ion, whe e he pa alleliza ion echnique was applied o all he flip-flops in he T i ium s eam ciphe , e en hough his mean edesigning non-linea eedback pa hs. This al e na i e was applied in an ea lie s udy [17] in which good esul s we e ob ained o a T i ium e en hough only esul s om logical simula ions we e p esen ed. Tha low-powe implemen a ion o T i ium was imp o ed and upda ed o he FPLP e sion. The applied echnique educes he in e nal flip-flop swi ching ac i i y ac o while main aining he same ex e nal equency, hus ela ing powe educ ion o he swi ching ac i i ies in he T i ium flip- flops. In his wo k, we compa ed logical esul s wi h elec ical simula ions in a s anda d-cell CMOS echnology ha included ansis o models o e alua ing and compa ing he accu acy o he powe measu emen s. Ou s udy also p esen s ano he low-powe (MPLP) implemen a ion al e na i e, which p oduced good esul s despi e being less complex. To compa e he benefi s o each o he p oposed solu ions, quan i a i e measu emen s o powe consump ion we e made in he di e en designs. Fo his pu pose, a de ailed powe consump ion s udy was ca ied ou a logic and elec ical le els in a 350-nm echnology ha inco po a ed bo h ansis o s and ga e-le el models in o de o pe mi bo h elec ical and logical simula ions. The esul s show ha his echnique makes i possible o educe dynamic powe and a e age cu en by be ween 30% and 58%, wi h no pe o mance loss and only a sligh penal y in a ea (less han 5%). The pape is o ganized as ollows. Sec ion 2 b iefly desc ibes he T i ium algo i hm and i s ha dwa e implemen a ion. Sec ion 3 p esen s he a chi ec u e o an MPLP T i ium implemen a ion wi h a non- ull-pa allel shi egis e , along wi h he co esponding powe educ ion esul s. Sec ion 4 desc ibes an al e na i e a chi ec u e o an FPLP T i ium implemen a ion. Sec ion 5 highligh s he main di e ences be ween he MPLP and FPLP implemen a ions, and, finally, some conclusions a e p esen ed in Sec ion 6. 2. TRIVIUM HARDWARE IMPLEMENTATION The ha dwa e implemen a ion o he T i ium [18] s eam ciphe is based on a 288-bi cyclic shi egis e (s a e egis e ), wi h combina ional logic o p o ide i s non-linea eedback. I gene a es up o 2 64 bi s o pseudo andom key s eam wi h an 80-bi sec e key and an 80-bi ini ializa ion ec o (IV). As can be seen in Figu e 1, he T i ium algo i hm implemen a ion, which gene a es one key s eam bi in each clock cycle, comp ises h ee shi egis e s o di e en leng hs and combina ional logic o he exclusi e-o sum and he AND ope a ions. The leng hs o he shi egis e s a e no he same; he fi s egis e has 93 bi s, he second has 83, and he hi d has 111. The s a e egis e is loaded wi h a sec e key, an IV, and some ones and ze os o ini ialize he s a e o he T i ium. Once loaded, he s a e egis e mus be shi ed 1152 imes (4 ×288) be o e a alid key s eam can be ob ained. The ou pu key s eam is an exclusi e-o ope a ion o signals om he h ee shi egis e s. Wi h his a chi ec u e and ope a ion mode, mos o he powe is consumed by he flip-flops o he h ee shi egis e s. To educe powe consump ion, we he e o e ocused on he shi egis e s uc u e. Dynamic powe depends on he swi ching ac i i y ac o (which ep esen s he a e age ac ion o clock cycles in which a signal ansi ion occu s), clock equency, supply ol age, and ou pu capaci ance. The mo e he logic ansi ions in he ou pu , he g ea e he inc ease in swi ching powe . In ou p oposal, dynamic powe in he T i ium shi egis e s is educed by dec easing he swi ching ac i i y. This is ca ied ou by applying he shi egis e pa alleliza ion echnique, while main aining he same equency and supply ol age. To accu a ely es ima e powe consump ion in he T i ium s eam ciphe , elec ical and logical simula ions we e ca ied ou in he di e en designs wi h he layou da a. The pos -layou ne lis con ained he clock bu e in he clock ees and he co e cells, so he powe consump ion was he summa ion o he logic ga es and he clock bu e s. The inpu /ou pu cells we e no included. Elec ical-simula ion-based analysis makes i possible o calcula e powe mo e accu a ely and in mo e de ail han using logical simula ion, al hough i also has he huge disad an age o being ex emely ime-consuming. A 350-nm CMOS p ocess echnology was chosen because i has logic and ansis o -le el models capable o pe o ming logical and elec ical simula ions. 3. MIXED-PARALLEL LOW-POWER TRIVIUM The pa alleliza ion echnique canno be applied di ec ly o all he flip-flops in he T i ium s a e egis e because he ou pu s o some o hem a e in ol ed in logical ope a ions. In his e sion, he echnique was applied only o he less significan bi s o each shi egis e no used in he eedback. The bi s in ques ion a e bi s 0 o 63 in he fi s shi egis e , bi s 93 o 160 in he second shi egis e , and bi s 177 o 240 in he hi d shi egis e (196 ou o 288 bi s in he s a e egis e ). The applica ion o he pa alleliza ion echnique equi ed a sligh ha dwa e modifica ion in each shi egis e o he ep esen a ion shown in Figu e 1. As can be seen in Figu e 2, he bi s o he shi egis e s no in ol ed in eedback o combina ional ope a ions we e di ided in o wo shi egis e s Figu e 1. T i ium s eam ciphe schema ic. denomina ed he odd and e en shi egis e s, espec i ely. This modifica ion made i necessa y o in oduce a flip-flop o gene a e a hal - equency clock. A mul iplexe was also needed, o selec he leas significan bi in each shi egis e . The MPLP implemen a ion is shown in Figu e 3. The s a e egis e was loaded in pa allel wi h a sec e key and an ini ializa ion ec o , he e en egis e s being loaded wi h he ising edge and he odd egis e s wi h he alling edge o an in e nal clock wi h hal he equency o he inpu clock. The MPLP and s anda d T i ium implemen a ions we e desc ibed in VHDL, syn hesized wi h Design Vision (Synopsys), and e ified using he ModelSim simula ion en i onmen , wi h he same es ec o s and using he same key and ini ializa ion ec o as hose p esen ed in he T i ium e e ence files [5]. Simula ions we e also pe o med wi h di e en se s o keys and ini ializa ion ec o s. The layou was implemen ed using he Encoun e Digi al RTL- o-GDSII Implemen a ion Sys em (Cadence). As p e iously men ioned, dynamic powe depends on he swi ching ac i i y ac o , which in u n ep esen s he a e age ac ion o clock cycles in which signal ansi ion occu s. To es ima e he e ec s o he pa alleliza ion echnique on swi ching ac i i y in he T i ium implemen a ion, RTL simula ions we e pe o med o compa e he numbe o ansi ions aking place in he s a e egis e flip-flops in each clock cycle. The a e age (a g) and maximum (max) numbe s o flip-flops ha changed in a clock cycle (0 o 1 and 1 o 0) a e shown in Table I. The a e age numbe o flip-flops swi ching hei alues in each clock cycle was 138 o he s anda d T i ium and 94 o he MPLP T i ium. The pa alleliza ion echnique he e o e educes he numbe o flip-flop swi ching in each clock cycle by app oxima ely 30%. This educ ion was also seen in he Figu e 2. Shi egis e pa alleliza ion schema ic. Figu e 3. Mixed-pa allel low-powe T i ium schema ic. a e age numbe o ansi ions om le els 0 o 1 and 1 o 0. These esul s, combined wi h he ac ha mos powe consump ion occu s in he s a e egis e ’sflip-flops, sugges ha a powe educ ion o abou 30% is possible, al hough his needs o be co obo a ed by logical and elec ical simula ions. The a ea epo p o ided by he Design Vision syn hesis ool o he MPLP and s anda d T i ium implemen a ions is shown in Table II. The a ea o he MPLP e sion o T i ium implemen ed in a 350-nm echnology is qui e simila o he a ea o he s anda d e sion, because he numbe s o flip- flops do no change (only one flip-flop is added, o he clock di ision) and he combina ional a ea only has o accommoda e h ee addi ional mul iplexe s. The conclusion is ha he MPLP e sion has no a ea penal y in compa ison wi h he s anda d e sion. 3.1. Mixed-pa allel low powe T i ium powe consump ion To analyze powe consump ion mo e accu a ely and ob ain a be e idea o why i dec eases, we measu ed cu en d awn om he powe supply in pos -layou elec ical simula ions. Elec ical simula ions we e ca ied ou wi h a clock equency o 25MHz, bu because o he complexi y o he ci cui and he compu ing ime, i was no possible o simula e a high numbe o clock cycles. Figu e 4 shows he wa e o m de ail o he cu en supply o bo h implemen a ions when simula ing o 1μs. No e ha he powe supply cu en peaks in he s anda d e sion o T i ium we e e y simila on bo h clock edges, whe eas he MPLP T i ium showed a educ ion in cu en peaks on he ising and alling edges o he clock, wi h peaks in he alling edges alling pa icula ly sha ply. Measu emen s om he elec ical simula ions show ha he peak cu en o he MPLP T i ium was educed by abou 20% on he ising clock edge and by abou 69% on he alling edge. Fu he mo e, a e age cu en consump ion as measu ed by elec ical simula ion Table I. Swi ching egis e s pe clock cycle in T i ium and MPLP T i ium. Swi ching egis e Swi ching 0 o 1 Swi ching 1 o 0 A e age Maximum A e age Maximum A e age Maximum T i ium 138 158 69 80 69 78 MPLP T i ium 94 117 47 58 47 59 MPLP, mixed pa allel low powe . Table II. Synopsys cell a ea epo o T i ium and MPLP T i ium. Synopsys epo 350nm T i ium MPLP T i ium Reduc ion Cell a ea 126 580 μm 2 129 165 μm 2 2% MPLP, mixed pa allel low powe . Figu e 4. Powe supply cu en pos -layou elec ical simula ion. MPLP, mixed pa allel low powe . dec eased by abou 25%, o he MPLP T i ium compa ed wi h he s anda d e sion. This is shown in Table III. The educ ion in powe consump ion shown in hese esul s was sligh ly less han expec ed because o he educed numbe o ansi ions in he flip-flops, shown in Table I. This is because clock ee powe consump ion is no conside ed in he able. Dynamic powe consump ion was measu ed om logical simula ions and compa ed wi h he elec ical simula ions. Logical simula ions we e ca ied ou o mo e clock cycles because hey a e less ime-consuming, al hough hei esul s a e less accu a e han hose o elec ical simula ions. Inpu pa e ns we e he same in bo h simula ions. The IV and key used we e hose p esen ed in he T i ium e e ence files [5]. Powe consump ion was analyzed using Encoun e Digi al Implemen a ion Sys em RTL o GDSII ools wi h a swi ching ac i i y file in a alue change dump o ma . This file was gene a ed wi h 1700 clock cycles (68-μs simula ion) and a clock equency o 25MHz. As men ioned ea lie , T i ium needs 1152 clock cycles o ob ain a alid key s eam. Capaci ances and powe models o wi es and ga es we e aken om he echnology lib a y. When he powe consump ion o he MPLP implemen a ion was compa ed wi h ha o he s anda d T i ium implemen a ion, i was ound ha he dynamic powe consump ion o he MPLP e sion was abou 25% lowe han ha o he s anda d e sion (Table IV). Again, he main eason o his educ ion was he lowe numbe o flip-flops changing in each clock cycle, as shown p e iously in Table I. This esul is e y simila o he measu emen s aken du ing he elec ical simula ion. The pa alleliza ion o 196 o he 288 bi s in he s a e egis e p oduced a powe educ ion o abou 25% in he MPLP T i ium. I he pa alleliza ion echnique could be applied o all 288 bi s o he s a e egis e , an e en g ea e educ ion in consump ion could be ob ained. Howe e , o do his, i was necessa y o in oduce some ha dwa e modifica ions. A new, low-powe , e sion inco po a ing such modifica ions is he e o e p esen ed in he ollowing sec ion. 4. FULL-PARALLEL LOW-POWER TRIVIUM In he FPLP implemen a ion, he pa alleliza ion echnique was applied o all he flip-flops in he shi egis e s. This, howe e , equi ed addi ional modifica ions in he s uc u e o he T i ium, as discussed in [17]. Shi egis e pa alleliza ion o all he bi s in he s a e egis e ans o ms each o he T i ium’s shi egis e s in o wo hal -leng h shi egis e s (odd and e en). Figu e 5 shows a schema ic ep esen a ion o he FPLP T i ium. The leng h o each shi egis e is indica ed by he figu es inside he odd and e en egis e s. Table III. A e age powe and cu en consump ion measu ed by elec ical simula ion. Elec ical Simula ion T i ium MPLP T i ium Reduc ion (%) A e age powe 4.09mW 2.98mW 25 A e age cu en 1.22 mA 0.9 mA 25 Maximum peak cu en 51.2 mA 42.1 mA 17 MPLP, mixed pa allel low powe . Table IV. Powe consump ion measu ed by logical simula ion and he Encoun e ool. Powe a 25 MHz a 3.3 V 350nm T i ium (mW) MPLP T i ium (mW) Reduc ion (%) Dynamic 5.84 4.36 25 Swi ching 1.12 1.11 Cell in e nal 4.72 3.24 31 MPLP, mixed pa allel low powe . The gene a ion o he inpu bi s o each shi egis e and he gene a ion o he key s eam depend on bi s s o ed in di e en posi ions in he shi egis e s. Bu he p oblem posed by his new s uc u e is ha he loca ion o hose bi s depends on whe he he clock cycle is odd o e en. In one case, he bi o be e ie ed is in he e en egis e , and in ano he , i is in he odd egis e . So ha he bi s a e co ec ly selec ed, glue logic mus be in oduced. This added logic basically in ol es he use o mul iplexe s, which, using he clock as he selec ion signal, will selec he bi o be e ie ed om he odd o e en shi egis e (Figu e 5). The FPLP T i ium e sion was desc ibed and designed using VHDL. The esul ing implemen a ion was e ified using he ModelSim simula ion en i onmen wi h a pos -layou ne lis . The FPLP implemen a ion inc eases he numbe o he cells and ne s because mo e mul iplexe s and combina ional cells ha e o be added o implemen he algo i hm. Table V shows he Synopsys cell and ne coun s o a 350-nm echnology. The FPLP e sion uses mo e cells (6.6%) and mo e ne s (16%) han he s anda d T i ium and MPLP implemen a ions. As wi h he MPLP e sion, he amoun o swi ching aking place in he shi egis e flip-flops was analyzed. In each clock cycle, he esul s o he a e age (a g) and maximum (max) numbe o flip- flops ha change ( om le els 0 o 1 and 1 o 0) we e compa ed wi h hose ob ained o he s anda d e sion o he T i ium and a e shown in Table VI. As can be seen in he able, he a e age numbe o flip-flops changing hei ou pu in each clock cycle was 138 o he s anda d T i ium and 70 o he FPLP T i ium. This ep esen s a educ ion o 49%. This educ ion also occu s in he a e age numbe o swi ches om le els 0 o 1 and 1 o 0. Figu e 5. Full-pa allel low-powe T i ium schema ic. Table V. Numbe o cells and ne s epo ed by Synopsys in T i ium and FPLP T i ium. Synopsys epo 350nm T i ium FPLP T i ium O e head (%) Cell 617 748 6.6 Ne s 792 921 16 FPLP, ull pa allel low powe . Rega ding he a ea, he combina ional a ea and he ne a ea a e ine i ably la ge in he FPLP T i ium because mo e mul iplexe s and combina ional cells ha e o be added o implemen he algo i hm. Table VII shows he a ea es ima ion epo s p o ided by he Design Vision syn hesis ool o he FPLP and s anda d e sions. The combina ional a ea o he FPLP e sion is 19.1% la ge han ha o he s anda d e sion. The non-combina ional a ea, howe e , is qui e simila in bo h designs because he numbe s o flip- flops do no change (only one flip-flop is in oduced, o he clock di ision). The FPLP e sion hus has a cell a ea penal y o abou 4% while i s ne a ea inc eases by 8%. 4.1. Full-pa allel low-powe T i ium powe consump ion As in he MPLP e sion, we closely analyzed he na u e o powe consump ion in he FPLP e sion o iden i y exac ly whe e powe educ ion occu s. The powe consump ion measu emen s we e aken om elec ical and logical simula ions in T i ium layou ci cui s. The elec ical simula ions we e ca ied ou wi h a clock equency o 25MHz, simula ing o 1μs, as o he MPLP T i ium simula ions. Figu e 6 shows he wa e o m de ail o he powe supply cu en flow o bo h implemen a ions. Again, he powe supply cu en peaks in he s anda d e sion o T i ium a e e y simila on bo h clock edges. In he FPLP T i ium, howe e , he cu en peaks ise on he ising edges o he clock and o ally disappea on he alling edge. Table VI. Swi ching egis e s pe clock cycle in T i ium and FPLP T i ium. Swi ching egis e s Swi ching 0 o 1 Swi ching 1 o 0 A e age Maximum A e age Maximum A e age Maximum T i ium 138 158 69 80 69 78 FPLP T i ium 70 86 35 43 35 43 FPLP, ull pa allel low powe . Table VII. Synopsys a ea epo o T i ium and FPLP T i ium. Synopsys a ea epo 350nm T i ium (μm 2 ) FPLP T i ium (μm 2 ) O e head (%) Combina ional 26,990 32,159 19.1 Non-combina ional 99,590 100,573 1 Cell 126,580 132,732 4 Ne 17,559 19,017 8 FPLP, ull pa allel low powe . Figu e 6. Powe supply cu en pos -layou elec ical simula ion. FPLP, ull pa allel low powe . Measu emen s om he elec ical simula ions showed ha he peak cu en on he ising clock edge inc eased by abou 25% in he FPLP T i ium implemen a ion, because o he clock ee, bu d opped sha ply, by abou 93%, on he alling clock edge. Fu he mo e, he a e age cu en consump ion, as measu ed du ing he elec ical simula ion, dec eased by 15% in he FPLP T i ium (Table VIII). The a e age powe measu emen p oduced by he elec ical simula ion indica es a powe educ ion o abou 15% in he FPLP T i ium, as can be seen in he able. As in Sec ion 3.1, powe consump ion was again measu ed om logical simula ions. The powe consump ions o he wo implemen a ions (s anda d T i ium and FPLP T i ium) a e shown in Table IX. When hey a e compa ed, he FPLP T i ium can be seen o ha e a cell dynamic powe consump ion 23% lowe han ha o he s anda d e sion. Swi ching powe is e y simila in bo h e sions o T i ium. This esul di e s sligh ly om he measu emen s p oduced by he elec ical simula ion, and he powe educ ion is lowe han ha ob ained by es ima ing he numbe o flip-flop ansi ions by clock cycles because clock ee powe consump ion is now included. Table VIII. A e age powe and cu en consump ion measu ed by elec ical simula ion. Elec ical simula ion T i ium FPLP T i ium Reduc ion (%) A e age powe 4.09mW 3.39mW 15 A e age cu en 1.22mA 1.03mA 15 Maximum peak cu en 51.2mA 63.5mA 25* FPLP, ull pa allel low powe . *Means inc easing. Table IX. Powe consump ion measu ed by logical simula ion and he Encoun e ool. Powe a 25 MHz a 3.3 V 350nm T i ium (mW) FPLP T i ium (mW) Reduc ion (%) Dynamic 5.84 4.46 23 Swi ching 1.12 1.13 Cell in e nal 4.72 3.33 29 FPLP, ull pa allel low powe . Table X. Compa a i e summa y o T i ium e e ences. T i ium Dynamic powe Supply ol age (V) Clock a e Technology (nm) T i ium [13] 175.1μW 1.2 10MHz 130 T i ium [12] 34.7μW 1 MHz 130 T i ium [12] 227μW 10MHz 130 T i ium [12] 2.15 mW 100 MHz 130 T i ium [14] 337μW 1.2 5 MHz 130 T i ium [14] 641μW 3.3 5 MHz 350 T i ium adix-16 [15] 0.68μA 1.5 100 kHz 350 T i ium [17] 1007 μW 1.8 25MHz 180 FPLP [17] 712μW 1.8 25MHz 180 T i ium [17] 236μW 1.2 25MHz 130 FPLP [17] 178μW 1.2 25MHz 130 T i ium [17] 219μW 1.2 25MHz 90 FPLP [17] 179μW 1.2 25MHz 90 T i ium [ his wo k] 5.8 mW 3.3 25 MHz 350 MPLP [ his wo k] 4.3 mW 3.3 25 MHz 350 FPLP [ his wo k] 4.4 mW 3.3 25 MHz 350 FPLP, ull pa allel low powe ; MPLP, mixed pa allel low powe .