Integrated chaos generators

Integrated Chaos Generators MANUEL DELGADO-RESTITUTO, MEMBER, IEEE AND ANGEL RODRÍGUEZ-VÁZQUEZ, FELLOW, IEEE Invited Paper Thispapersurveysthedifferentdesignissues,frommathematical model to silicon, involved on the design of integrated circuits for the generation of chaotic behavior. Keywords—Analog CMOS, chaos, design methodology, design system, nonlinear circuit design. I. INTRODUCTION The design of electronic circuits with customized controllable chaotic behavior has potential interest in many application scenarios such as instrumentation, analog signal processing, and communication and ranging systems. Regarding instrumentation, chaotic circuits represent an efficient alternative for nonrepeatable pseudorandom signal generation. Such generators are useful for the implementation of noise sources—both white and colored—which are frequently employed at speech processing [1] and for testing the dynamic behavior of electronic systems [2], among many other applications [3]. On the other hand, chaos generators can be used in analog signal processing applications as a dither source to improve the performance of other blocks. For instance, dithering can be used to whiten the noise floor of modulators, as well as to reduce the (idle channel) spurious tones, which are introduced during quantization of direct current (dc) inputs (audible in voice-band applications) [4], [5]. Also, dithering can be used to improve the integral nonlinearity of high-performance Nyquist-rate analog-to-digital converters [6]. In another application, chaos generators can be used, together with certain dynamic element matching mechanisms, to make digital-to-analog errors average to zero over multiple sample instances [7]. Manuscript received July 6, 2001; revised December 12, 2001. This work was supported in part by the C.I.C.Y.T, Spain, under Grant 1FD97-1611(TIC), in part by the Spanish P.R.O.F.I.T. Project AFIN (FIT-070000-2001-843), and in part by the EC Project INSPECT (ESPRIT 31103). The authors are with the Institute of Microelectronics of Seville–National Center for Microelectronics (IMSE-CNM), Seville 41012, Spain (e-mail: [email protected]). Publisher Item Identifier S 0018-9219(02)05238-6. In ranging systems, the nonperiodicity of chaotic signals, as well as the rapid decorrelation of their time-shifted sequences, make the use of chaos an interesting coding technique for high resolution radar systems [8]. Finally, chaotic circuits play a prominent role in chaos-based digital communication systems as they supply the required sample functions to which information symbols are mapped to [9]. In these systems, chaos generators, instead of conventional frequency synthesizers, provide the communication carriers, which are modulated by the digital information that is transmitted. Inherent to this chaotic modulation, the digital information also experiments a bandwidth spreading as a consequence of the wideband and noise-like spectral properties of chaos. This capability of simultaneous modulation and spreading, with an a priori lower system complexity than traditional spread spectrum techniques, is deserving a considerable research interest during the last years. In the aforementioned applications, chaotic circuits can be realized by interconnecting discrete integrated circuit (IC) component parts on a printed circuit board. However, whenever system miniaturization and/or power consumption are issues, chaotic circuits must be realized as monolithic ICs, preferably in standard complementary metal–oxide–semiconductor (CMOS) technologies where they can be embedded with other digital and analog circuitry. The objective of this paper is, indeed, to survey the different design techniques, both at system and circuit levels, involved in the monolithic realization of chaotic ICs. Though the design of chaotic generators can be afforded from different perspectives as, for instance, by adjusting the parameters of well-known oscillators or phase-locked loop structures[10],thispaperfocusesonasystematicstate-space approach, which lead to more general solutions, based on the electronic synthesis of the system state equations. Following this approach, Section II reviews the mathematical models leading to chaotic behavior and identifies the basic building blocks required for their implementations. They are classified into linear (covered in Sections III and IV) and nonlinear (described in Section V) operators. Finally, Section VI 0018-9219/02$17.00 © 2002 IEEE PROCEEDINGS OF THE IEEE, VOL. 90, NO. 5, MAY 2002 747 Authorized licensed use limited to: Universidad de Sevilla. Downloaded on April 13,2020 at 14:49:35 UTC from IEEE Xplore. Restrictions apply. presents three chaotic IC prototypes which illustrate the application of the methodological aspects and circuit concepts previously described. II. MATHEMATICAL MODELS FOR CHAOS GENERATION Every mathematical model able to produce chaotic behavior has two basic ingredients: dynamics and nonlinearity. Regarding dynamics, models for chaos generation can be classified into discrete-time or continuous-time, depending on whether the system evolution is described by nonlinear difference or differential equations, respectively. Another possible classification is between autonomous or nonautonomous systems, which depends on whether the generator is able or not to self-sustain chaotic oscillations without any external driving excitation. Because this last classification has a weak impact regarding IC implementation, we will focus exclusively on the autonomous case. In the following, we will separately review the basic features of discrete-time and continuous-time chaos generators, identifying the basic operations needed for their synthesis. Asalreadymentioned,asystematicstate-spaceapproachwill be used as the theoretical framework to express (and later to implement) the different chaotic systems. A. Discrete-Time Chaos Generators Autonomous discrete-time systems (or discrete maps, in short)canbegenerally describedbythefollowing th(delay) order -dimensional ( -D) finite-difference equation (FDE): (1) where symbolizes the discrete-time variable, represents the state vector of the system at the th discrete time instant, and is a -D time-invariant nonlinear vector field that depends on the parameter set . For the purposes of signal generation, we will assume that system (1) is characterized by an invariant set under , such that any trajectory starting in remains confinedtoit.Additionally,themodelmayalsoincludea -D output equation defined in terms of the most recent states of the system (2) where is the output vector of the discrete map at the th instant and is a function, in general, nonlinear and parameterized by a vector . Among the discrete maps defined by (1), first-order systems ( ) play a major role as they model most of the electronic chaos generators proposed so far. Their state equation may be written as (3) where , , , and is a nonlinear time-invariant vector field ( and ). Fig. 1 shows a block diagram for first-order discrete-maps comprising a linear section, a nonlinear function block connected in a (a) (b) Fig. 1. (a) Block diagram of a first-order FDE-based chaos generator. (b) Operations encompassed in the 1 block [element in the inset of Fig. 1(a)]. Table 1 Short Catalog of Chaotic Discrete Maps feedback loop [11] and an output stage. The linear section, included in the dashed box of Fig. 1(a), consists of static and dynamic elements. The static elements realize the operations of summation and scaling (blocks labeled and ). On the other hand, the dynamic element performs sample-and-hold (S/H) and delay operations, as shown in Fig. 1(b). Usually, such element is implemented by a single electronic device which, hereafter, will be represented by the symbol in the inset of Fig. 1(a) and denoted as delay element. The clock signal fixing the sampling period of the delay element determines the iterations of the feedback loop. Table1containsashortcatalogoffirst-orderdiscretemaps which have been implemented in electronic form, either by means of discrete components or integrated on silicon. For 748 PROCEEDINGS OF THE IEEE, VOL. 90, NO. 5, MAY 2002 Authorized licensed use limited to: Universidad de Sevilla. Downloaded on April 13,2020 at 14:49:35 UTC from IEEE Xplore. Restrictions apply. Fig. 2. Block diagram of an ODE-based chaos generator. each entry, Table 1 shows the particular settings for and ,accordingto(3). Thedefinitionintervalofthemaps and their parameter ranges to achieve chaotic regime can be foundinthereferencesattachedtothefirstcolumnofTable1. An important conclusion that can be drawn from Table 1 is that chaotic behaviors can be obtained from very simple mathematical models. Indeed, a single state-variable is required to generate chaos, as occurs in the 1-D maps listed in the first eight rows of Table 1. Thereby, simple monolithic realizations can be expected from the use of discrete maps. In spite of this structural simplicity, the dynamic behavior of the system can be extremely rich and complicated. This will be illustrated in Section VI by means of the Bernoulli map defined in the fifth row of Table 1. B. Continuous-Time Chaos Generators As already mentioned, continuous-time chaos generators arethosethatcan bedescribedbynonlineardifferentialequations.Amongthem, we canfurther distinguishbetweenthose based on ordinary differential equations (ODEs) and those based on delay-differential equations. The latter have been recentlyproposedas anefficientmethodforthegenerationof high fractal dimension chaos with no substantial increase on complexity (a first order system is enough to produce chaotic behavior) [24]. Nevertheless, these systems are still far from being well understood and we will focus on ODE-based systems, for which a lot of research has been done in the last decades. Autonomous continuous-time ODE-based chaos generators belong to the space of -D dynamical systems with nonlinear elements, defined by the state equation (4) where is a diagonal matrix defining the time-integration constants of the system, is the state vector, , , , and is a nonlinear vector field (and ). Such systems can be mapped onto the analog computer concept of Fig. 2. It consists of a forward path containing a linear time-invariant subsystem(includedinthedashedboxofFig.2),afeedbackpath including the nonlinear elements of , and an additional path to synthesize the output vector .As Table 2 Catalog of ODE-Based Autonomous Chaotic Oscillators can be seen, the only difference between the conceptual diagram in Fig. 2 and that associated to first-order discrete maps inFig.1(a)istheuseofintegratorsinsteadofdelayelements. This apparently minor change has, however, strong implications regarding system design, as will be shown next. Table 2 includes some exemplary ODE-based chaotic systems found in the literature. Conditions on the different system parameters to guarantee chaotic behavior can DELGADO-RESTITUTO AND RODRÍGUEZ-VÁZQUEZ: INTEGRATED CHAOS GENERATORS 749 Authorized licensed use limited to: Universidad de Sevilla. Downloaded on April 13,2020 at 14:49:35 UTC from IEEE Xplore. Restrictions apply. be found in the references attached to the first column of Table 2. The remaining columns indicate, respectively, matrices , and the elements of the vector field in accordance to the state representation in (4) (in all cases, is a null vector and is the identity matrix). Circuit demonstrators using off-the-shelf discrete electronic devices have been reported for all the examples in Table 2 and those in rows 3, 7, 9, and 12 have been also implemented in monolithic form. Table 2 reveals a well-known fact: in autonomous ODE-based systems, three state variables are at least required to generate chaos if the nonlinear feedback path in Fig. 2 is memoryless. Otherwise, if the vector field exhibits hysteresis, as occurs in the last row of Table 2, the jumps in the hysteretic elements correspond to additional states [36]. This is clearly in contrast with discrete maps for which single state-variable systems are enough to produce chaotic behavior. C. General Considerations for the Design of Chaotic ICs Inthe previoustwo sections,boththe architectures and operations required for the systematic design of chaos generators using a state-space approach have been identified. One step ahead is to apply the appropriate transformations on the mathematical models to make them suitable for synthesis in monolithic form. Such modifications must consider two different aspects that are related, on the one hand, to the particular nonlinear vectorfield and,ontheother,totheoverallstateequation of the dynamical system [defined by (3) for discrete maps or (4) for ODE-based generators]. First, let us consider the nonlinear vector field. The synthesis of arbitrary nonlinear functions in IC form can be achieved by relying to systematic representation techniques where operators are closely related to the nonlinearities available at the design primitives (details are given in Section V). Nevertheless, for the sake of reliability and also to reduce the hardware complexity of the design (and, hence, its area and power consumption), nonlinear vector fields should be made as “primitive-based” as possible in order to reduce the number of such elementary operators. It is, therefore, strongly suggested to properly alter the nonlinear vector field (if it deviates too much from a simple primitive-based representation) while retaining the most relevant features of the targeted dynamic behavior. In particular, simplification strategies based on piecewise-linear (PWL) modeling are specially appealing for IC realization because of the accuracy and simplicity of their synthesis—it is ultimately based on the controled transition between the ON and OFF states of transistors, as nonlinear primitive operator. An example of piecewise linearization is given by the ODE-based systems in the rows 8 and 9 of Table 2, in which multipliers are replaced by simpler PWL nonlinearities, namely, sign inversion and absolute value operations. Another advantage of PWL modeling, in particular for high-accuracy IC implementations, is that the dynamical system becomes linear at each region of the space partition and, hence, well-defined calibration [38], [39] and Fig.3. Annihilation ofchaoticdynamics in the tent map for B =2 . tuning [40] mechanisms are readily applicable to precisely trim each of the affine characteristics. Another important issue for the choice of an IC-suitable nonlinear vector field is the robustness of the system dynamics [22], [42]. Because of the limited accuracy of analog circuit implementations, models for chaos generators must be robust enough so that the unavoidable technological parameterdeviationsdonotseverelydegradethe prescribeddynamic features. A main consequence of this fact is that some nonlinearities, which are often found in theoretical studies, must be precluded for electronic chaos generation, unless they are conveniently transformed. A typical example is offered by the tent map, defined in the fourth row of Table 1. In order to obtain a uniform distribution of the chaotic time-se- ries, parameter is set to 2, as illustrated in Fig. 3. In this configuration, if for some circuit impairment or noise contribution, the trajectory jumps outside the nominal invariant set (shaded area in Fig. 3), the system evolves after a transient to the parasitic equilibrium point , which arises from the saturation characteristics of the circuit (long-dashed rectangle in Fig. 3). As a result, the chaotic behavior vanishes and the nominal invariant set collapses to the stable fixed point .Toavoidthissituation,themap must be transformed so that it exhibits a basin of attraction larger than its nominal invariant set, with a clearance between them determined by the maximum expected perturbations in the circuit implementation. Different strategies to achieve this goal can be found in [15], [22], [41], [42]. Let us, now, consider the overall state equation of the chaotic system. For similar reasons of reliability and cost, it should be simplified before implementation. This can be accomplished by, first, defining a family of dynamical systems that retains almost all features of the targeted model and, second, by identifying which element of such family is the most convenient from an IC perspective. Essential to the first step is the concept of linear conjugacy,1among dynamical systems [43], [44], as it guarantees that both the 1Two dynamics systems F ( 1 ) and H ( 1 ) are said to be linearly conjugated if there exists a nonsingular matrix M such that M  F = H  M (“  ” denotes composition). 750 PROCEEDINGS OF THE IEEE, VOL. 90, NO. 5, MAY 2002 Authorized licensed use limited to: Universidad de Sevilla. Downloaded on April 13,2020 at 14:49:35 UTC from IEEE Xplore. Restrictions apply. original model and the elements of its linearly conjugated family exhibit the same qualitative dynamics. Interestingly enough, it has been shown that for a wide class of dynamical systems, namely, those which can be represented in Lur’e form,2linear conjugacy between systems with the same vector field is assured whenever the eigenvalues of corresponding matrices , and , are identical [44]. This implies that the family of linearly conjugated Lur’e forms built upon a given nonlinear vector field can be exactly defined by less parameters than those nominally included in the representations (3) and (4)—together with vector . Hence, there exist infinitely many linearly conjugated elements able to reproduce the same qualitative dynamics as the original model, which allows one to establish a selection procedure aimed to determine that element most suitable for IC realization.3Some tailoring criteria for this selection procedure are [32]. 1) Low Complexity: Because system parameters must be mapped into physical devices, those vector fields with a minimum number of different nonzero entries in , and —they are referred to as canonical elements—are a priori the best suited in terms of area and power consumption. In particular, those configurations with proportional to a unitary vector are preferred because the vector field exhibits a single nonlinear block. 2) Optimum Dynamic Range: The dynamic range of a chaos generator is maximized as long as all its state variables are able to swing up to a maximum tolerable level imposed by the power supply of the circuit [1], [47]. The procedure by which this maximization can be achieved is scaling and basically consists on applying a convenient similarity transformation on the state vector . It is worth pointing out that scaling does not affect the system architecture (null entries to matrices and remain unaltered after scaling), but the canonical property of the original system may be lost, i.e., system parameters, initially with identical magnitude, turn to be different after scaling, thus leading to an increase on the system complexity. 3) Reduced Mismatch: Ratio accuracy (or matching) of similar components is enhanced as long as circuit elements are built by replicating a given unitary device [48]. Thus, if system parameters are related by integer ratios, the IC improves in accuracy and, at the layout level, in modularity and integration density. This improvement, however, reduces as the spread of system parameter values increases [48]. Thus, the unitary elements replication approach must be accompanied, in some cases, by techniques aiming 2Dynamical systems in Lur’e form are systems defined by (3) and (4) in which the vector field fff ( 1 ) , assumed memoryless, depends on w x , where w 2< . For our purposes, it will further assumed that Lur’e forms are observable in the classical sense of control theory [45]. 3It is worth noting that multidimensional PWL representation with parallel boundary planes [46] can be also expressed in Lur’e form and, hence, they are also suitable for system level optimization—an additional advantage on the use of PWL models for chaos generation. to reduce the spread of system parameters [1]. Once again, this can be achievedby using a proper similarity transformation on the state variables. A final (and critical) system-level consideration that must be addressed on the design of chaos generators is to evaluate the tolerance of the dynamic behavior against parameter deviations. Such deviations are due to the fact that physical circuit components (e.g., capacitors, operational amplifiers, comparators, etc.) deviate from nominal values or design intent because of a variety of nonidealities which can be grouped into three main categories, namely, noise, static, and dynamic [39]. Noise category basically comprises the errors due to thermal noise generated by solid-state devices. On the other hand, mismatch of ideally identical devices, which results from uncontrolled technological parameters in the fabrication process, and dc-related errors such as offset, signal-independent charge injection, and finite dc gain of active components can be grouped as static nonidealities. Saturation characteristics that result from the upward limited dynamic range of the circuit elements can be also seen as an static nonideality. Finally, dynamic errors sums all frequency dependent nonidealities such as signal-dependent charge injection, limited dynamic accuracy in comparators, limited slew-rate, and limited gain-bandwidth product in amplifiers. In order to tie the degradation of the chaotic dynamics to the above nonidealities, each of the error sources must be conveniently modeled and incorporated in the nominal representations (3) or (4) [22], [32]. Then, a worst-case analysis, together with exhaustive simulations of the system including all nonideal effects, must be made to determine the specifications for the different building blocks of the architecture. This bridges the system and circuit levels in the design route of the chaos generator. Of course, there may be cases in which the calculated block requirements are beyond the limitations imposed by the technological process. This occurs either when the specifications for the chaos generator (usually given in terms of output statistics) are too restrictive or when the system architecture shows a large sensitivity to some parameter variations, making it impractical for silicon implementation. In this last case, if the mathematical model belongs to a family of linearly conjugated systems, a new element that is less sensitive to parameter inaccuracies must be found. In general, there is not a simple way to link chaotic system perturbations and deviations on statistic performance other than by long-run simulations. Only for PWL chaotic models, where the system behaves linearly at each region, a classical sensitivity analysis [49] on the eigenvalues pattern—which determines the qualitative dynamics of the generator—with respect to the circuit components can be useful to estimate how far the dynamic behavior deviates from the nominal one [32]. D. Concluding Remarks In this section, we have explored different alternatives of chaos generators, given selection criteria for high-level optimization, and identified the basicoperations involved in their implementation. Such operations can be classified between DELGADO-RESTITUTO AND RODRÍGUEZ-VÁZQUEZ: INTEGRATED CHAOS GENERATORS 751 Authorized licensed use limited to: Universidad de Sevilla. Downloaded on April 13,2020 at 14:49:35 UTC from IEEE Xplore. Restrictions apply. (a) (b) (c) (d) Fig. 4. Basic concepts for the continuous-time dynamics. (a) Open-loop integrator. (b) Miller integrator. (c) Parasitics of integrated capacitors. (d) First-order frequency-domain model of a transconductor. linear and nonlinear and within the first group, between dynamic (continuous-time integrators and delay elements) and static (signal weighting and summation) operators. In the following sections, we will present some general ideas and concepts for the IC realization of these operations, paying special attention to the nonidealities which affect them, as they ultimately determine the accuracy and operation speed of the chaos generator. III. LINEAR OPERATORS FOR CONTINUOUS-TIME GENERATORS A. Integrators Because monolithic inductors are only feasible at very high frequencies,4capacitors are the basic dynamic primitives of ODE-based chaotic ICs. State variables are, hence, voltages and the dynamic updating of these voltages is realized by driving the state capacitors through currents. Fig. 4 shows two alternative implementations of this dynamic updating: the open-loop [see Fig. 4(a)] and the Miller [see Fig. 4(b)] structures. In both cases, the excitation is obtained for convenience as the result of a linear voltage-to-current transformation—using a transconductor—from an intermediate voltage , i.e., . Ideally, both circuits obtain (5) which corresponds to the behavior of an integratorwith nominal time constant ( stands for the th state variable of the system). The differences between these alternative realizations arise when parasitics are accounted. In the foregoing analysis, considered parasitics are the following. 4Interestingly enough, some (integratable) classical oscillators based on passive resonant circuits, such as the Colpitts oscillator [28], can exhibit chaotic behavior upon proper parameter setting, thus giving the possibility of generating chaotic signals in the gigahertz range. Table 3 Time-Constant Error and Approximated Poles of the Open-Loop and Miller Structures 1) Those associated with the capacitor [see Fig. 4(c)], consistingoftwoadditionalcapacitors(bottomandtop plates). 2) The first-order small-signal parasitics of the transconductor, namely: output resistance , output capacitance , and frequency-dependent transconductance [see Fig. 4(d)]. 3) The small-signal parasitics associated to the op-amp. Obviously, these are dependent on the op-amp architecture. Here, we assume that the op-amp is internally compensated, has low output impedance (negligible for analysis purposes), and can be modeled as [48] (6) First of all, note that in the structures of Fig. 4(a) and (b), the capacitor terminal labeled is connected to a lowimpedance point (a point where the voltage changes only slightly for large current ranges). In Fig. 4(a), the terminal is directly connected to an alternating current (ac) ground, while in Fig. 4(b), the low-impedance feature is achieved by theop-amp outputnode.Consequently,the twostructuresare insensitiveto , i.e., the parasitic hasvirtually no influence on the circuit behavior.5Let us now separately analyze the circuits of Fig. 4(a) and (b). In the structure of Fig. 4(a), the parasitic capacitors and are connected in parallel with the nominal capacitor . This makes the integrator time constant to deviate from its nominal value as , where the time-con- stant error is given in Table 3. In addition, the parasitic resistances connected to the node produce losses in the integration and, hence, the dynamic behavior deviates from the nominal one represented by . The actual transfer function is (7) where is the low-frequency pole created by the parallel connection of and (see Table 3) and 5This is not exactly true as this capacitor may influence the transient response of the op amp, especially when the op amp has a single-stage architecture [48]. 752 PROCEEDINGS OF THE IEEE, VOL. 90, NO. 5, MAY 2002 Authorized licensed use limited to: Universidad de Sevilla. Downloaded on April 13,2020 at 14:49:35 UTC from IEEE Xplore. Restrictions apply. Fig. 5. Equivalent circuit for the analysis of the Miller configuration. represents the transconductor frequency response.6 The transfer function models the so-called dynamic error of the integrator. This error is negligible only for those frequencies, where . Neglecting at this point the influenceofthetransconductor,thesefrequenciesaredefined by . Considernowthe Miller configurationof Fig.4(b).Tofirst order, the subcircuit formed by the op amp and the capacitor can be represented by the equivalent circuit at the right of node in Fig. 5—obtained by applying the Miller theorem. Analysis of this circuit obtains (8) which contains two poles at and , respectively, and displays time constant errors in the passband . Assuming that and are largely separated and that ,oneobtainsthepole expressionsshowninTable3.Withinthepassbandfrequency range, where the circuit operates as an integrator, (8) can be approximated by (9) thus leading to the expression of given in Table 3. It shows that the time constant error is inversely dependent on the op-amp dc gain and, hence, very small. Comparing the Miller and the open-loop configurations, the following conclusions can be drawn. 1) In the Miller configuration, the time constant error is attenuated by . Hence, the Miller integrator exhibits superior performance regarding the influence of the parasitic capacitances. It is a consequence of the fact that, in the passband, the op amp exhibits very small input resistance given by , which dominates over other impedances connected to this node.In the limit, as , this resistance becomes null and the op-amp input becomes a virtual ground. 2) The low-frequency corner of the passband, given by , is much smaller for the Miller than for the open loop. In the latter, the output conductance manifests as such in the expression of , while, for the 6To first-order analysis, the frequency dependence of transconductances can be modeled by using a single pole T ( s )  (1 + s=! ) . This model can be valid for frequencies up to tens of megahertz. For more detailed models, see [50]. Miller configuration, it manifests attenuated by . This is another positive consequence of feedback. 3) The high-frequency corner is smaller for the Miller configuration—a negative consequence of feedback. In the open-loop configuration, the high-fre- quency behavior is limited by the dynamic response of the transconductor , while in the Miller one, it is also limited by . Assuming that the op amp and the transconductor are optimized, it is likely that the latter exhibits a frequency range wider than , thus, inferring poorer frequency response for the Miller configuration than for the open-loop one. Summarizing,thepreviousanalysisshowsthattheopen-loop configuration is preferable for high-frequency applications, though it may require predistortion to compensate for the time constant errors. On the contrary, the Miller configuration is more appropriate for low and medium frequencies, requiring no predistortion. Note, however, that the degradation of the frequency response in the Miller structure is mainly a consequence of the model used for the op amp. High-fre- quency advantages of the open-loop structure are not so evident if custom op amps without internal compensation are used [51]. In addition, frequency response of Miller structure may perhaps be enhanced by active compensation techniques [49] to properly shape the integrator high-frequency response and, thus, combine the features of accuracy, small losses, and large frequency bandwidth into a single structure. Another comparison between the two configurations concernstheirsuitabilityforICimplementation.Specifically,the fact that ac grounded capacitors (i.e., those that have one of theirterminalstiedtoeitherthepositiveorthenegativepower supply) are better suited than floating capacitors. B. Signal Summation The circuits of Fig. 4(a) and (b) can be extended to perform summing integration by routing all the voltage-to-cur- rent transformation outputs (each associated with a summing term) to node and letting Kirchoff current law (KCL) to work. In this way, the basic structure to implement (4), conceptually shown in Fig. 6(a), is defined.Note that every summing term has an output conductance and an output capacitance. Hence, at node , the equivalent conductance and capacitance are given, respectively, by (10) where and are mean values of the individual conductances and capacitances, respectively, and is the number of excitations [according to (4) ]. After substituting by and by in the expressions of Table 3, we notice that increases proportionally with for the open-loop configuration. The same enlargement is observed in the Miller integrator. However, the whole error for this configuration is still attenuated DELGADO-RESTITUTO AND RODRÍGUEZ-VÁZQUEZ: INTEGRATED CHAOS GENERATORS 753 Authorized licensed use limited to: Universidad de Sevilla. Downloaded on April 13,2020 at 14:49:35 UTC from IEEE Xplore. Restrictions apply. Fig. 6. (a) Obtaining the state variable updating current as the summation of M current components. (b) Using a second-generation current conveyor to isolate the summing node from the state variable node. (c) Concept for the realization of current conveyors. by . As a counterpart, the frequency behavior of the open-loop integrator remains virtually unchanged, while the value of for the Miller configuration decreases inversely proportional to . A strategy to attenuate the errors caused by the summation of signals is to isolate the node where the currents are aggregated from that where the resulting current is applied to the state capacitor. This is represented in Fig. 6(b) for the open-loop configuration, although it can be used with the Miller configuration as well. The “glue” component is a currentconveyor[52].Actually,thecurrentconveyorinFig.6(b) is of the so-called second generation, whose ideal behavior is described by (11) On the one hand, it creates a virtual ground between the terminals and . On the other, it realizes a current follower operation between the terminals and . Depending on the polarity of the current transfer between the and terminals, the conveyor can be positive (CCII+) or negative (CCII-), which correspond respectively to theplus and minus signs in (11). In practice, the input terminals of the current conveyor can be realized by arranging two MOS transistors in feedback configuration around an op amp, as depicted in the conceptual circuit of Fig. 6(c). Then, the negative and the positive components of the input current can be rooted to the output node by using current mirrors [52]. Obviously, the current conveyorproduces new errors that must be taken into consideration for proper design. First-order analysis of these errors can be found in [53]. (a) (b) (c) Fig. 7. Structures for voltage-to-current conversion in the case of (a) low output resistance, (b) floating self-coductor, and (c) grounded self-conductor. C. Basic Strategies for Voltage-to-Current Transformation—Signal Weighting Along this section, voltage-to-current transformation has been modeled through a transconductor, i.e., a component whose output resistance—modeled through in Fig. 4(d)—is large by construction. Also, the transconductor input resistance has been implicitly assumed infinite and, consequently, loading errors at the transconductor driving node have been disregarded. However, in practice, voltage-to-current transformation is sometimes realized using circuits whose input and/or output resistances are not large by construction—for instance, MOS transistors operating in the ohmic region under strong inversion [54]. For transformation circuits having low input resistance, the only way to attenuate loading errors is driving the input node with low output resistance. On the other hand, for those having low output resistance, the loading problems can be attenuated by resorting to one of the structures of Fig. 7. In Fig. 7(a), the output node is clamped at a fixed value , thus annulling spurious current contributions to due to node voltage fluctuations. On the other hand, Fig. 7(b) and (c) is appropriate whenever the voltage-to-current transformation is realized by exploiting the self-conductance of either an active, i.e., composed of MOS transistors, or a passive resistor. Other important issues on the design of voltage-to-current transformation circuits are briefly reviewed in the following. Programmability: It basically refers to the possibility of scaling transconductances through electrical control 754 PROCEEDINGS OF THE IEEE, VOL. 90, NO. 5, MAY 2002 Authorized licensed use limited to: Universidad de Sevilla. Downloaded on April 13,2020 at 14:49:35 UTC from IEEE Xplore. Restrictions apply. variables. For instance, the transconductance of a MOS transistor in the saturation regime under strong inversion depends on the large-signal transconductance factor and on the gate voltage overdrive (see Fig. 12 in Section V for details). Two possible controlling scenarios, hence, arise: 1) taking advantage of the dependence of on transistor geometry and of the MOS transistor operation as an analog switch to realize digitally controled values; 2) taking advantage of the dependence on biasing conditions to realize analog-controled transconductance values. It is worth pointing out that programmability is the basic mechanism for signal weighting and, hence, for the implementation of the coefficients of , and in (4). Linearity: Another important issue regarding signal weightingistoguaranteelinearityoftheoverallinput–output characteristics. Because primitive components are essentially nonlinear (see Fig. 12), linearity on transconductances must be achieved by properly combining different elements. Many different strategies have been proposed for nonlinear cancellation as, for instance, by using differential configurations, by applying feedback, through inverse function techniques, etc. Some of these strategies are reviewed in [52]. Scaling Factor Accuracy: Scaling factor accuracy has two faces: absolute accuracy and ratio accuracy. The former refers to exactness in absolute values of transconductances and has tolerances of around 30%. Absolute accuracy is important in cases where timing is relevant. In these cases, a tuning mechanism must be incorporated to the circuit to reduce the tolerances to about 1%–2% [40], [49]. On the other hand, ratio accuracy, which was already considered as a selection criteria in Section II-C, can be made quite good—up to 0.1%—depending on the device areas, shapes, and distances [48]. IV. LINEAR OPERATORS FOR DISCRETE-TIME GENERATORS The implementation of delay elements for discrete maps always relies on the use of capacitors for storing and retrieving information in the form of voltages, switches for charging and/or discharging capacitors in response to a control signal, and active devices for defining the conditions of charge transfer. Main difference among analog sampled-data techniques come from the physical variables which is ultimately used to convey the information. Such variables can be in the form of voltages [switched-capacitor (SC) technique [11]), currents [switched-current (SI) technique [16]], timing characteristics of a pulse train (pulsewidth [13] or pulse-position modulation techniques [17]), or phase angles (phase-locking technique [14]), among other possibilities. In this paper, we will focus on SC and SI techniques. The SC technique requires op amps, as active devices, and linear capacitors, as holding elements [1], [56], [57]. High-quality capacitors (high linearity, reduced voltage, and temperature dependence, and good matching properties) are available in technologies that offer parallel-plate structures separated by thin oxide [58], [59]. If such structures are not available, as in pure digital CMOS technologies, capacitors arecommonlyimplemented byexploitingthethin-oxidegate capacitance of MOS transistors [60]. MOS-based capacitors usually exhibit larger capacitance per unit area and better matching than parallel-plate structures, but suffer from significant nonlinearities and parasitic capacitances, and must be conveniently biased to guarantee a low-resistivity conducting layer under the gate. As a result, SC circuits built on digital technologies have inevitably poorer performance than those implemented on analog-oriented processes. An alternativesampled-data approach that avoids the need for highly linear capacitors is the SI technique [61]. In this case, capacitors are simply formed by the input parasitics of transconductors, thus, rendering the approach specially appealing for standard digital processes. Unfortunately, this notable simplification is at the expense of performance degradations. Nevertheless, in applications requiring moderate accuracy, the complexity and area consumption of SI circuits is generally lower than that of SC circuits performing the same function, which makes SI technique a fallback alternative when low-cost fabrication is mandatory. A. Switched-Capacitor Linear Operators Consider the basic S/H structure of Fig. 8(a) [1]. Analog switches are controled by a clock with two nonoverlapping phases, as shown in Fig. 8(c). Switches labeled (respectively, ) turn ON in synchronization with the first (respectively, second) clock phase.7The circuit operates as follows. In the acquisition phase, switches labeled are ON and the opampisconfiguredasaunity-gainamplifier.Assumingthat the op amp is ideal, the input voltage is sampled by capacitor . In the holding phase, switch labeled is ON and the bottom plate of the samplingcapacitor isconnected tothe op-amp output. Since the top plate of remains connected tothe inverting inputofthe op amp, theoutputvoltageduring the holding phase keeps the previously sampled input. Altogether, the operation of the S/H circuit can be described by the following recursive equation: (12) thus providing unity-gain half-cycle delay of the input voltage during the holding phase and null output during acquisition. Full-cycle delay elements, as required by (3), can be realized by simply cascading two half-delay stages with alternating S/H clock phases. Taking advantage of the holding operation, SC techniques allowsimplerealizationsoftheaggregationandscalingfunctions. Consider, for instance, the SC circuit of Fig. 8(b) and assume the op amp is ideal. During phase , voltages are sampled by capacitors , while capacitor is discharged as a result of the virtual ground at the input terminals of the op amp. During the next phase, 7By convention, any arbitrary signal s ( 1 ) observed at the end of the first (respectively, second) clock phase will be denoted as s ( k +1 = 2) [respectively, s ( k ) ] k =0 ; 1 ; ... ,where T isthe clock signalperiod [see Fig.8(c)]. DELGADO-RESTITUTO AND RODRÍGUEZ-VÁZQUEZ: INTEGRATED CHAOS GENERATORS 755 Authorized licensed use limited to: Universidad de Sevilla. Downloaded on April 13,2020 at 14:49:35 UTC from IEEE Xplore. Restrictions apply. Fig. 15. SC schematics for Bernoulli map. (a) (b) Fig. 16. (a) Onset of parasitic stable points in the Bernoulli map due to improper setting of A . (b) Strategy to avoid locked states. Op-amp and related capacitors perform the weighted summation in (37) and introduce a half-cycle delay. Op-amp is used to implement the remaining half delay stage and complete the concept of Fig. 1(a). Parameters in the map are controled by the capacitors , , and and the dc voltage as follows: (38) The nonlinearity is realized via a phase-reverser switch arrangement controlled by a dynamic comparator. Depending on the value of , this arrangement makes to be either added or subtracted at the input of the op-amp , thereby yielding the sign operator in (37). The comparator consists of an input offset canceled amplifier, followed by a regenerative sense amplifier and a NOR-based latch [57]. Operation of the circuit in Fig. 15 is described by (37) whenever op amps work in their linear region. If any of the amplifiers enters in saturation, the circuit no longer implements (37) and locks at parasitic stable points close to the power rails. This undesirable situation can be avoided by properly setting parameter . To illustrate this point, Fig. 16 shows the open-loop transfer characteristics of the map, including op-amp voltage saturations, for two different values of andthesamevalueof . InFig.16(a),parasitic stable points and appear at the intersections of the transfer function characteristics with the bisecting line. This makes the circuit to evolve, after a transient, to either or , destroying any chaotic behavior. On the other hand,for Fig. 16(b) nospurious equilibria appear andchaotic waveforms are robustly generated. Necessary conditions to guarantee this last situation are (39) Fig. 17. Microphotograph of the SC Bernoulli map prototype. Fig. 18. Measured open-loop transfer characteristic of the SC Bernoulli map for (a) different values of A and (b) different values of B and B . Measured spectra for different B , B settings for (c) B = B =61 = 32 and (d) B =47 = 32 , B =39 = 32 . where denotestheopamp’spositive(negative) saturation level. Interestingly enough, the condition gives rise to the creation of a clearance between the invariant set of the system and its basin of attraction, which guarantees that, under small perturbations, trajectories are always reinjected into the invariant set. Other strategies to achieve this goal can be found in [15], [22], [41], and [42]. Fig. 17 shows the microphotograph of a programmable prototype of the circuit in Fig. 15 [15]. In this prototype, the slopes of the characteristic— for and for —can be separately controled by means of two binary weighted capacitors with six control bits each. Also, an additional control bit can be used to selectively open or close the feedback loop. Fig. 18(a) shows a family of curves for different values of voltage and slopes and fixed at 61/32. On the other hand, Fig. 18(b) shows a set of transfer characteristics obtained for different values of and with chosen so that V. Measurements in closed loop were also made for all possible combinations of and values inside the chaotic regime. Fig. 18(c) and (d) show the spectra obtained for two of these combinations using a clock frequency of kHz. Flat spectra were obtained for the cases . This is illustrated in Fig. 18(c), obtained for . The spectrum is flat up to 75 kHz (35% of the clock frequency) with a maximum deviation of 1 dB, which renders the circuit well suited for white 762 PROCEEDINGS OF THE IEEE, VOL. 90, NO. 5, MAY 2002 Authorized licensed use limited to: Universidad de Sevilla. Downloaded on April 13,2020 at 14:49:35 UTC from IEEE Xplore. Restrictions apply. Fig. 19. Programmable current-mode scaled delay block. (a) (b) Fig. 20. Current-mode realization of the Bernoulli map nonlinearity. (a) Circuit schematic. (b) Implemented characteristic. noise generation. On the other hand, for , generated noise becomes colored, as shown in Fig. 18(d). Now, let us consider implementation of (37) in current-mode domain [16]. The scaled delay operation is realized as a cascade of two track-and-hold SI stages with complementary phase clocks. As indicated in Fig. 19, the rightmost transconductor has a parallel digitally programmable structure controled by a digital word of 4 bits . This makes parameter B binary-pro- grammable from 1.0 to 2.0 at steps of 0.25—in practice, the scaling factor of the transconductor controlled by bit is made slightly less than to make parameter lower than 2.0 and, hence, avoiding divergent orbits. Fig. 20(a) shows a conceptual schematic for the realization of the PWL characteristics of Fig. 20(b). Its operation relies on the current rectifier of Fig. 14(a). Positive input currents are routed to node while, simultaneously, the voltage evolves to the high logic state, turning ON and OFF. Thus, a current (obtained by KCL) is directed to the output node through the transistor —the right-hand piece of Fig. 20(b) is implemented in this manner. Similarly, negative input currents turn ON and a current , obtained by KCL at node , is delivered to the output node. Fig. 21 shows a microphotograph of the SI Bernoulli map prototype [16]. It includes some extra circuitry to enable testing the output current and to open or close the feedback loop. Fig. 22(a) shows the measured PWL current transfer characteristics obtained from the prototype. Deviation from the ideal characteristic for input currents between 20 Ato 20 A is less than 0.2%. Fig. 22(b) shows a detail of the globalcharacteristics, inwhichtheinput currentswingsfrom 21 pA to 21 pA. It is intended to illustrate the resolution Fig. 21. Microphotograph of the SI Bernoulli map prototype. Fig. 22. (a) Measured characteristic of the nonlinear block. (b) Detail of the discrimination function. (c) Measured current waveform. (d) Power density spectrum. achieved in the current discrimination which, as already anticipated in Section V-B, amounts to a few picoamperes. Fig. 22(c) and (d) illustrates the closed loop operation of the prototype for a clock frequency of 500 kHz. Fig. 22(c) shows the measured current waveform at the output of the delay block for (actually, a slightly lower value as mentioned before), while Fig. 22(d) shows its associated power density spectrum. The waveform of Fig. 22(c) shows that apparently coincident values of result in quite different values after few iterations, thereby confirming the expected unpredictably feature. Regarding Fig. 22(d), detailed measurements shows a very flat spectrum from dc up to about 30% of the clock frequency (deviation in this range was of less than 1 dB). It is illustrative to compare performance of this circuit to that of the SC circuit in Fig. 15. Area occupation of the SI prototype is about one order of magnitude smaller than for the SC prototype. Also, for half the power consumption, the speedoftheSIprototypeisaboutthreetimesgreaterthanthat obtained from the SC prototype. This confirms the suitability of the SI technique for moderate system requirements. DELGADO-RESTITUTO AND RODRÍGUEZ-VÁZQUEZ: INTEGRATED CHAOS GENERATORS 763 Authorized licensed use limited to: Universidad de Sevilla. Downloaded on April 13,2020 at 14:49:35 UTC from IEEE Xplore. Restrictions apply. Fig. 23. Optimized Gm-C realization of the Chua’s oscillator. B. Chua’s Oscillator Fig. 23 shows the simplified schematic of an integrated prototype of the Chua’s oscillator [32]. It implements, indeed, a modified version of such oscillator, obtained from the optimization procedure described in Section II-C. The resulting model is slightly different to that shown in Table II and defined by matrices (40) where . The nonlinear function is still given by . In Fig. 23, all the integrating capacitors are assumed identical and the linear transconductors have been implemented by building a unitary block with gain and connecting in parallel as many of such units as indicated by the values of , , and . On the other hand, the nonlinear transconductor has been designed so that its output current also includes the linear term associated to the first entry of , i.e., (41) Fig. 24 shows the circuit used for the PWL function consisting of a front-end transconductor and a nonlinear circuit that operates in current-mode domain based on the high-ac- curate rectification mechanism described in Section V-B. Two further circuit level aspects have been considered in the design of the schematic of Fig. 23. One is the addition of dummy devices so that all the integration nodes exhibit the same capacitance by construction. Accordingly, the global time constant of the circuit is given by , where is the total capacitance at the state variable nodes. Since parasitics are nonlinear and depend on the operating point of the circuit, more than 80% of the total capacitance is contributed by the nominal integrating capacitance . Fig. 24. Implementation of the PWL transconductor. Fig. 25. Chip microphotograph. Fig. 26. Route to chaos in a silicon prototype of the Chua’s oscillator. Limit cycle for (a) period 1, (b) period 2, and (c) period 4. (d) Birth of Rössler-like attractor. (e) Rössler-like attractor. (f) Birth of double-scroll attractor. (g) Double-scroll attractor. (h) Periodic window. (i) Double-scroll attractor close to saturation. 764 PROCEEDINGS OF THE IEEE, VOL. 90, NO. 5, MAY 2002 Authorized licensed use limited to: Universidad de Sevilla. Downloaded on April 13,2020 at 14:49:35 UTC from IEEE Xplore. Restrictions apply. A second aspect is the introduction of a tuning mechanism [49] (not shown in Fig. 23) to reduce the absolute tolerance of the circuit time constant below 2% [32]. Fig. 25 shows a microphotograph of the chaotic oscillator, which includes the onchip tuning scheme, and other auxiliary circuitry for biasing and measurement purposes. Power dissipation is less than 1.8 mW for a symmetrical biasing of 2.5 V. The fabricated prototype is able to reproduce the whole bifurcation sequence leading to the chaotic attractors ofthe oscillator,as shownin Fig.26[32].Thedifferentphase portraits (projections on the plane ) has been obtained by progressively increasing parameter , while keeping the other system parameters fixed. As can be seen, the picture book reveals a period-doubling route to chaos, including periodic windows, as well as Rössler-like and double-scroll attractors. VII. SUMMARY Through proper design techniques encompassing considerations both at system and circuit levels, it is possible to design compact and robust chaotic ICs in CMOS technologies. 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Delgado-Restituto, “High-resolution CMOS current comparators: Design and applications to current-mode function generation,” An. Integr. Circuits Signal Processing, vol. 7, pp. 149–166, Mar. 1995. Manuel Delgado-Restituto (Member, IEEE) receivedtheDoctorenCienciasFísicasdegreefrom the University of Seville, Seville, Spain in 1996. In 1990, he joined the Research Staff of the Department of Analog and Mixed-Signal Integrated Circuit Design of the Institute of Microelectronics, University of Seville, Seville, Spain. Since 1998, he has been a Tenured Scientist of the Spanish Council of Research (CSIC). He current research interests include the design of analog and mixed-signal VLSI circuits for nonlinear signal processing, including vision chips, neurofuzzy controllers, and chaotic circuits for communications, the design and modeling of integrated circuits for wireless communication, and the design for reusability of analog and mixed-signal circuit blocks. 766 PROCEEDINGS OF THE IEEE, VOL. 90, NO. 5, MAY 2002 Authorized licensed use limited to: Universidad de Sevilla. Downloaded on April 13,2020 at 14:49:35 UTC from IEEE Xplore. Restrictions apply. Angel Rodríguez-Vázquez (Fellow, IEEE) was born in Seville, Spain. He is a Professor of Electronics with the Department of Electronics and Electromagnetism, University of Seville, Seville, Spain. He is also a Member of the Research Staff of the Institute of Microelectronics of Seville–National Center for Microelectronics (IMSE-CNM), Seville, Spain, where he heads a research group on analog and mixed-signal VLSI. His current research interests include the design of analog interfaces for mixed-signal VLSI circuits, CMOS imagers and vision chips, neurofuzzy controllers, symbolic analysis of analog integrated circuits, and optimization of analog integrated circuits. Dr. Rodríguez-Vázquez received the Young Scientist Award of the Seville Academy of Science in 1992, the IEEE Circuits and Systems Society Guillemin–Cauer Award in 1995 and the Best Paper Award of the European Conference on Circuit Theory and Design in 1995. He was an Associate Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—PART I: FUNDAMENTAL THEORY AND APPLICATIONS from 1993 to 1995, a Guest Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—PART I: FUNDAMENTAL THEORY AND APPLICATIONS Special Issue on Low-Voltage and Low-Power Analog and Mixed-Signal Circuits and Systems in 1995, a Guest Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—PART II: ANALOG AND DIGITAL SIGNAL PROCESSING Special Issue on Advances in Nonlinear Electronic Circuits in 1999, and a Chair of the IEEE Circuits and Systems Analog Signal Processing Committee in 1996. DELGADO-RESTITUTO AND RODRÍGUEZ-VÁZQUEZ: INTEGRATED CHAOS GENERATORS 767 Authorized licensed use limited to: Universidad de Sevilla. Downloaded on April 13,2020 at 14:49:35 UTC from IEEE Xplore. Restrictions apply.