Continuous-time cascaded ΣΔ modulators for VDSL: A comparative study

* [email protected]; phone +34955056666; fax +34955056686; www.imse.cnm.es Continuous-Time Cascaded Σ∆Modulators for VDSL: A Comparative Study Ramón Tortosa, José M. de la Rosa*, Angel Rodríguez-Vázquez and Francisco V. Fernández Instituto de Microelectrónica de Sevilla, IMSE-CNM (CSIC) Edificio CICA-CNM, Avda Reina Mercedes s/n, 41012-Sevilla, SPAIN ABSTRACT This paper describes new cascaded continuous-time Σ∆ modulators intended to cope with very high-rate digital subscriber line specifications, i.e 12-bit resolution within a 20-MHz signal bandwidth. These modulators have been synthesized using a new methodology that is based on the direct synthesis of the whole cascaded architecture in the continuous-time domain instead of using a discrete-to-continuous time transformation as has been done in previous approaches. This method allows to place the zeroes/poles of the loop-filter transfer function in an optimal way and to reduce the number of analog components, namely: transconductors and/or amplifiers, resistors, capacitors and digital-to-analog converters. This leads to more efficient topologies in terms of circuitry complexity, power consumption and robustness with respect to circuit non-idealities. A comparison study of the synthesized architectures is done considering their sensitivity to most critical circuit error mechanisms. Time-domain behavioral simulations are shown to validate the presented approach. Keywords: Analog-to-digital converters, sigma-delta modulators, continuous-time circuits. 1. INTRODUCTION Continuous-Time (CT) Sigma-Delta Modulators (Σ∆Μs)have demonstrated to be an attractive solution for the implementation of Analog-to-Digital (A/D) interfaces in systems-on-chip integrated in deep-submicron standard CMOS technologies 1. Although most reported Σ∆Ms have been implemented using Discrete-Time (DT) circuits, the increasing demand for broadband data communication systems has motivated the use of CT circuit techniques. In addition to show an intrinsic antialiasing filtering, CT Σ∆Ms provide potentially faster operation with lower power consumption than their DT counterparts 2,3. In spite of their mentioned advantages, CT Σ∆Ms are more sensitive than DT Σ∆Ms to some circuit errors, namely: clock jitter, excess loop delay and technology parameter variations 2,3. The latter are specially critical for the realization of cascaded architectures. This has forced the use of single-loop topologies in most reported silicon prototypes even thought low oversampling ratios ( ) are needed 4,5, whereas very few cascaded CT Σ∆M Integrated Circuits (ICs) have been reported 6. However, the need to achieve medium-high resolutions ( ) within high signal bandwidths ( ) while guaranteeing stability, has prompted the interest in proper methods for the synthesis of high-order cascaded CT Σ∆Ms 79. These methods are based on applying a DT-to-CT transformation to an equivalent DT topology that fulfils the required specifications. In most cases, the use of such a transformation is normally translated into an increase of the analog circuit complexity with the subsequent penalty in silicon area, power consumption and sensitivity to parameter tolerances. This paper presents a direct synthesis method of cascaded CT Σ∆Ms which, dispensing with the DT-to-CT equivalence, make it possible to reduce the analog circuitry complexity and place the zeroes/poles of the quantization noise transfer function in an optimal way, thus yielding to more robust architectures than using a DT-to-CT transformation. As an application, the proposed methodology is used to find optimum CT Σ∆Ms for Very high-rate Digital Subscriber Line (VDSL). Three fifth-order cascaded topologies are synthesized: 2-1-1-1, 2-2 and 3-2. These modulators are designed for 12-bit@20-MHz specifications and their performances are compared in terms of time-domain simulations that take into account critical error mechanisms like mismatch and clock jitter error. 12< 12bits>20MHz> VLSI Circuits and Systems II, edited by José Fco. López, Francisco V. Fernández, José María López-Villegas, José M. de la Rosa, Proceedings of SPIE Vol. 5837 (SPIE, Bellingham, WA, 2005) 0277-786X/05/$15 · doi: 10.1117/12.607923 59 Downloaded From: https://www.spiedigitallibrary.org/conference-proceedings-of-spie on 24 Jan 2020 Terms of Use: https://www.spiedigitallibrary.org/terms-of-use 2. CASCADED CONTINUOUS-TIME Σ∆ MODULATORS Fig.1 shows the conceptual block diagram of a cascaded CT Σ∆M. Each stage, consisting of a single-quantizer CT Σ∆M, re-modulates a signal containing the quantization error generated in the previous stage. Once in the digital domain, the outputs, , of the stages are properly processed and combined (by the cancellation logic) in order to cancel out the quantization errors of all the stages, but the last one in the cascade. This latter error appears at the overall modulator output shaped by a function of order equal to the summation of the orders of all the stages. Cascaded CT Σ∆Ms are normally synthesized from equivalent (well-known) DT systems and use the same digital cancellation logic 8. This DT/CT equivalence can be guaranteed because the overall open loop transfer function of each stage in Fig.1 is in fact a DT system 2. Thus, in the case of a rectangular impulsive response of the Digital-to-Analog Converter (DAC), it can be shown that the equivalent DT loop filter transfer function is given by 10,11: (1) where is the sampling frequency; ; ; and are respectively the time delay and pulse width of the DAC waveform; are the poles of and stands for the residue of . In order to get a functional CT Σ∆M while keeping the cancellation logic of the original DT Σ∆M, every state variable and DAC output must be connected to the integrator input of later stages 8. This increases the number of analog components, i.e transconductors, amplifiers and DACs. As an illustration, Fig.2(a) shows a cascaded CT Σ∆M obtained from an existing DT Σ∆M12. Note that at least eight scaling coefficients ( ) and their corresponding signal paths are needed to connect the different stages of the modulator. The number of integrating paths can be reduced −as shown in Fig.2(b) − if the whole cascaded Σ∆M is directly synthesized in the CT domain as proposed in the next section. 3. PROPOSED SYNTHESIS METHODOLOGY The idea of dispensing with the DT-to-CT transformation was previously reported in 3for single-loop architectures. However, in the case of cascaded architectures, the cancellation logic functions (not present in single-loop Σ∆Ms) must be included in the synthesis procedure to get an optimum architecture. Let us consider the more general case of the cascaded CT Σ∆M shown in Fig.1. The overall output, , is given by: (2) Figure 1. Conceptual block diagram of a cascaded CT Σ∆M. CT Σ∆M 1 CT Σ∆M 2 CL 1 CL 2 CL m . . . . . .. . . x(s) y 2 (z) y 1 (z) y m (z) y o (z) E 1 (z) E 2 (z) E m (z) Cancellation Logic CT Σ∆M m + DAC To next stage E 2 (z) y 2 (s) x 2 (s)F(s) y 2 (z) m-stage yi Fz() Re Fs() s ----------- em1TSs⋅ ze TSs⋅ – -------------------- ⋅    pi ∑Re Fs() s ----------- em2TSs⋅ ze TSs⋅ – -------------------- ⋅    pi ∑ –= f s1T s ⁄ = m11tdTs ⁄ –= m21tdτ + ()Ts ⁄ –= tdτ piFs()s⁄Re x() x 2-1-1 kg29– m-stage yo yoz() ykz()CLkz() k1= m ∑ = 60 Proc. of SPIE Vol. 5837 Downloaded From: https://www.spiedigitallibrary.org/conference-proceedings-of-spie on 24 Jan 2020 Terms of Use: https://www.spiedigitallibrary.org/terms-of-use where and represent respectively the output and partial cancellation logic transfer function of the stage. If the modulator input, , is set to zero, the output of each stage can be written as: (3) where stands for the , is the inverse Laplace transform, is the transfer function of the DAC, and (4) represents the transfer function from to the input of quantizer. Using the following notation (5) the output of each stage is given by: (6) and the output of the modulator can be written as: (7) Figure 2. Cascaded 2-1-1 CT Σ∆M architecture obtained (a) from an equivalent DT Σ∆M (b) using the proposed method. DAC CL 1 CL 3 1 T s s DAC CL 2 k g1 1 T s s k fb2 1 T s s k g5 k g9 k g8 k g7 k g6 k fb4 x(s) y o (z) (a) DAC DAC CL 1 CL 3 DAC CL 2 E 2 (z) E 1 (z) E 3 (z) y 1 (z) y 2 (z) y 3 (z)y 3 (s) y 2 (s) y 1 (s) y o (z) x(s) (b) E 1 (z) E 2 (z) E 3 (z) y 1 (s) y 2 (s) y 3 (s) y 1 (z) y 2 (z) y 3 (z) k in1 1 T s s k fb1 DAC k g2 k g3 k g4 k fb3 k in1 1 T s s k fb1 k in3 1 T s s k fb4 k g1 1 T s s k fb2 k in2 1 T s s k fb3 ykz() CLkz() k-th xt() ykz() Ekz() ZL 1–HDFik [] nTs    yiz() i1= k1 – ∑ + 1ZL 1–HDFkk [] nTs    – ------------------------------------------------------------------------------------------- = ZZ-transform L1 – HDHDAC s()≡ Fij Fij s()≡Input Quantizer j yis() ----------------------------------------- = yis() j-th Z km ZL 1–HDFkm () nTs   ≡ ykz() Ekz() 1Zkk – -----------------Zik yiz() 1Zkk – -------------------- i1= k1– ∑ += yoykCLk k1= m ∑Ek 1Zkk – -----------------1 1Zkk – -----------------Zik yi i1= k1– ∑ +    CLk k1= m ∑ == Proc. of SPIE Vol. 5837 61 Downloaded From: https://www.spiedigitallibrary.org/conference-proceedings-of-spie on 24 Jan 2020 Terms of Use: https://www.spiedigitallibrary.org/terms-of-use The partial cancellation logic transfer functions ( ) can be calculated by imposing the cancellation of the transfer function of the first quantization errors in (7). This gives: (8) where the partial cancellation logic transfer function of the last stage, , can be chosen to be the simplest form that preserves the required noise shaping. Note that the design equations (2)-(8) do not only take into account the single-stage loop filter transfer functions ( ), but also the inter-stage loop filter transfer functions ( ). The latter are continuous-time integrating paths appearing only when the modulator stages are connected to form the cascaded Σ∆M and must be included in the synthesis methodology to obtain a functional modulator with minimum number of inter-stage paths. Therefore, the following procedure can be used in a systematic methodology for the synthesis of cascaded CT Σ∆Ms††: • First, the poles of single-stage transfer functions ( ) are optimally placed in the signal bandwidth for given specifications. This process is carried out entirely in the CT domain and no equivalence to an existing DT modulator needs to be imposed. • Second, once the individual stages are designed and optimized, cancellation logics are calculated using (8). For illustrative purposes, the 2-1-1 CT Σ∆M of Fig.2(b) was synthesized using (2)-(8) to achieve resolution in a bandwidth, with a sampling frequency of 48MHz (oversampling ratio, ) 12.For simplicity, in order to facilitate the comparison of the performance of both modulators in Fig.2, the coefficients of the first stage ( ) are taken to be equal in both systems and are obtained from a DT-to-CT transformation of the first stage of a DT Σ∆Min12. The rest of coefficients in Fig.2(b) are taken such that the time constant of the integrators is the inverse of the sampling frequency ( ): (9) Hence, the single-loop and inter-stage transfer functions are given by: (10) and the partial cancellation logic transfer functions can be calculated using (8)-(10). Considering a Non-Return-to-Zero (NRZ) DAC, the following cancellation logics are derived: (11) †† In this procedure, the modulator order, oversampling ratio and number of bits of internal quantizers are assumed to be determined for given specifications from well-known expressions 1. CLk m1 – Ekz() C Lkz() ZkmCLm – 1Zmm – ------------------------ ZL 1–HDFkm [] nTs    CLmz( ) – 1ZL 1–HDFmm [] nTs    – ------------------------------------------------------------------------ - == CLmz() Fii F ij ij≠, Fii s() 16-bit 750-kHz M32 = kin1kg1kfb1kfb2 ,, , T s1f s ⁄ = kin1kfb1 – 14⁄ ;== kfb238⁄ –= kg1kin2k–fb3kin3k–fb41== == = F11 3Ts 8 ---------s1 4 --- +   – sTs () 2 ------------------------------ =F22 F33 1– sTs -------- == F13 3Ts 8 ---------s1 4 --- +   – sTs () 4 ------------------------------ =F23 1– sTs () 2 --------------- = CL1 z1– 48 -------729+z1–7z2– –5z3– –()= CL2z1–1z1– +()1z1– –() 2 = CL321 z1– –() 3 = 62 Proc. of SPIE Vol. 5837 Downloaded From: https://www.spiedigitallibrary.org/conference-proceedings-of-spie on 24 Jan 2020 Terms of Use: https://www.spiedigitallibrary.org/terms-of-use where is chosen to have three zeroes at DC, corresponding to the zeroes contributed by the first three integrators. In order to compare the robustness of both modulators in Fig.2, the effect of mismatch on the Signal-to-Noise Ratio ( ) was also simulated using SIMSIDES, a SIMULINK-based time-domain behavioral simulator for Σ∆Ms 13.For this purpose, maximum values of mismatch were estimated for a 0.13 µm CMOS technology and both modulators in Fig.2 were simulated considering a Gm-C implementation. The results are shown in Fig.3, where the loss is represented as a function of the standard deviation of the transconductances ( ) and capacitances ( ). For each point of these surfaces, 150 simulations were carried out using random variations with the standard deviation given in the diagrams. The value of loss represented in Fig.3 stands for the difference between the ideal , i.e with no parameter variation, and the with 90% of the 150 simulations above it. It is shown that the lower analog component count in Fig.2(b) is reflected in a lower variance of the modulator coefficients, leading to a better behavior in terms of sensitivity to mismatch. 4. APPLICATION TO VDSL As an application of the proposed methodology, three 5th-order cascaded CT Σ∆Ms, shown in Fig.4, were synthesized to cope with VDSL specifications: 12-bit resolution within a 20-MHz signal bandwidth. In order to fulfil these specifications without being limited by the clock jitter error, the sampling frequency, , and the number of bits of the internal quantizers (and DACs), , must be properly chosen. In the case of a 5th-order modulators like those shown in Fig.4, the inband jitter noise power is minimized for and 14. Another critical source of error in CT Σ∆Ms is the excess loop delay. As shown in 15 this error can be compensated by adding an extra feedback branch between the output and the input to the quantizer (DAC2in Fig.4) and two D-latches. By adding this extra branch with the appropriate gain, the loop impulse response is exactly the same as that of the original. This extra feedback term can be easily included in the calculation of the cancellation logic. In a practical implementation it could be advantageous to make DAC2programmable 5. Considering the factors above, the CT Σ∆Ms in Fig.4 were synthesized using the methodology described in Section 3, taking into account the following considerations: • The first stage of the 2-1-1-1 architecture (Fig.4(a)) is formed by a resonator which has its poles placed at , in order to minimize the quantization Noise Transfer Function (NTF) in the signal bandwidth, . Resistor variations can be tuned out using a combination of a discrete rough tuning of the resistors ( , and ) and a continuous fine tuning of the transconductors and . This tuning can be also used to cancel the effect of finite Gain-Bandwidth product ( ) of the front-end opamp, due to the fact that this error can be modelled as an integrator gain error 5. All the other transconductors could be tuned in order to keep the time constant unchanged over variations. • An additional resonator has been used in the 2-2-1 architecture (Fig.4(b)), in order to optimally distribute the poles of NTF 16. CL3 SNR Figure 3. Effect of mismatch on the SNR of a cascaded 2-1-1 CT Σ∆M obtained from: (a) an equivalent DT Σ∆M; (b) propose d method. (b) SNR Loss (dB) SNR Loss (dB) (a) SNR σgm σC SNR SNR SNR f s B f s240MHz = B4 = ωp2π79⁄Bw = BwRin Rfb Rr k ff kg1 GB Cg m ⁄C Proc. of SPIE Vol. 5837 63 Downloaded From: https://www.spiedigitallibrary.org/conference-proceedings-of-spie on 24 Jan 2020 Terms of Use: https://www.spiedigitallibrary.org/terms-of-use Figure 4. Cascaded CT Σ∆Ms synthesized for VDSL: (a) 2-1-1-1; (b) 2-2-1; (c) 3-2. + − D Latch DAC 2 D Latch DAC 1 DAC 3 DAC 4 DAC 5 CLK CLK CLK CLK CLK CLK CL 1 CL 2 CL 4 CL 3 C 1 C 2 C 3 C 4 C 5 R in k ff R fb R r k g1 k in3 k in4 k g5 k g2 k in2 k g3 k g4 k fb2 k fb3 k fb4 y o (z) x(s) (b)(a) (c) + − D Latch DAC 2 D Latch DAC 1 DAC 4 CLK CLK CLK CLK CLK CL 1 CL 2 CL 3 C 1 C 2 C 4 C 5 R in k ff1 R fb R r k g1 k in3 k g2 k in2 k g4 k g5 k fb2 k fb3 DAC 2 D Latch DAC 1 CLK CLK D Latch k ff2 k r2 k g3 C 3 y o (z) x(s) + − D Latch DAC 2 D Latch DAC 1 CLK CLK CLK CLK CL 1 CL 2 C 1 C 5 R in k ff2 R fb k g2 k g3 k in2 k g5 k fb2 DAC 2 D Latch DAC 1 CLK CLK D Latch k ff3 k r2 k g4 C 4 C 2 k r1 k ff1 k g1 C 3 64 Proc. of SPIE Vol. 5837 Downloaded From: https://www.spiedigitallibrary.org/conference-proceedings-of-spie on 24 Jan 2020 Terms of Use: https://www.spiedigitallibrary.org/terms-of-use • The 3-2 modulator shown in Fig.4(c) includes a first stage which consists of an integrator and a resonator. This topology allows the same optimum pole positioning as in the 2-2-1 modulator with one less stage. However, stability problems might arise that compromise the modulator performance. Table 1 shows the single-loop and inter-stage transfer functions ( ) for the different architectures in Fig.4 as a function of the loop filter coefficients . The expressions of , obtained from (8) and (11), are also shown. It is important to note that are found from an iterative simulation-based process that optimizes the first stage of the modulator in order to maximize while keeping stability. The outcome of the optimization process −entirely done in the CT domain −is summarized in Table 2.This table includes the values of loop filter coefficients, (implemented as transconductances) as well as the capacitances, , and resistances, obtained from the optimization process. The modulators in Fig.4 were simulated using SIMSIDES 13. Fig.5 shows the ideal output spectra of the modulators when clocked at . It can be observed the effect of the resonators poles distributed within the signal bandwidth. The impact on the in-band noise power is better appreciated in Fig.6 that represents the Signal-to-(Noise+Distortion) Ratio (SNDR) vs input amplitude. Note that, although both the 2-2-1 and 3-2 architectures have the same location of the zeroes of the NTF, the 3-2 modulator achieves a worse resolution. This is due to the fact that the optimization process applied to that architecture was more conservative as a consequence of the stability constrains imposed by the 3rd-order stage. In addition to the ideal performance described above, the effect of most critical limiting factors has been taken into account in the high-level design. Fig.7 shows the SNR loss caused by clock jitter error. Note that the 2-1-1-1 architecture seems to be less sensitive to this error than the other architectures. However, it is important to note that the ideal SNR of this modulator is lower than the others. Therefore, there is a higher component of quantization noise masking the effect of clock jitter. Two critical limiting factors in cascaded Σ∆Ms, and particularly in their CT implementation, are circuit tolerances and component mismatch. The first one can be controlled by using tuning of time constants 4,5 or digital calibration 6. However mismatch error still remains. In order to evaluate the impact of this error on the performance of the modulators in Fig.4, maximum values of mismatch were estimated for a 0.13 µm CMOS technology considering a Gm-C implementation. The Fij bij CLi bij SNR kiCi Ri Figure 5. Ideal output spectra of the cascaded CT Σ∆Ms in Fig.4: (a) 2-1-1-1. (b) 2-2-1. (c) 3-2. (a) (b) (c) f s240 MHz= Proc. of SPIE Vol. 5837 65 Downloaded From: https://www.spiedigitallibrary.org/conference-proceedings-of-spie on 24 Jan 2020 Terms of Use: https://www.spiedigitallibrary.org/terms-of-use Table 1: Transfer functions and cancellation logic functions of the modulators in Fig.4 Modulator Transfer functions Cancellation Logic 2-1-1-1 2-2-1 3-2 Cancellation Logic Coefficients 2-1-1-1 2-2-1 F14 b10 s3s2ωp 2 +() --------------------------- = F 24 1– Ts 3s3 ----------- =F34 1– Ts 2s2 ----------- = F44 1– Tss -------- = C L1z1 – n14 n+13z1 – n12z2 – n11z3 – n10z4 – +++()= C L2 1 6 ---z1–14z1–z2– –+()12 Tsωp ()cos z1– –z2– +()= C L3 1 2 ---z1–1z1– +()1z1– –()12 Tsωp ()cos z1– –z2– +()= C L41z1– –() 212 Tsωp ()cos z1– –z2– +()= F13 b10 ss 2ωp1 2 +()s2ωp2 2 +() ----------------------------------------------------- = F 23 b20 ss 2ωp2 2 +() ---------------------------- =F44 1– Tss -------- = C L1z1–n14 n+13z1 – n12z2 – n11z3–n10z4– +++()= C L2z1–n22 n21z1–n20z2– ++()12 Tsωp1 ()cos z1– –z2– +()= C L312 Tsωp1 ()cos z1– –z2– +()12 Tsωp2 ()cos z1– –z2– +( ) = F12 b11sb 10 + ss 2ωp1 2 +()s2ωp2 2 +() ----------------------------------------------------- = F 22 b21sb 20 + s2ωp2 2 + ----------------------- eTSs–kceTSs–2⁄ += C L1z2–n14 n+13z1 – n12z2 – n11z3 – n10z4 – +++()= C L212 Tsωp1 ()cos z1– –z2– +()1z1– –()⋅= 12 Tsωp2 ()kc –cos()z1– –1n21 kc2Tsωp2 ()cos–+()z2–n20 k+c ()z3– ++ () n 10 n14 b – 10 Ts 3ωp 5 ------------- Tsωp ()sin Tsωp –1 6 ---Tsωp () 3 +== n 11 n13 b–10 Ts 3ωp 5 ------------- [Tsωp () 32Tsωp ()cos– 3 ----------------------------------- 4Tsωp ()2TsωpTsωp ()1+cos()+sin–== n 12 b–10 Ts 3ωp 5 ------------- [Tsωp () 314 Tsωp ()cos– 3 ---------------------------------------6Tsωp ()sin 2Tsωp12 Tsωp ()cos+()]–+= n 10 n14 b – 10 ωp1 3ωp2 3ωp2 2ωp1 2 –() ------------------------------------------------ Tsωp1ωp2 3ωp1 3ωp2 –()ω p1 3Tsωp2 ()ω p2 3Tsωp1 ()sin–sin+[== n 11 n13 2b10 – ωp1 3ωp2 3ωp2 2ωp1 2 –() ------------------------------------------------ [Tsωp2ωp1 3ωp2 3ωp1 –()Tsωp1 () Tsωp2 ()cos+cos()()+== ωp2 3Tsωp1 ()1Tsωp2 ()cos+()ω p1 3Tsωp2 ()1Tsωp1 ()cos+()]sin–sin+ n 12 2b10 – ωp1 3ωp2 3ωp2 2ωp1 2 –() ------------------------------------------------ [Tsωp1ωp2 3ωp1 3ωp2 –()12 Tsωp1 ()Tsωp2 ()coscos+()+= ωp1 3Tsωp2 ()12 Tsωp1 ()cos+()ω p2 3Tsωp1 ()12 Tsωp2 ()cos+()]sin–sin+ n 20 n22 b20 – ωp2 3 ---------- Tsωp2Tsωp2 ()sin–[]== n21 2b20 – ωp2 3 --------------Tsωp2 ()Tsωp2Tsωp2 ()cos–sin[ ] = 66 Proc. of SPIE Vol. 5837 Downloaded From: https://www.spiedigitallibrary.org/conference-proceedings-of-spie on 24 Jan 2020 Terms of Use: https://www.spiedigitallibrary.org/terms-of-use results of this analysis are shown in Fig.8 where the SNR is represented as a function of the standard deviation of the transconductances ( ) and capacitances ( ). For each point of these surfaces, a MonteCarlo analysis of 150 simulations was carried out. The value of the SNR represented in the vertical axis of Fig.8 is obtained by 90% of the simulations for each case of and . Note that even in the worst-case mismatch, the resolution is above the specified ( ). Finally, the modulators in Fig.4 were high-level sized, i.e, the system-level specifications ( ) were mapped onto building-block specification using statistical optimization for design parameter selection, and behavioral simulation for evaluation. The results of this sizing process are summarized in Table 3 and Table 4 showing the maximum (minimum) values of the circuit error mechanisms that can be tolerated in order to fulfil the required modulator performance. As an illustration, Fig.9 shows the output spectra of the modulators taking into account the non-idealities listed in these tables. The effective resolution is and for the modulators in Fig.4(b) and (c), respectively. Table 1: Transfer functions and cancellation logic functions of the modulators in Fig.4.(Cont.) Mod. Cancellation Logic Coefficients 3-2 10 b–10 Tsωp1ωp2ωp2 2ωp1 2 –()ω p1 3Tsωp2 ()ω p2 3Tsωp1 ()sin–sin+() ωp1 3ωp2 3ωp2 2ωp1 2 –() -------------------------------------------------------------------------------------------------------------------------------------------------------------------- += b–11 ωp1 21Tsωp2 ()cos–()ω p2 21Tsωp1 ()cos–()–() ωp1 2ωp2 2ωp2 2ωp1 2 –() ---------------------------------------------------------------------------------------------------------------------------------- + 11 2b10 –Tsωp1ωp2ωp1 2ωp2 2 –()Tsωp1 ()Tsωp2 ()cos+cos()ω p2 3Tsωp1 ()1Tsωp2 ()cos+()sin+( ) ωp1 3ωp2 3ωp2 2ωp1 2 –() -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+= 2b10 ωp1 3Tsωp2 ()sin 1 Tsωp2 ()cos+()() ωp1 3ωp2 3ωp2 2ωp1 2 –() ----------------------------------------------------------------------------------------------------2b11 ωp2 2Tsωp2 ()cos 1 Tsωp1 ()cos–()ω p1 2Tsωp1 ()cos 1 Tsωp2 ()cos–( ) –( ωp1 2ωp2 2ωp2 2ωp1 2 –() ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -- + 12 2b10 –Tsωp1ωp2ωp2 2ωp1 2 –()12 Tsωp1 ()cos Tsωp2 ()cos+()ω p1 3Tsωp2 ()12 Tsωp1 ()cos+()sin+( ) ωp1 3ωp2 3ωp2 2ωp1 2 –() ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+= 2b10 ωp2 3Tsωp1 ()sin 1 2 Tsωp2 ()cos+()() ωp1 3ωp2 3ωp2 2ωp1 2 –() ------------------------------------------------------------------------------------------------------- 13 2b10 –Tsωp1ωp2ωp1 2ωp2 2 –()Tsωp1 ()Tsωp2 ()cos+cos()ω p2 3Tsωp1 ()1Tsωp2 ()cos+()sin+( ) ωp1 3ωp2 3ωp2 2ωp1 2 –() -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+= 2b10 ωp1 3Tsωp2 ()sin 1 Tsωp2 ()cos+()() ωp1 3ωp2 3ωp2 2ωp1 2 –() ----------------------------------------------------------------------------------------------------+2b11 ωp1 2Tsωp1 ()cos 1 Tsωp2 ()cos–()ω p2 2Tsωp2 ()cos 1 Tsωp1 ()cos–()–( ) ωp1 2ωp2 2ωp2 2ωp1 2 –() ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - 14 b–10 Tsωp1ωp2ωp2 2ωp1 2 –()ω p1 3Tsωp2 ()ω p2 3Tsωp1 ()sin–sin+() ωp1 3ωp2 3ωp2 2ωp1 2 –() -------------------------------------------------------------------------------------------------------------------------------------------------------------------- –= b 11 ωp2 21Tsωp1 ()cos–()ω p1 21Tsωp2 ()cos–()–() ωp1 2ωp2 2ωp2 2ωp1 2 –() - ------------------------------------------------------------------------------------------------------------------------------ – 2 0 b21 Tsωp2 ()sin ωp2 -------------------------------------b20 1Tsωp2 ()cos–() ωp2 2 ---------------------------------------------------- –= n21 b–21 Tsωp2 ()sin ωp2 ---------------------------------------- b20 1Tsωp2 ()cos–() ωp2 2 ---------------------------------------------------- –= σgm σC σgm σC72-dB 12-bit@20-MHz 13.4 bits≅13.2bits≅ Proc. of SPIE Vol. 5837 67 Downloaded From: https://www.spiedigitallibrary.org/conference-proceedings-of-spie on 24 Jan 2020 Terms of Use: https://www.spiedigitallibrary.org/terms-of-use