Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level

Measu emen o he Swi ching Ac i i y o CMOS Digi al Ci cui s a he Ga e Le el C. Baena, J. Juan-Chico, M.J. Bellido, P. Ruiz de Cla ijo, C.J. Jiménez and M. Valencia1 Ins i u o de Mic oelec ónica de Se illa-CNM / Uni e sidad de Se illa A da. Reina Me cedes s/n, 41012-Se illa, SPAIN Phone: +34-95-505-66-66; Fax: +34-95-505-66-86;[email p o ec ed] Abs ac . Accu a e es ima ion o swi ching ac i i y is e y impo an in digi al ci cui s. In his pape we p esen a compa ison be ween he e alua ion o he swi ching ac i i y calcula ed using logic (Ve ilog) and elec ical (HSPICE) simula o s. We also s udy how he a ia ion on he delay model (min, yp, max) and pa asi ic e ec s a ec he numbe o ansi ions in he ci cui . Resul s show a a iable and signi ican o e es ima ion o his measu emen using logic simula o s e en when including pos layou e ec s. Fu he mo e, we show he con ibu ion o gli ches o he o e all swi ching ac i i y, g i ing ha he ea men o gli ches in con en ional logic simula o s is he main cause o swi ching ac i i y o e es ima ion. 1 In oduc ion E alua ing he swi ching ac i i y in CMOS digi al ci cui s is a key poin o calcula e i s powe consump ion [1, 2]. In mixed-signal ci cui s, swi ching ac i i y o he digi al pa c ea es a swi ching noise ha is ans e ed o he analog pa [3, 4, 5]. Fu he mo e, as digi al ci cui s become as e and la ge , he in luence o gli ches in he swi ching ac- i i y g ows because he e a e mo e and mo e inpu collisions [6, 7, 8, 9]. Thus, e alu- a ion o swi ching ac i i y is oday a majo opic in he design p ocess o bo h pu e dig- i al, and mixed-signal in eg a ed ci cui s. Measu ing he swi ching ac i i y in a digi al ci cui conce ns h ee impo an ques ions: The i s one is e e ed o de e mining he ep esen a i e inpu s imuli ha mus be ob ained in o de o ge an accu a e es ima ion o he swi ching ac i i y. The second one is conce ned o he iming simula o . In iming simula ion o digi al ci cui s, s anda d ga e-le el logic simula o s (like Ve ilog [10]) a e able o handle e y la ge ci cui s and hey a e commonly used by ci cui designe s. O he wise, accu a e e alua ion o he swi ching ac i i y is possible by using elec ical simula o s (like HSPICE [11]), bu hese simula o s a e limi ed o a he small ci cui s, hey spend lo s o compu a ional esou ces, and hey a e no used in a ypical digi al design low. The hi d issue ocuses on he o igin o he logic ansi ions a he nodes o he ci cui . Inpu changes cause wo ypes o logic ansi ions: Fi s , p ope ope a ion gene a es 1.This wo k has been sponso ed by MCYT o Spain unde P ojec s TIC2000-1350 and TIC2001/2283 unc ional ansi ions and second, he gene a ion and p opaga ion o spu ious ansi o y signal pulses (gli ches) cause non- unc ional ansi ions. The basic me hod o es ima e he powe consump ion a logic le els consis s in ob aining he inal alue o i by summing up he powe con ibu ion each node has e e y ime i makes a ansi ion. So, i is necessa y o calcula e he o al numbe o ansi ions in he ci cui besides he use o a powe model o es ima e he consump ion a each node. Tools ha use his me hod ob ain an o e es ima ion in he powe consump ion. In o de o co ec his esul , new powe models a e p oposed in [12,13]. In his communica ion, we demons a e ha he swi ching ac i i y can be g ea ly o e es ima ed when calcula ed wi h con en ional logic simula o s like Ve ilog. This o e es ima ion is mainly due o an inaccu a e p opaga ion and elimina ion o gli ches, which happens ega dless he model used among hose p o ided by he ound y, o he inclusion o pos layou in o ma ion. This con ibu ion is o ganized as ollows: The me hod used o swi ching ac i i y compu a ion applied o ISCAS’85 benchma k ci cui s is summa ized in Sec ion 2. Simula ion esul s a e p esen ed and analysed in he sec ion 3. Finally, in sec ion 4, we d aw some conclusions on swi ching ac i i y e alua ion. 2 Swi ching Ac i i y Measu emen P ocedu e In his sec ion, we desc ibe a me hod o ob ain he swi ching ac i i y in a ci cui . To illus a e he me hod he ISCAS´85 benchma k ci cui s a e conside ed [14]. As said abo e, we compa e di e en measu es o swi ching ac i i y o a ci cui using wo kinds o simula o s, logic and elec ical. The p ocedu es a e e y simila in all o he cases and a scheme o hem a e p esen ed in Fig 1. We s a wi h he desc ip ion o he ci cui , p o ided by he ISCAS´85 benchma ks documen . This desc ip ion mus be ansla ed o ano he o ma sui able o he design en i onmen Design F ameWo k II (DFWII) in ou case [15]. To do his ansla ion, a so wa e pa se has been w i en using he PERL language [16]. The pa se akes he o iginal desc ip ion o he ci cui as supplied wi h he se o benchma ks, and p oduces he co esponding Ve ilog ne lis . The pa se also needs a simple mapping lib a y which assigns he igh cell o he cu en echnology o each logic ope a o . In ou case, ci cui s a e implemen ed in a CMOS 0.35 µm echnology. Once he ci cui desc ip ion is loaded in DFWII, we can gene a e HSPICE ne lis s in o de o do elec ical simula ion, o un a Ve ilog logic simula ion. A his poin , we ollow h ee di e en pa hs, bu be o e ha , we need o s udy which and how many ec o s o es mus be applied o ge an accu a e and ealis ic e alua ion o he swi ching ac i i y. Swi ching ac i i y inside a ci cui is highly inpu -pa e n dependen [17], hus, simula ion esul s a e di ec ly ela ed o he speci ic inpu pa e ns used. The wo main objec i es when selec ing a se o inpu pa e ns a e o gene a e an “a e age” swi ching ac i i y and o use a numbe o pa e ns ha is small enough in o de o limi he cos in compu a ional esou ces. The me hod desc ibed in he ollowing poin s accomplish bo h objec i es: • Fi s we un a Ve ilog simula ion on 1000 andom inpu pa e ns and ge he numbe o ansi ions in he whole ci cui . We ha e checked ha o such a numbe o andom pa e ns, simila swi ching ac i i y is ob ained (wi hin 2%) o any se o pa e ns, hus, he esul is an a e age measu e o he swi ching ac i i y. •Se e al 1000 andom ec o s simula ions a e un, and he numbe o ansi ions pe inpu ec o calcula ed. The mean alue o all measu emen s is aken as a s anda d alue o he ci cui 's swi ching ac i i y. • Then, we simula e he ci cui se e al imes using only 50 andom es ec o s in o de o ind a se o inpu pa e ns ha gene a ed a numbe o ansi ions pe s im- uli wi hin he 3% o he mean alue p e iously de e mined. Thus, hese 50 an- Desc ip ion o he benchma k ci cui pa se VERILOG ne lis o he ci cui DFWII HSPICE desc ip ion o he ci cui HSPICE VERILOG simula o s imuli N ans HSPICE N ans N ansZe o Figu e 1 . AÃschemeÃo à heÃme hodà o Ãswi chingÃac i i yÃcompu a ion Elec-Coun Log-Coun ∆1∆ = 0 ope a ion- o-cell mapping PWL gene a o SiliconEnsamble VERILOG simula o P&R N anspos lay ∆2 Log-Coun dom inpu pa e ns ep esen a gene ic inpu case and hey a e no exp essly se- lec ed o ge good esul s. These se o ec o s is hen used o compa e he swi ching ac i i y using logic and elec ical simula o s. In his way, we signi ican ly educe he compu a ional ime when unning elec ical simula ions on medium-la ge sized ci cui s. A e he selec ion o he s imuli we s a wi h he logic simula ion using he iming in o ma ion o each cell and he Ve ilog s anda d simula o , which uses an ine ial delay model. F om he esul s o his simula ion he global numbe o ansi ions (i.e., all o he nodes in he ci cui , N ans) is compu ed. To do ha , we ha e de eloped a p og am, Log-Coun , ha scans he Ve ilog ou pu and e u ns he numbe o logic ansi ions in each node, as well as he o al numbe o ansi ions. Addi ionally, his same p ocedu e is done using a ze o delay model o each ga e in he ci cui . The esul s o his simula ion p o ide a measu emen o he minimum swi ching ac i i y equi ed by he logic unc ionali y o he ci cui . No gli ch e ec s a e conside ed. We will no e his esul N ansZe o. Ano he p ocedu e conside ed o measu e he swi ching ac i i y is based on HSPICE simula ion. This esul is accu a e and will be used as a e e ence in ou compa ison. Fo his pu pose, we need o ansla e he same s imuli used be o e o piece-wise-linea unc ions o each inpu in he ci cui . Manually ansla ing he inpu ec o s o PWL o ma is no easible and his unc ionali y canno be ound in he design en i onmen . Hence, a gene al-pu pose p og am ha ansla es Ve ilog ec o s o SPICE PWL o ma has been de eloped o gene a e he app op ia e s imuli. These s imuli joined o he HSPICE ne lis a e all he necessa y da a o he HSPICE simula o . The iles gene a ed wi h hese simula ions a e he inpu o a so wa e p og am, Elec-Coun . This p og am is dedica ed o coun he numbe o imes each node in he ci cui c osses he Vdd/2 ol age. The inal esul is he swi ching ac i i y o he whole ci cui and is no ed as N ansHSPICE. Finally, we wan o conside he e ec s o ou ing on each node in o de o ha e a mo e ealis ic desc ip ion o he ci cui . To do ha , we used Silicon Ensemble ool and ollowing an au oma ic p ocess we ge he layou o he ci cui . F om his iew we ob ain a new se o delay alues o each node which include he wi e e ec s and new capaci ies alues. A e ha , we un ano he logic simula ion using his new in o ma ion and, ollowing he same p ocedu e we used be o e o he logic simula ion, we ob ain he numbe o logic ansi ions in each node, as well as he o al numbe o ansi ions and called i N anspos lay. 3Resul s In his sec ion, he whole me hod will be applied o nine o ISCAS’85 benchma k ci - cui s, in o de o compa e he swi ching ac i i y ob ained wi h logic simula ion includ- ing p e and pos layou agains he “in insic” swi ching ac i i y (ze o delay) and he “accu a e” alue ob ained wi h HSPICE. In Table 1, we lis he ci cui s selec ed and hei complexi y. Fo each one, he numbe o ansi ions o he simula ion o 50 es ec o s using Ve ilog conside ing ine ial delay model (minimum, ypical and maximum alues) o each ga e (N ansmin, N ans yp, N ansmax), and Ze o delay model (N ansZe o) is shown in Table 2. The esul o he simula ion unde he same condi ions using HSPICE (N ansHSPICE) is also included. As can be seen in he able, i we compa e minimum and maximum delays o he ypical, he di e ences in he o al numbe o ansi ions a e less han 1%. Fu he mo e, in some cases, he numbe o ansi ions using minimum alue o he delay is bigge han he esul using maximum delays bu in o he cases, i happens he opposi e. In Table 3, we ep esen he ela i e e o be ween N ans yp and N ansHSPICE (%e ∆1-Hsp) and he ela i e e o be ween N ansZe o and N ansHSPICE (%e Ze o- Hsp). As can be seen, in each example, he ela i e e o be ween N ans yp and N ansHSPICE is e y di e en . I a ies be ween 3% o c880 and 115% o c6288. Ano he impo an conclusion can be d awn om Table 3: when we compa e N ansZe o o N ansHSPICE, we obse e ha a high con ibu ion o he swi ching ac i i y is due o he gli ches gene a ed and p opaga ed inside he ci cui . In all o he cases, he con ibu ion o he gli ches is be ween 20% and 50%, excep o he case o c6288 o which his con ibu ion is e en g ea e han 77%. This is mainly due o he size o his ci cui and specially, he high numbe o le els (123, [13]) he ci cui has. Table 1: ISCAS85 benchma k ci cui s no. o inpu s no. o ou pu s o al ga es c432 36 7 160 c499 41 32 202 c880 60 26 383 c1355 41 32 546 c1908 33 25 880 c2670 233 140 1193 c3540 50 22 1669 c5315 178 123 2307 c6288 32 32 2416 c7552 207 108 3512 Table 2: Numbe o ansi ions using 50 inpu ec o s Ci cui N ansHSPICE N ansZe o N ansmin N ans yp N ansmax c432 4517 3637 4719 4735 4753 c499 6196 4868 6423 6417 6421 c880 11033 7707 11353 11337 11331 c1355 13960 10420 16318 16190 15990 c1908 25873 18465 32393 32411 32441 c2670 38655 26279 45095 44979 45029 c3540 52303 28799 61044 60920 60376 c5315 79803 48899 100589 100295 100327 c6288 194784 44378 421909 418815 416729 c7552 144535 76315 174682 174292 174062 Table 3: Rela i e e o s wi h espec o N ansHSPICE Ci cui %e ∆1-Hsp %e Ze o-Hsp c432 4.8 19.5 c499 3.5 21.4 c880 2.7 30 c1355 16 25.3 c1908 25.2 28.6 c2670 16.3 32 c3540 16.5 45 c5315 25.7 38.7 c6288 115 77.2 c7552 20.6 47.2 In o de o be mo e ealis ic doing logic simula ion, in he Table 4 we show he numbe o ansi ions ob ained a e conside ing he pa asi ic e ec s in each node using minimum, ypical and maximum delay o he ga e and we compa e hem o he esul s ob ained p e iously, be o e layou . Fo he h ee alues o he delay we can say ha he ela i e de ia ion be ween p e and pos layou a e no e y signi ican , less han 10% excep in he case o c2670 (11%) and he case o c6288 (13%). As we said o able 2, in some o he ci cui s he e o is posi i e and in o he examples is nega i e. A e analysing he esul s p esen ed in ables 2 and 4, we can conclude ha he pos -layou in o ma ion does no imp o es in gene al he compu a ion o he swi ching ac i i y when using logic simula o s. In able 5, we p esen he ela i e e o in he numbe o ansi ions a e a logic simula ion ha ing used pos layou ypical delays e sus HSPICE simula ion1. Gene ic conclusions a e simila we did when we compa ed he esul s wi h he p elayou logic simula ion (Table 3). The mo e simple ci cui s (c432, c499 and c880) ha e a ela i e e o is eally close o he HSPICE alue, bu in o he s he di e ence can each he 86% as he case o c6288. I is impo an o no ice ha he e a e cases in which he pos layou esul s a e u he o he eali y. In e ec , al hough c6288 dec eases i s ela i e e o om 115% (p elayou ) o 86% (pos layou ), in he case o c2670 he change is om 16.3% (p e) o 29.6% (pos ) making pos layou wo se han p elayou esul . Then, pos layou alues do no gua an ee an accu a e measu emen o he swi ching ac i i y. Table 4: Numbe o ansi ions p e-pos layou Ci c ui N ansmin N ans yp N ansmax p e pos % p epos % p epos % c432 4719 4499 4.7 4735 4505 4.8 4753 4511 5.1 c499 6423 5937 7.6 6417 6260 2.4 6421 5977 6.9 c880 11353 11495 -1.2 11337 11493 -0.1 11331 11485 -1.3 c1355 16318 15447 5.3 16190 15383 2.2 15990 15297 4.3 c1908 32393 32976 -1.8 32411 32880 -1.4 32441 32782 -1 c2670 45095 50122 -11.1 44979 50106 -11.4 45029 50072 -11.2 c3540 61044 61465 -0.7 60920 60979 -1 60376 61005 -1 c5315 100589 108587 -7.9 100295 108441 -8.1 100327 108015 -7.7 c6288 421909 365702 13.3 418815 362870 13.3 416729 361019 12.1 c7552 174682 166908 4.4 174292 166806 4.3 174062 166709 4.2 1. Un o una ely, o his echnology we ha en’ had a ailable he necessa y da a o un pos layou elec ical simula ion. The esul s ob ained in he di e en ables make us conclude ha Ve ilog simula ion is no an app op ia e way o measu e he swi ching ac i i y in a ci cui . Specially o wo main easons, he i s one because he ela i e e o can be e y high in some cases, in he case o he ci cui c6288, he esul is no alid a all; and he second idea o emphasise is he g ea a ia ion in he pe cen age among he di e en examples ha makes he esul s o he swi ching ac i i y no eliable in compa ison o HSPICE. F om hese esul s, i can be concluded ha he de ia ion in he powe consump ion es ima ion o a ci cui ob ained om logic simula o s is de i ed om he o e es ima ion in he swi ching ac i i y. So, he way o imp o e his esul in his kind o ools is ge ing a mo e accu a e swi ching ac i i y es ima ion h ough he use o new delay models wi h a be e ea men o gli ch gene a ion and p opaga ion [18]. Finally, in Table 6 we show he app oxima e o CPU ime spen in each simula ion. F om hese esul s, we can poin ou , he well known conclusion, ha elec ical simula o s a e limi ed o a he small ci cui s because hei cos is high in compu a ional esou ces and CPU ime. These kind o ools a e es ic ed o c i ical pa s o a digi al ci cui . Table 5: Rela i e e o s numbe o ansi ions pos layou s HSPICE Ci cui %e pos lay-Hsp c432 -0.2 c499 1 c880 4.2 c1355 10.2 c1908 27.1 c2670 29.6 c3540 16.6 c5315 35.9 c6288 86.3 c7552 15.4 4 Conclusions Some esul s o swi ching ac i i y es ima ion in digi al CMOS ci cui s when hey a e measu ed using s anda d simula o s has been p esen ed. In o de o be impa ial, bench- ma k ci cui s has been selec ed as ci cui s unde es , and andom medium leng h s im- uli ha e been applied. Gene ally, ac i i y due o gli ches (i.e., N ansZe o) has a ema kable con ibu ion ( o m 19% o c432 o 77% o c6288) o he o e all swi ching ac i i y. Thus, i can be emphasized he g ea impo ance o adequa ely handling he gli ch gene a ion and p opaga ion e ec s by iming simula o s. When he esul s o s anda d logic simula ion (Ve ilog) a e compa ed o accu a e da a (HSPICE) (i.e. N ans s. N ansHSPICE), i is obse ed ha he o e es ima ion o he N ans a ies app eciably, i.e. om 3% o c880 o 115% o c6288. Tha o e es ima ion pe sis s e en when minimum and maximum alues a e used and pos layou e ec s a e aking in o accoun . The g ea es a ia ion be ween min/max is 1% and be ween p e and pos layou is 13%. Bo h de ia ions a e much smalle han he a e age alue o he o e es ima ion. Hence, logic simula o s a e nei he p ecise no eliable a measu ing swi ching ac i i y. I is due o he ac ha hey a e no accu a e a simula ing gli ch p opaga ion. Table 6: Simula ion CPU ime CPU ime (s) VERILOG simula ion CPU ime (s) HSPICE simula ion c432 6.4 2714 c499 7.2 8087 c880 8.3 15240 c1355 8.3 28411 c1908 9.9 83989 c2670 16.7 260106 c3540 14.8 722935 c5315 24.1 1518849 c6288 34.2 836644 c7552 31.3 4577727