Effects of buffer insertion on the average/peak power ratio in CMOS VLSI digital circuits

E ec s o bu e inse ion on he a e age/peak powe a io in CMOS VLSI digi al ci cui s An onio J. Acos a, José M. Mo a, Ja ie Cas o, and Pila Pa a Ins i u o de Mic oelec ónica de Se illa-CNM-CSIC/Uni e sidad de Se illa, Spain ABSTRACT The bu e inse ion has been a mechanism widely used o inc ease he pe o mances o ad anced VLSI digi al ci cui s and sys ems. The d i e o epea e used o his pu pose has e ec on he iming cha ac e is ics on he signal on he wi e, as p opaga ion delay, signal in eg i y, ansi ion ime, among o he s. The powe conce ns ela ed o bu e ing ha e also ecei ed much a en ion, because o he low powe equi emen s o mode n in eg a ed sys ems. In he same way, he bu e inse ion has s ong impac on he eliabili y o synch onous sys ems, since he sui ed dis ibu ion o clock equi es educed o con olled clock-skew, being he bu e and wi e sizing, a c ucial aspec . In a di e en way, bu e inse ion has been also used o educe noise gene a ion, especially in hea ily loaded ne s, since he inclusion o bu e s help o desyn- ch onize signal ansi ions. Howe e , he inclusion o bu e s o in e e s o imp o e one o mo e o hese cha ac e is ics ha e o en nega i e e ec on ano he pa ame e s, as i happens in he a e age and peak o supply cu en . Mainly, he inclusion o a bu e o educe noise (peak powe ), ia desynch onizing ansi ions, could in oduce mo e dynamic con- sump ion, bu educing he sho -ci cui cu en because o he inc emen o signal slope. Thus, he a e age/peak cu en op imiza ion can be conside ed a design ade-o . In his pape , he mechanism o ob ain an a e age/peak powe op imi- za ion p ocedu e a e p esen ed. Selec ed examples show he easibili y o minimizing swi ching noise wi h negligible impac on a e age powe consump ion. Keywo ds: Swi ching noise gene a ion, submic on CMOS VLSI, mixed analog/digi al ci cui s, bu e inse ion, bu e epea e . 1. INTRODUCTION As he p og ess o deep sub-mic on p ocess echnology, he noise ma gins a e conside able educed whe eas he powe supply fluc ua ion is exace ba ed. The p esence o la ge cu en peaks on he powe and g ound lines is a se ious conce n o designe s o synch onous digi al ci cui s [1-5 ]. Al hough a lo o esea ch e o s ha e been made in he minimiza ion o o al powe consump ion o ci cui s [6-9], he e a e no many wo ks ha pay a en ion in minimiza ion o he peak cu - en o hem [10-13]. Peak cu en is a p ima y conce n in he design o powe dis ibu ion ne wo ks. In s a e-o - he-a VLSI sys ems, powe and g ound lines mus be o e -dimensioned in o de o accoun o la ge cu en peaks. Such peaks de e mine he maximum ol age d op and he p obabili y o ailu e due o elec o-mig a ion. Peak cu en s a e caused by simul aneous swi ching o highly loaded clock lines and by he signal p opaga ion h ough he sequen ial logic elemen s. So, o cu en ci cui s, he con ol o powe supply noise becomes e y impo an in e ms o ci cui pe o mance and eliabili y, demanding a educ ion o peak powe (cu en ) as well as powe consump ion [3]. The basic idea analyzed in his pape is he inclusion o bu e s (in e e s) o desynch onize signal ansi ions. This inclusion has e ec on bo h he signal slope and he p opaga ion delay, in such a way ha , o peak cu en we expec a educ ion because o signals do no a i e a he same ime o he load, and o a e age powe , he sho -ci cui cu en is expec ed o be educed due o he inc emen o signal slope, bu dynamic consump ion could be inc eased. As a conse- quence, a design ade-o can be ound o con e he bu e inse ion echnique in a good powe and noise sa ing ool. Ou con ibu ion does no p o ide a global and op imum solu ion o bu e inse ion bu aims o show he e ec s o bu e .Add ess o co espondence:IMSE-CNM, A da. Reina Me cedes s/n, 41012-Se illa, Spain. e-mail: [email p o ec ed] VLSI Ci cui s and Sys ems III, edi ed by Valen ín de A mas Sosa, Kam an Esh aghian, Felix B. Tobajas, P oc. o SPIE Vol. 6590, 659007, (2007) · 0277-786X/07/$18 · doi: 10.1117/12.724162 P oc. o SPIE Vol. 6590 659007-1 Downloaded F om: h p://p oceedings.spiedigi allib a y.o g/ on 11/08/2013 Te ms o Use: h p://spiedl.o g/ e ms inse ion on he a e age/peak powe a io. A cu en peak educ ion o a ound a 40% has been obse ed, wi hou any inc ease o powe consump ion. The o ganiza ion o he pape is as ollows: Sec ion 2 shows an in oduc ion o he CMOS in e e . Sec ion 3 will ocus on he low powe echniques, he e ec on swi ching noise and he me hodology used in he p ocess. In Sec ion 4 he p oposal is alida ed wi h HSPICE simula ions. Finally, Sec ion 5 includes he summa y o esul s and he conclu- sions. 2. CMOS INVERTER/REPEATER Much wo k has been epo ed in li e a u e abou CMOS in e e s. The CMOS in e e can be conside ed as he simples bu e o epea e in VLSI ci cui s. The h ee componen s o powe consump ion in a CMOS in e e a e dynamic, sho - ci cui and leakage. To oggle be ween logic ze o and logic one, capaci ies ha e o be discha ged and cha ged. The elec ic cu en ha flows du ing his p ocess causes a powe dissipa ion, his is dynamic powe consump ion. The cu en is dependen on he capaci i e ou pu load and he supply ol age. CMOS in e e consis o a pull-up (PMOS) and pull- down (NMOS), which ha e a fini e inpu all/ ise ime la ge han ze o. Du ing his sho ime in e al, when he PMOS and NMOS ansis o s a e conduc ing bo h, a cu en flows om powe o g ound. This cu en is called sho -ci cui -cu - en . Dynamic and sho -ci cui powe depend on swi ching ac i i y, so no powe should be los du ing idleness o a CMOS ci cui . Bu he exis ence o leakage cu en s shows ano he piece o eali y. These a e due mainly o cu en s flow- ing h ough he e e se biased diodes ha a e o med be ween he di usion egions and he subs a e, and flows h ough ansis o s ha a e non-conduc ing. Figu e 1 shows a CMOS bu e d i ing a load and i s equi alen symbolic ep esen a ion. In figu e 1a he inpu change om logic one o logic ze o ( all ansi ion), hen he load capaci ance is cha ged and dynamic cu en flows h ough he PMOS ansis o , while in his case h ough he NMOS ansis o only flows he sho -ci cui cu en (sho ci cui pa h be ween supply ails du ing swi ching). The e is also leakage cu en s due o leaking diodes and ansis o s, bu his cu en is no conside ed in his analysis. In figu e 1b he inpu change om logic ze o o logic one ( ise ansi- ion), hen he load capaci o is discha ged h ough NMOS (dynamic powe consump ion) and h ough PMOS only flows sho -ci cui cu en . The cha ge and discha ge o he load capaci ance equi es cu en om he supply sou ce. As ansi ion ime inc eases, he peak in supply cu en will be educed, since he same amoun o cha ge will be supplied du ing mo e ime. Some HSPICE esul s showing his dependence o a 0.13 m CMOS in e e a e depic ed in figu e 2. Resul s in able o figu e 2 show he inc emen in p opaga ion delay ( pLH), all ime ( all) and sho -ci cui cu en (IP) as inpu slope Vdd Vdd gnd gnd CLCL In 1=>0 all In 0=>1 ise sho -ci cui cu en sho -ci cui cu en Dynamic powe consump ion Dynamic powe consump ion F igu e 1. Powe consump ion in an in e e , a) in a all ansi ion, whe e cu en lows h ough PMOS o cha ge he load (dynamic powe consum ion), while h ough NMOS only lows sho -ci cui cu en . b) Rise ansi ion, whe e cu en lows h ough NMOS o discha ge he load (dynamic powe consum ion), while h ough PMOS only lows sho -ci cui cu en , and c) in e e equi alen symbolic ep esen a ion Load ci cui CL a) b) c) µ P oc. o SPIE Vol. 6590 659007-2 Downloaded F om: h p://p oceedings.spiedigi allib a y.o g/ on 11/08/2013 Te ms o Use: h p://spiedl.o g/ e ms 500u 400u 300u 200u 1 00u 0.00 —100u —200u 250P 500P ime ( S 750P 1.0n dec eases. In a smoo h way, a educ ion in he peak and an inc emen in he a e age o o al cu en (IN) is also no iced. Rela ed o a e age powe consump ion, sho -ci cui powe inc eases when ansi ion ime inc eases, due o NMOS and PMOS simul aneous ope a ion in linea and sa u a ion mode, espec i ely o he ou pu alling ansi ion. Managing hese e ec , a ade-o be ween peak cu en educ ion and a e age powe - iming pe o mances deg ada ion can be ound i a sui ed alue o inpu slope is conside ed. 3. LOW POWER/LOW SWITCHING NOISE AND METHODOLOGY Fi s , an in oduc ion o he impo ance o low powe consump ion echniques and hei e ec s on swi ching noise is p e- sen ed. Nex , he me hodology ollowed o ca y ou he simula ions o show he e ec s o bu e inse ion is explained. 3.1. Low powe consump ion and swi ching noise gene a ion When designe s ecognized powe consump ion as a design cons ain , simple models we e c ea ed. Powe pe MHz is s ill a commonly used ep esen a ion o a componen . Wi h a close look a powe dissipa ion, i becomes ob ious ha he subjec is no ha simple. Elec ic cu en is no cons an du ing ope a ion, and peak powe is an impo an conce n oo, because o he de ice would mal unc ion due o elec o-mig a ion and ol age d ops e en i he a e age powe consump- ion is low. So, peak powe is an impo an pa ame e o ake in o accoun in he simula ions as well as a e age powe . Reduc ion o he supply ol age has a quad a ic e ec on he educ ion o powe consump ion bu i also inc eases he delay. I u he mo e educes he swi ching noise gene a ed by single ga es, bu noise ma gins a e educed oo. To bal- ance he delay inc ease p oduced by he supply ol age educ ion, some au ho s sugges inc easing pa allelism o using pipeline s uc u es. Bo h echniques inc ease simul aneous ac i i y and noise. The e is a ade-o be ween low ol age- induced swi ching noise educ ion and he inc ease in simul aneous ac i i y ha has o be deal wi h. To sum up, i is no clea ha all low powe echniques necessa y educe swi ching noise. Some o hem could e en inc ease his (like powe -down modes). The educ ion o he ci cui ac i i y does no necessa ily educe maximum simul- aneous ac i i y by he same amoun , and his ques ion indeed equi es u he analysis [3]. VIN IP IN 1/0.12um 3.5/0.12um 3 F VOUT IN IP VIN VOUT ol s amps ise VIN pLH all VOUT a g IPmax INa g IN 36 ps 18 ps 20 ps 0.31 µA 546 µA 5.95 µA 72 ps 21 ps 26 ps 0.52 µA 387 µA 6.12 µA 180 ps 29 ps 44 ps 1.18 µA 261 µA 7.33 µA 360 ps 37 ps 72 ps 3.89 µA 208 µA 10.04 µA 720 ps 49 ps 129 ps 9.84 µA 176 µA 15.99 µA Figu e 2. In luence o he inpu slope on ou pu ol age and cu en wa e o ms o a CMOS in e e . P oc. o SPIE Vol. 6590 659007-3 Downloaded F om: h p://p oceedings.spiedigi allib a y.o g/ on 11/08/2013 Te ms o Use: h p://spiedl.o g/ e ms 3.2. Schema ic disposal To check he easibili y o bu e inse ion wi h ega d o swi ching noise, wo schema ic disposal ha e been p oposed. Fi s , a schema ic wi h in e e s ha simula e a ci cui and a hea y load is used (figu e 3a). In a UMC 0.13 m echnol- ogy, an in e e wi h PMOS wid h Wp=50 m ep esen a ci cui (no e ha in all cases Wn=Wp/2, and ansis o channel L=0.12 m), while an in e e wi h Wp=1000 m ep esen a hea y load. In his si ua ion we can measu e he o iginal ci cui cha ac e is ics, such as powe consump ion and peak powe supply cu en .Then we modi y he schema ic s uc- u e wi h he inclusion o a bu e (figu e 3b). As i is well known, when a signal a i es a a ci cui wi h an equi alen hea y load, a lo o powe is consumed and a la ge cu en peak is gene a ed. We can di ide he a i al o he signals o he ci cui load wi h he in oduc ion o a bu e in pa o he load, ob aining a desynch oniza ion in signal ansi ions. Then we can simula e he a e age cu en (dynamic and sho ci cui ) and peak cu en in bo h cases, wi h and wi hou bu e inse ion, in o de o compa e he alues. A educ ion in peak powe supply cu en and sho ci cui cu en a e expec ed due he bu e inse ion, while a penal y o pay is an inc ease in p opaga ion ime (delay). Fo he simula ion we use HSPICE and a pe iodic inpu signal “In” (T=10 ns, = =100 ps, Vdd=1.2 , whe e T is he pe iod, and a e he all and ise ime espec i ely, and Vdd is he powe supply). 4. SIMULATION RESULTS We ob ain measu emen s o a e age and peak cu en s o he all and ise ansi ion. We measu e he cu en h ough he PMOS and NMOS ansis o s in e e y signal ansi ion, and in his way we can iden i y he cu en due o sho ci cui and dynamic. In he a e age cu en we no ice ha due o dynamic powe , sho ci cui and o al a e age cu en pe an- si ion, o bo h cases, he one wi hou bu e inse ion and he one wi h bu e inse ion, as can be seen in able 1. We also pu in pa en heses, in he case wi h bu e inse ion, he a io be ween bo h cases, so we can see he imp o emen achie ed wi h ega d o he o iginal case wi hou bu e inse ion. As can be seen in able 1, he a e age cu en is educed when he bu e is inse ed, a ound a 20% in dynamic powe , and a 50% in he case o sho -ci cui cu en ( his is due o he highe signal slope wi h bu e inse ion, and as a consequence he sho ci cui cu en mus be less han in he case wi hou bu e inse ion). The o al powe consump ion is educed a ound a 25% since he dynamic powe is he dominan . In he case o peak powe supply cu en , we did measu emen s o peak a each ansi ion (“In” all and “In” ise) and we measu e on Vdd line, g ound line, and o al peak cu en (see able 2). Again we anno a e he a io be ween he case wi h and wi hou bu e inse ion, so ha we can see how he peak cu en is educed. Resul s show ha his educ- ion is a ound a 40%, which makes he bu e inse ion a good echnique o educe swi ching noise wi hou any inc ease in powe consump ion, e en a educ ion is ob ained as we saw in esul s in able 1, and hen, a good ade-o be ween bo h pa ame e s is achie ed. In figu e 4 you can see he cu en wa e o m in all and ise ansi ion o bo h, he case wi hou bu e inse ion and he case wi h bu e inse ion. In he cu en wa e o m in he case wi h bu e inse ion we no ice ha µ µ µµ i dd Vdd gnd 50 1000 50 50 50 500 500 a) b) Figu e 3. Schema ic o he wo con igu a ions, a) wi hou bu e inse ion, one in e e is he hea y load and he o he one in oduce he signal “In” o he load inpu , b) schema ic wi h bu e inse ion disposal which makes ha signals do no a i e a he same ime o he load. The numbe nex o each in e e co espond o Wp (being Wn=Wp/2, and L=0.12 m).µ In In T=10 ns = =100 ps Load Load bu e inse ion WpLp ⁄ WnLn ⁄ -------------------50 0.12⁄ 25 0.12⁄ -------------------- = P oc. o SPIE Vol. 6590 659007-4 Downloaded F om: h p://p oceedings.spiedigi allib a y.o g/ on 11/08/2013 Te ms o Use: h p://spiedl.o g/ e ms he e a e wo peaks o each ansi ion, due o he desynch oniza ion o he signal a i al, bu hese peaks a e mo e o less inside he cu en wa e o m ob ained wi hou bu e inse ion. Tha is why powe consump ion is no inc eased. And ega ding o p opaga ion ime, in he case wi hou bu e inse ion is 0.14 ns, and wi h bu e inse ion is 0.18 ns. So, as a penal y, an inc ease o a ound a 25% in delay occu wi h he in oduc ion o he bu e . Then, we will ocus on hese wo pa ame e s, peak cu en and delay, and we will look o a ade-o be ween hem. Table 1: A e age cu en (mA), in he cases wi hou and wi h bu e inse ion, o all and ise ime, dynamic and sho ci cui (SC) cu en , and o al cu en o each ansi ion Wi hou bu e inse ion Wi h bu e inse ion Fall Rise Fall Rise Dynamic SC Dynamic SC Dynamic SC Dynamic SC a g. cu en (mA) 2.02 0.912 1.693 0.584 1.637 (0.81) 0.435 (0.48) 1.461 (0.86) 0.246 (0.42) o al (mA) 2.932 2.277 2.072 (0.71) 1.707 (0.75) Table 2: Peak cu en (mA) in powe supply line, g ound line, and o al, o bo h cases, wi hou and wi h bu e inse ion. dd gnd o al Wi hou bu e Wi h bu e Wi hou bu e Wi h bu e Wi hou bu e Wi h bu e peak cu en (mA) - all 64.95 40.15 (0.62) 64.91 40.09 (0.62) 129.9 80.24 (0.62) peak cu en (mA) - ise 58.7 36.82 (0.63) 58.81 36.92 (0.63) 117.5 73.74 (0.63) 80.24 mA (wi h bu e inse ion) 73.74 mA (wi h bu e inse ion) 129.9 mA (wi hou bu e inse ion) 117.5 mA (wi hou bu e inse ion) “In” all “In” ise Figu e 4. HSPICE simula ion esul s o cu en wa e o m o all and ise ansi ion o inpu signal and o he wo con igu a ions, wi h wo in e e and wi h i e in e e s. P oc. o SPIE Vol. 6590 659007-5 Downloaded F om: h p://p oceedings.spiedigi allib a y.o g/ on 11/08/2013 Te ms o Use: h p://spiedl.o g/ e ms In o de o comple e he esul s, some modifica ions we e made on he dimensions o he in e e s (figu e 5) used as bu e inse ion [14-16], and we measu e he peak cu en in all and ise ansi ions, and also he p opaga ion ime. In able 3 a e he esul s o hese simula ions. As can be seen om he esul s, as he dimension o he bu e sizing is dec eased, he peak cu en is educed (figu e 6a), bu he p opaga ion delay is inc eased (figu e 6b). I we look o a ade-o be ween peak cu en and p opaga ion delay, we can see figu e 6c, whe e he noise-delay p oduc is ep esen ed. As can be seen, he lowes alues in bu e sizing gi e he wo s alues o he peak cu en and p opaga ion ime ade-o . 5. SUMMARY AND CONCLUSIONS In his pape , we ha e in oduced an e ficien way o educing peak cu en wi hou significan inc ease in o he pa ame- e s, such as a e age powe consump ion o p opaga ion delay. In ac , a educ ion in powe consump ion is also achie ed. This simple me hodology shows ha he bu e inse ion is a good op ion in e ms o low powe consump ion and swi ch- ing noise gene a ion. Measu emen s, using HSPICE simula ions, o bo h pa ame e s we e done in an UMC 0.13 m ech- nology, and also se e al bu e s wi h di e en sizes we e used in o de o ob ain he one wi h he bes noise-delay p oduc . Expe imen al esul s show a ound a 40% educ ion in peak cu en (swi ching noise) and a 30% educ ion in a e age powe consump ion, while he p opaga ion ime go wo se a ound a 20%. ACKNOWLEDGEMENTS This wo k has been sponso ed by he Spanish MEC TEC2004-01509 DOC and he Jun a de Andalucía TIC2006-635 P ojec s. 50 WpWp500 500 In Load bu e inse ion Bu e inse ion sizing: - case 1: Wp/Wn = 10/5 - case 2: Wp/Wn= 20/10 - case 3: Wp/Wn = 30/15 - case 4: Wp/Wn = 40/20 - case 5: Wp/Wn = 50/25 - case 6: Wp/Wn = 60/30 Figu e 5. Modi ica ions on bu e inse ion dimensions. The e a e six di e en s cases o bu e inse ion o simula ion, depending on he size o he bu e . We change he PMOS wid h Wpbe ween 10 m and 60 m, being he NMOS wid h Wn= Wp/2. Wi h hese new simula ions we can see which bu e dimension is he bes in e ms o peak cu en and delay. µµ Table 3: Peak cu en ( all and ise ansi ion), p opaga ion ime ( p), and noise-delay p oduc wi h modi ica ions on bu e inse ion wid hs. bu e Wp/Wn10/5 20/10 30/15 40/20 50/25 60/30 peak cu en (mA) - all 36 38.1 38.49 38.82 40.15 41.61 peak cu en (mA) - ise 31 32.8 33.56 34.31 36.82 39.25 p (ns) 0.40 0.26 0.22 0.19 0.18 0.17 noise-delay p oduc (pJ/ ) 14.4 9.9 8.5 7.4 7.2 7.1 µ P oc. o SPIE Vol. 6590 659007-6 Downloaded F om: h p://p oceedings.spiedigi allib a y.o g/ on 11/08/2013 Te ms o Use: h p://spiedl.o g/ e ms Poak cu T&I (JTl) a a P opagon ml. (ns) 4 (pJM 4 4 7 REFERENCES 1. X. A agonès; J. L. González and A. Rubio, “Analysis and Solu ions o Swi ching Noise Coupling in Mixed-signal ICs”, Kluwe Academic Publishe s, 1999 2. P. La sson, “di/d noise in CMOS in eg a ed ci cui s”, Analog In eg a ed Ci cui s and Signal P ocessing, 14-1/2, pp. 113-129, 1997 3. C. J. Alpe , A. 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