An ART1 microchip and its use in multi-ART1 systems

1184 IEEE TRANSACTIONS ON NEURAL NETWORKS, VOL. 8, NO. 5, SEPTEMBER 1997 An ART1 Mic ochip and I s Use in Mul i-ART1 Sys ems Te esa Se ano-Go a edona and Be nab´ e Lina es-Ba anco Abs ac —Recen ly, a eal- ime clus e ing mic ochip neu al en- gine based on he ART1 a chi ec u e has been epo ed. Such chip is able o clus e 100-b pa e ns in o up o 18 ca ego ies a a speed o 1.8  s pe pa e n. Howe e , ha chip ende ed an ex emely high silicon a ea consump ion o 1 cm 2 , and consequen ly an ex emely low yield o 6%. Redundan ci cui echniques can be in oduced o imp o e yield pe o mance a he cos o u he inc easing chip size. In his pape we p esen an imp o ed ART1 chip p o o ype based on a di e en app oach o implemen he mos a ea consuming ci cui elemen s o he i s p o o ype: an a ay o se e al housand cu en sou ces which ha e o ma ch wi hin a p ecision o a ound 1%. Such achie emen was possible a e a ca e ul ansis o misma ch cha ac e iza ion o he ab ica ion p ocess (ES2-1.0  m CMOS). A new p o o ype chip has been ab ica ed which can clus e 50-b inpu pa e ns in o up o en ca ego ies. The chip has 15 imes less a ea, shows a yield pe o mance o 98%, and p esen s he same p ecision and speed han he p e ious p o o ype. Due o i s highe obus ness mul ichip sys ems a e easily assembled. As a demons a ion we show esul s o a wo-chip ART1 sys em, and o an ARTMAP sys em made o wo ART1 chips and an ex a in e acing chip. Index Te ms—Adap i e esonance heo y, analog ci cui s, ana- log conpu e s, analog in eg a ed ci cui s, analog p ocessing ci - cui s, analog sys ems, ART neu al ne wo ks, ci cui s, clus e ing me hods, CMOS in eg a ed ci cui s, CMOS memo y in eg a ed ci cui s, in eg a ed ci cui design, la ge-scale in eg a ion, lea ning sys ems, neu al-ne wo k ha dwa e, nonlinea ci cui s, eal- ime sys ems. I. INTRODUCTION SINCE he in en ion o he ART1 a chi ec u e in 1987 [2] many high-le el neu al p ocessing sys ems ha e been de eloped [3] which a e based on he ART1 o mo e e ol ed bu simila a chi ec u es [4]–[8]. These high-le el neu al sys- ems ha e in e nal complex s uc u es, bu many imes hey a e based on a small numbe o ART-like building blocks. When hese high-le el neu al sys ems ha e o be used in eal-wo ld applica ions, po able equipmen s, obo s, indus ial con ol applica ions, e c., i is no always possible o ely on so wa e p og ams unning on expensi e wo ks a ions. In such cases i is manda o y o build a piece o ha dwa e ha ealizes physically he neu al p ocessing sys em. The a ail- abili y o ART-like modula chips would signi ican ly boos he p oli e a ion o ART-based neu al ha dwa e sys ems. Due o he inhe en in e nal hie a chy o ART-based neu al sys ems hei ha dwa e ealiza ion would be signi ican ly simpli ied i Manusc ip ecei ed June 25, 1996; e ised Ap il 2, 1997. The au ho s a e wi h Na ional Mic oelec onics Cen e (CNM), 41012 Se illa, Spain. Publishe I em Iden i ie S 1045-9227(97)05251-X. (a) (b) Fig. 1. (a) ART1 a chi ec u e diag am. (b) Algo i hmic ope a ion desc ip ion o VLSI- iendly as -lea ning ART1 sys em. obus and low-cos ART-like chip modules would be eadily a ailable. Al hough some p elimina y wo k was done o build ART- based ha dwa e p o o ypes [9], [10], i is no un il ecen ly ha a ully unc ional easonable size eal- ime clus e ing mic ochip neu al engine based on he ART1 a chi ec u e has been epo ed [1]. I is based on a sligh ly modi ied e sion o he ART1 algo i hm which was shown o p ese e all i s 1045–9227/97$10.00 1997 IEEE SERRANO-GOTARREDONA AND LINARES-BARRANCO: ART1 MICROCHIP AND ITS USE 1185 (a) (b) (c) Fig. 2. (a) Ci cui diag am o cu en -mode ART1 chip. (b) De ail o synapse S ij . (c) De ail o con olled cu en sou ce C i . o iginal compu a ional p ope ies [11], bu has a mo e VLSI- iendly algo i hmic s uc u e. The epo ed ART1 chip was able o clus e bina y inpu pa e ns o up o 100 pixels in o up o 18 di e en ca ego ies. The chip was able o classi y an inpu pa e n and lea n i s ele an cha ac e is ics by upda ing i s in e nal knowledge, all in less han 1.8 s. The chip in e nal ci cui a chi ec u e also allowed modula expansion o he clus e ing sys em. Assembling an a ay o hese chips would esul in ART1 sys ems able o clus e 100 pixel inpu pa e ns in o up o 18 ca ego ies. Un o una ely, he esul ing a ea consump ion (and cos ) o he chip was ex emely high (1 cm ), and consequen ly i s yield1 pe o mance was ex emely low (6%). Ne e heless, due o he aul - ole an na u e o he algo i hm, mos o he aul y chips s ill we e able o pe o m sa is ac o ily [1]. A s aigh o wa d solu ion o he yield p oblem is o include ex a edundan ci cui y in he chip oge he wi h some sel - es ing subsys ems ha would iden i y and disconnec aul y subcells. This me hod is used in ensi ely in la ge-a ea high- densi y comme cial DRAM chips. Howe e , his edundancy- based yield enhancemen echnique inc eases silicon a ea, equi es mo e p ocessing ci cui y and inc eases design e o and cos [13]. In his pape a new ART1 chip is p esen ed which sol es he yield p oblem using a di e en app oach: a ea 1Pe cen age o aul - ee chips o e o al numbe o ab ica ed chips. educ ion. A e ca e ul MOS ansis o elec ical pa ame e misma ch cha ac e iza ion o he echnological p ocess o be used, we we e able o iden i y he maximum chip a ea o which he pa ame e a ia ions would emain wi hin he necessa y limi s o p ese e he equi ed sys em ope a ion p ecision. We concluded ha o he ES2-1.0 m CMOS p ocess, o ansis o s o size m sp ead o e a die a ea o he o de o 2.5 2.5 mm, and o cu en le els a ound 10 A, he s anda d de ia ion o ansis o cu en misma ch is o he o de o %. Taking his in o accoun we we e able o design and ab ica e an ART1 chip capable o clus e ing 50-b inpu pa e ns in o up o en ca ego ies, wi h a yield pe o mance o 98%, and whose a ea is 15 imes less han ha o he i s p o o ype. The chip showed a e y obus beha io which enabled us o implemen some mul ichip ART1 sys ems. As an illus a ion we will show esul s o a wo-chip ART1 sys em and o a h ee-chip ARTMAP sys em. This pape is s uc u ed as ollows. In he nex sec ion he VLSI- iendly ART1 algo i hm employed is e iewed as well as he ci cui design ha maps i in o ha dwa e. In Sec ion III we show why he i s p o o ype has a e y high a ea consump- ion, how we pe o med a ca e ul echnology cu en misma ch cha ac e iza ion, and how we modi ied he ci cui o d as ically educe i s a ea, while main aining sys em p ecision and speed 1186 IEEE TRANSACTIONS ON NEURAL NETWORKS, VOL. 8, NO. 5, SEPTEMBER 1997 Fig. 3. T ee-like cu en -mi o s uc u e o gene a ing a la ge numbe o ma ched cu en sou ces. Fig. 4. Simpli ied diag am o misma ch cha ac e iza ion chip and expe i- men al se up. pe o mance. In Sec ion IV we will p o ide measu ed expe i- men al esul s o he new ART1 chip and o a wo-chip ART1 sys em. Sec ion V desc ibes how o assemble an ARTMAP sys em and p o ides measu ed expe imen al esul s as well. Finally, we conclude in Sec ion VI. II. VLSI-FRIENDLY ART1 ALGORITHM AND CIRCUIT IMPLEMENTATION An ART1 sys em is a sel -o ganizing neu al associa i e memo y capable o gene a ing in an unsupe ised way s able ecogni ion codes in esponse o a se ies o a bi a ily many, a bi a ily o de ed, and a bi a ily complex bina y inpu pa - e ns. As shown in Fig. 1(a) he ART1 a chi ec u e consis s o wo laye s. The bo om laye has nodes each o which ecei es he h bina y pixel o he ex e nal inpu pa e n . The op laye has nodes, each o which ep esen s a lea ned ca ego y o clus e o inpu pa e ns . Each laye node connec s o all laye nodes h ough bina y weigh s which can be ei he “0” o “1.” Each laye ca ego y is cha ac e ized by he se o weigh s ha connec s o i . E e y ime an inpu pa e n is p esen ed o he inpu laye an in e nal sea ch p ocess s a s which, when inished, esul s in ac i a ing a single laye ca ego y. This ca ego y is he one ha bes ep esen s he inpu pa e n acco ding o he alue o a igilance pa ame e which can be uned wi hin he in e al [0,1]. Fo small alues many pa e ns will be clus e ed in o he same ca ego y, while o high alues only e y simila pa e ns will be conside ed o belong o he same ca ego y. In he o iginal ART1 pape by Ca pen e and G ossbe g [2] he ope a ion o he sys em (a) (b) Fig. 5. Measu ed cu en o an a ay o MOS ansis o s wi h he same V GS and V DS ol ages ( o a nominal cu en o 10  A), sp ead o e a die a ea o 2.5 2 2.5 mm. (a) A ay o NMOS ansis o s and (b) a ay o PMOS ansis o s. was desc ibed by se s o nonlinea di e en ial equa ions. I was also men ioned ha he ope a ion o he sys em could be desc ibed by an algo i hmic low diag am which basically desc ibes he s eady s a e o he di e en ial equa ions. This algo i hmic desc ip ion was named as he as -Lea ning mode o ope a ion. Fig. 1(b) shows a modi ied e sion o he o iginal as -Lea ning ART1 ope a ion which has a highe po en ial o VLSI ci cui implemen a ions. I has been shown ha his algo i hm p ese es all he o iginal compu a ional p ope ies o an ART1 sys em [11]. The ope a ions o be pe o med a e he ollowing. 1) Rese all bina y weigh s . 2) Read a bina y inpu ec o I. 3) Compu e a se o analog “choice unc ions” o dis ances (1) o in ec o no a ion2 (2) 2Gi en a ec o a  ( a 1 ; 111 ;a N ) , he no a ion j a j ep esen s i s ` 1 no m j a j = N i =1 j a i j , and he in e sec ion ope a o be ween wo ec o s ep esen s he componen -wise logical AND ope a ion. SERRANO-GOTARREDONA AND LINARES-BARRANCO: ART1 MICROCHIP AND ITS USE 1187 Fig. 6. Measu ed cu en s o he L B a ay o he new ART1 chip p o o ype. 4) Selec he maximum among all .I is his maximum hen he h node is se o while all o he s a e se o . Hence, laye ac s as a winne - ake-all (WTA). 5) Check he igilance c i e ion: i he c i e ion is no sa is ied. In such case, o ce and e u n o S ep 4). O he wise, he c i e ion is sa is ied and he weigh s mus be upda ed o inco po a e he cha ac e is ics o pa e n in o ca ego y (3) o in ec o no a ion (4) The way his algo i hm can be implemen ed in a pa allel analog cu en -mode p ocessing ci cui is depic ed in Fig. 2(a). I consis s o a 10 50 a ay o synapses ,a1 50 a ay o con olled cu en sou ces , wo 1 10 a ays o uni y-gain cu en mi o s CMA , CMB ,a1 10 a ay o cu en compa a o s CC , a en-inpu WTA ci cui , wo uni y- gain cu en mi o s CMM and CMC, and an adjus able-gain (0 ) cu en mi o . Regis e s and he NOR ga e a e op ional. The ci cui diag am o a synapse is shown in Fig. 2(b). I con ains h ee cu en sou ces, a la ch, and a se o NMOS and PMOS ansis o s ac ing as swi ches. The s a e o he la ch is se o “1” by ac i a ing he RESET signal p io o ci cui ope a ion, o is se o “0” du ing ci cui ope a ion i , and simul aneously. The synapse gene a es wo cu en s, one o alue which is d ained om node in Fig. 2(a), and ano he o alue d ained om node . Nodes and a e sha ed by all synapses in he same ow. Consequen ly, he o al inpu cu en o mi o CMA and injec ed o inpu o he WTA is (5) No e ha cu en is p o ided by cu en mi o CMM o all nodes. Simila ly, he o al inpu cu en o each mi o CMB is (6) Fig. 2(c) shows he ci cui y o each cell . This cell d ains a cu en om node . The o al inpu cu en o he -gain mi o is hus . This cu en , ampli ied by a ac o , is eplica ed by mi o CMC and compa ed agains each cu en a each CC cu en compa a o . I (7) compa a o CC deac i a es he WTA inpu cu en ,by making he WTA con ol inpu . This way, cu en will no compe e in he WTA. Consequen ly, only he cu en s ha mee he igilance c i e ion (7) will compe e. The maximum among hese cu en s, le us call i , will make while he es become . Once a single winne is ac i e he signal can be ac i a ed making (8) An uncommi ed node is one ha has no ye been selec ed as a winne . Such nodes ha e hei ini ial weigh alues . Consequen ly, hei co esponding ow o synapses will gene a e he same cu en (9) 1188 IEEE TRANSACTIONS ON NEURAL NETWORKS, VOL. 8, NO. 5, SEPTEMBER 1997 Fig. 7. T aining sequence o a one-chip ART1 sys em wi h  =0 : 3 and  =1 : 1 . The unc ion o he shi egis e is o enable only one uncommi ed cell o compe e o he winne . E e y ime an uncommi ed cell wins, he shi egis e con en is shi ed one posi ion and he nex uncommi ed node is enabled o WTA compe i ion. The NOR ga e signals ha all nodes a e al eady commi ed. III. YIELD AND AREA OPTIMIZATION BY PROCESS MISMATCH CHARACTERIZATION F om a sys em p ecision poin o iew i is impo an o make all and cu en sou ces o ma ch wi hin he equi ed p ecision. When we designed ou i s ART1 p o o ype [1] we had no in o ma ion conce ning he long dis ance ma ching beha io o la ge a ays o cu en sou ces o he echnology we we e using. The e o e, we decided o use a mi o ee-like s uc u e o gene a e all cu en sou ces om wo ex e nal and cu en e e ences. This app oach is shown in Fig. 3. Each mul iple-ou pu cu en mi o had a he mos en ou pu s. Each cu en mi o was laid ou using common cen oid echniques, hus minimizing g adien - induced misma ch a he expense o inc easing die a ea. I each cu en mi o o s age in oduces a misma ch e o cha ac e ized by a s anda d de ia ion , he o al e o o a Fig. 8. T aining sequence o a wo-chip ART1 sys em wi h  =0 : 5 and  =2 . -s ages cascade is gi en by (10) The las s age is he mos nume ous and will occupy mos o he a ea. Pu e andom misma ch is in e sely p opo ional o ansis o a ea and cu en le el [12]. I we wan o keep a ound 1%, each s age mus ha e smalle e o s. In ou i s ART1 p o o ype chip [1] mos o he die a ea was spen by he h s age o common cen oid low-misma ch mul iple-ou pu s cu en mi o s. The esul ing ART1 chip had a die a ea o 1cm while ha ing a 100-node laye and an 18-node laye . The yield pe o mance o a mic ochip has he ollowing app oxima e dependence on die a ea : (11) whe e, o his echnology he es ima ed a e age de ec densi y is cm . Fo cm yield esul s o be a ound 6%.3Al hough mos o he aul y chips ende ed sa is ac o y clus e ing beha io [1] we decided o inc ease yield by educing die a ea. In o de o keep he sys em p ecision a ound 1% wi hou using a la ge-a ea-consuming ee-like mi o s uc u e a ca e ul long dis ance misma ch cha ac e iza ion o he echnological p ocess o be used was necessa y. A special pu pose chip was designed in he ES2-1.0 m CMOS echnology o es ima e he ma ching beha io o la ge ansis o a ays, o di e en ansis o sizes. The chip con- ains a ma ix o cells, each o which has se e al NMOS and PMOS ansis o s o se e al sizes, plus a ansis o selec ion ci cui y. Fig. 4 shows schema ically he chip oge he wi h an expe imen al se -up o measu e all ansis o s. In he chip all 3The chip pad ing a ea is no included in he yield compu a ion. SERRANO-GOTARREDONA AND LINARES-BARRANCO: ART1 MICROCHIP AND ITS USE 1189 Fig. 9. ARTMAP a chi ec u e. NMOS and PMOS ansis o s ha e hei sou ces connec ed o pin , all NMOS ansis o s ha e hei d ains connec ed o pin , all PMOS ansis o s ha e hei d ains connec ed o pin , all ansis o s ha e hei ga es sho -ci cui ed o hei sou ces, excep o one pai o NMOS and PMOS ansis o s. This pai has hei ga es connec ed o he ex e nal pin . A digi al bus and in e nal decoding ci cui y selec s one pai among all. By connec ing a cu e acing ins umen (in ou case, he HP4145) o pins and he selec ed NMOS ansis o can be accessed and cha ac e ized, while by using pins and he selec ed PMOS ansis o can be measu ed. This echnique has been used o cha ac e ize he misma ch beha io o se e al echnological p ocesses [14]. Fo ansis o s o size 10 m 10 m sp ead o e a chip a ea o 2.5 mm 2.5 mm, biased by he same ga e- o-sou ce and d ain- o-sou ce ol ages so ha hei nominal cu en was a ound 10 A, we measu ed he cu en sp eads depic ed in Fig. 5. Fig. 5(a) shows, as a unc ion o ansis o posi ion, he cu en measu ed o each ansis o o an NMOS a ay. Fig. 5(b) shows he same o a PMOS a ay. As can be seen, he su aces p esen a long dis ance g adien componen and a sho dis ance noise componen . Le us call he measu ed cu en s su ace . Fo his su ace we can compu e he bes i plane . Then, o each poin we can de ine (12) By compu ing he s anda d de ia ion o , we a e ex ac ing he noise componen o su ace . The g adien componen is de ined by plane . The maximum de ia ion due o he g adien componen is gi en by (13) On he o he hand, o he noise componen , 98% o he poin s emain wi hin he in e al. Consequen ly, le us de ine he maximum de ia ion due o he noise componen TABLE I CURRENT MISMATCH COMPONENTS FOR TRANSISTOR ARRAYS WITH 10  A NOMINAL CURRENT, 10  m 2 10  mTRANSISTOR SIZE, AND 2.5 2 2.5 mm DIE AREA FOR THE ES2-1.0  m CMOS PROCESS as . Le us now de ine (14) as he a io be ween noise componen and g adien componen con ibu ions. Table I shows hese a ios measu ed o NMOS and PMOS ansis o s o size 10 m 10 m, d i ing nominal cu en s o A and o di e en chips. Also shown in Table I a e he s anda d de ia ions o he noise componen , he maximum de ia ion o he g adien componen , and he o al s anda d de ia ion o ansis o cu en s , compu ed as (15) The cu en mi o ee-like s uc u e o Fig. 3 was in ended o supp ess he g adien componen o a 1 cm chip. The noise componen can only be educed by inc easing ansis o a ea [12]. Table I e eals ha o die a eas o 2.5 mm 2.5 mm, ansis o sizes o 10 m 10 m, and nominal cu en s o 10 A, he con ibu ion o noise componen is equal o highe han he g adien componen , while he s anda d de ia ion o cu en misma ch is kep below 1%. Consequen ly, o hese dimensions we can a oid he use o high a ea consuming 1190 IEEE TRANSACTIONS ON NEURAL NETWORKS, VOL. 8, NO. 5, SEPTEMBER 1997 Fig. 10. Flow diag am o ARTMAP aining mode ope a ion. ci cui s uc u es (like common cen oid mi o s a anged in a ee-like ashion) o elimina e he g adien componen , and di ec ly implemen a single cu en mi o wi h all he ou pu s needed. This is he app oach we used in he p esen ART1 chip p o o ype. This chip has a die a ea o 2.5 mm 2.2 mm, and con ains an a ay o 50 10 synapses, each synapse wi h wo and one cu en sou ces. The cu en sou ces ansis o s a e o size 10 m 10 m and d i e a nominal cu en o 10 A. Fig. 6 shows he measu ed cu en s o he a ay. Table II shows he measu ed alues o he misma ch componen s o he and cu en sou ces a ays o all ab ica ed chips. No e ha he o al cu en misma ch s anda d de ia ion is less han 1% o all chips. Due o he much smalle chip a ea i s ab ica ion cos is much less and i s yield pe o mance is signi ican ly highe : 98% by applying (11). In he nex sec ions single chip ope - a ion expe imen al esul s a e desc ibed as well as esul s o sys ems assembled wi h se e al ART1 chips. IV. EXPERIMENTAL RESULTS OF ART1 SYSTEMS All en ab ica ed chip samples we e ully ope a ional and o none o hem we we e able o de ec any aul in i s subci cui s. All sys em componen s could be isola ed and independen ly cha ac e ized. The ci cui pe o mances o he di e en subci cui s we e simila o hose o he i s p o o ype [1], and consequen ly hei cha ac e is ics will no be epea ed in his pape . He e we will only p o ide some illus a i e examples on sys em le el beha io . Al hough he chip is analog in na u e, i s inpu s and ou pu s a e digi al. The e o e, i is possible o es i s sys em le el beha io using a digi al es equipmen (in ou case, he HP82000). This equipmen applies digi al inpu ec o s ( ), SERRANO-GOTARREDONA AND LINARES-BARRANCO: ART1 MICROCHIP AND ITS USE 1191 TABLE II MEASURED MISMATCH COMPONENTS FOR THE FABRICATED ART1 CHIP PROTOTYPES eads digi al ou pu ec o s ( ), and eads he in e nal weigh s () a each p ocessing s ep. Th ee ex e nal e e ence cu en s need o be supplied o he chip: and . Cu en [see Fig. 2(a)] is needed o assu e ha all cu en s eaching he WTA a e posi i e. The ART1 sys em beha io is con olled by wo ex e nally adjus able pa ame e s, and . is he gain o a cu en mi o and is adjus ed h ough a digi al wo d applied ex e nally [1], while is con olled by app op ia ely se ing cu en s and . To es he sys em beha io i was ained wi h a se o en -b inpu pa e ns. Each pa e n ep esen s each o he en digi s om “0” o “9.” The las inpu pixel was always se o ze o and i is no shown in he igu es. The classi ica ion o he se o inpu pa e ns was epea ed o di e en alues o he igilance pa ame e and se e al alues o pa ame e . Fig. 7 shows he aining sequence o and . The i s column ep esen s he inpu pa e n applied o he sys em. The emaining en columns co espond o he weigh s s o ed in each ca ego y when he inpu pa e n has been classi ied and lea ned. The boxed ca ego y is he winning ca ego y a e he WTA compe i ion. In his case, lea ning sel -s abilizes a e wo inpu pa e n p esen a ions. Tha is, no modi ica ion o he winning ca ego y o he s o ed weigh s ake place in subsequen p esen a ions o he inpu pa e n sequence. As shown in Fig. 7, he sys em has clus e ed all en inpu pa e ns in o ou ca ego ies. A wo-chip ART1 sys em was assembled. In his case, he inpu pa e ns had bina y pixels. Fig. 8 depic s a aining sequence pe o med on his sys em. The sys em classi ies he en inpu pa e ns in o eigh ca ego ies a e a single p esen a ion o he inpu pa e n se . The sequence o Fig. 8 was ob ained o a igilance pa ame e o , and A, A). V. ASSEMBLING AN ARTMAP SYSTEM USING ART1 CHIP MODULES An ARTMAP sys em [7] consis s o wo ART1 subsys ems connec ed h ough an In e -ART module, as depic ed in Fig. 9. Le be an -dimensional inpu ec o o he i s ART1 subsys em ART1 , and an -dimensional one o he second ART1 subsys em. An Fig. 11. Flow diag am o he p edic ion ARTMAP ope a ion. ARTMAP sys em is a supe ised lea ning neu al ne wo k ha lea ns he co espondence be ween wo simul aneous inpu pa e ns and . Two modes o ope a ion can be dis inguished: •T aining Mode, du ing which pai s o inpu pa e ns () a e p o ided, and he ARTMAP sys em lea ns hei co espondence. •P edic ion Mode, du ing which only pa e ns a e p o ided o he i s ART1 subsys em, and ARTMAP p edic s he co esponding ART1 clus e . Fig. 10 illus a es he algo i hmic desc ip ion o ARTMAP ope a ion in aining mode [7]. A e eading wo inpu ec o s and each ART1 module selec s an winning node ( o ART1 and o ART1 ) ha mee hei igilance c i e ia. The in e -ART module, which is simply an a ay o bina y weigh s ini ially se o “1,” lea ns he co espondence be ween he ART1 winning ca ego y and he ART1 one by making i o he wise (16) o , in ec o no a ion (17) Howe e , i ART1 ca ego y and ART1 ca ego y become simul aneously ac i e and he In e -ART weigh has al eady been se o “0,” his means ha ART1 ca ego y has al eady been assigned o a di e en ART1 ca ego y. In his case ART1 igilance pa ame e is inc eased un il deac i a es and a di e en ART1 ca ego y is selec ed. Du ing he p edic ion mode o ope a ion subsys em ART1 does no ecei e any inpu s. Only subsys em ART1 e- cei es ex e nal inpu pa e ns and selec s a winning ca ego y .ART1 ou pu s, which a e he ou pu s o he comple e 1192 IEEE TRANSACTIONS ON NEURAL NETWORKS, VOL. 8, NO. 5, SEPTEMBER 1997 (a) (b) (c) Fig. 12. (a) ARTMAP ha dwa e assembly. (b) Diag am o In e -ART chip. (c) De ail o In e -ART chip cell. ARTMAP sys em, a e ac i a ed by he In e -ART module (18) o equi alen ly in ma ix no a ion (19) whe e Wis he weigh ma ix o he In e -ART module. Acco ding o he way he In e -ART weigh s a e se , o each ART1 ac i e ca ego y only one ART1 ca ego y will be chosen, bu an ART1 ca ego y can be ac i a ed by mo e han one ART1 clus e .4Fig. 11 shows he algo i hmic low diag am o he ARTMAP p edic ion mode ope a ion. An ARTMAP ha dwa e sys em can be assembled using wo ART1 chips and an ex a chip o he In e -ART module, as is shown in Fig. 12(a). The In e -ART chip, shown in Fig. 12(b), is simply an a ay o cells whose simpli ied schema ic is depic ed in Fig. 12(c). Each cell has a la ch which is se ini ially o “1” and changes o “0” i , and he LEARN signal is high. Ex a ansis o s, 4This is ue unless he inpu pa e n a ac i a es an uncommi ed ART1 a F 2 node (pa e n ais no ecognized as belonging o any ART1 a ca ego y). In his case, w jk =1 8 k , and all ART1 b F 2 nodes would be ac i a ed, implying ha he applied inpu pa e n is no ecognized as belonging o any o he lea ned ca ego ies. no shown in Fig. 12(c), a e also included o ead ou he weigh alues. Du ing aining mode he alue o weigh is used o con ol a digi al coun e ha inc emen s he alue o .I he coun e will inc ease i s alue un il he ART1 winning ca ego y changes and becomes “1.” A his momen he coun e s ops and i s con en ep esen s he app op ia e alue o . The sys em le el ope a ion o he ARTMAP ha dwa e sys em has also been es ed using he HP82000 digi al es equipmen . Fig. 13 shows a sys em aining sequence. The i s column, named , ep esen s he inpu pa e ns applied o he ART1 chip. The column named ep esen s he inpu pa e ns applied o he ART1 chip. The columns named and ep esen he s o ed weigh s in he ART1 and ART1 modules a e he classi ica ion and lea ning o each inpu pa e n pai . The boxed ca ego ies a e he ones ha emain ac i e a e he sea ch p ocess has inished, and hese a e he only ones ha a e upda ed wi h lea ning. Below each ART1 winning ca ego y he inal alue o he igilance pa ame e needed in he sea ch p ocess o choose his ca ego y is indica ed ( was inc eased in s eps o ). The las column shows he s o ed weigh s in he in e -ART module which ep esen he lea ned co espondence be ween he ART1 and ART1 ca ego ies (index is coded e ically om op o bo om, while index is coded ho izon ally om