HADES-1: A rapid prototyping environment based on advanced FPGA’s

HADES-I: A Rapid P o o yping En i onmen based on Ad anced FPGA's M.A. Agui e, J.N. Tombs, A. To alba and L.G. F anquelo Depa amen o de lngenie la Elec 6nica. Escuela Supe io de lngenie os de Se illa A da. Camino de los Descub imien os sin {agui eJon, o alba,leopoldo }@g e.esi.us.es Abs ac Rapid p o olyping o la ge digi al sys ems is becoming suppo ed wi b be use o new ad anced FPGA's. These FPGA's ean gi e mO e In o ma ion han unc ional simula ion and emula ion asks, due o hei inne inspec ion ea u es~ Tbis pape p esen s HADES-l, a new en i onmen o apid p o o yping and ha dwa e debugging. HADES-l is based on one FPGA o he VIRTEX amily, exploi ing he ad anced ea u es o he Selee Map po and a as link wi b be bos PC. 1. In oduc ion The imp o emen s in he a ea o mic oelec onics lead o sho e design cyeles and apidly ising complexi y o elec onics designs [I]. The e o e, de elope s a e o ced o e ine he sys em de elopmen p ocess o a oid a p oduc i i y gap. Rapid p o o yping is a echnique o suppo he sys em de elopmen . The enn apid p o o yping is de ined as a ype o p o o ypiog in which emphasis is placed 00 de eloping p o o ypes ea ly in he de elopmen p ocess o penni ea ly eedback and analysis. Thc adl ional de elopmen p ocess can be ep esen ed in he V-model ( ig I). The V-model enhanced by di e en le els o apid p o o yping is called VP-medel[2]. The idea o apid p o o yping is o skip ime in ensi e s eps o he de elopmen p ocess, and educe he ime o ge a i s unc ional p o o ype o he en i e sys em o a pa o he sys em. This p o o ype allows he alida ion o unc ionali y and ea ly pc onnance es s. Tile compa ison be ween di e en design al e na i es can be simpli ied and he e o e he concep oal alida ion ises. Compa ed o sys em simula ion, apid p o o yping o e s a es in he eal en i onmeo . Hence, eal- ime beha iou , in e e ences and in e aees wi h he eal en i onmen mus also be aken in o accoun . Th ee di e en le els can be dis inguished: • Concep o ien ed apid p olo yping ep esen s Ihe as con e sion o an execu able speci ica ion in o a unc ional p o o ype. This p o o ype se es 32 10 cla i y sys em goals and mus suppo a widesp ead ange o ha dwa e in e aces, The concep is o ienled a high le el. The suppo en i onmen is no speci ie and can be eused o o he p o o ypes. • A chi ec u e-o ien ed apid p o o yping, whe e he inal a chi ec u e o he sys em is ixed. Some componen s o he en i e sys em a e al eady de eloped o s anda d componen s a e used, whils o he pa s a e s i uede line de elopmen . • implemen a ion-o ien ed apid p olo yping is highly specialized and p ecise, he p o o ypes don' pe mi a widesp ead applicabili y. Usually i is onned om se e al inal elease componen s su ounded by new componen s. This app oach allows pe o mance analysis. Requi emen s Elici a i Sys Spacilica Module Design Sys em se Module Tes Fig 1. VP Diag am o Rapid P o olyping This pape desc ibes he solu ions o a cos e ec i e en i onmen ha suppo s p o o yping in he i s le el and second le el, named HADES-I (HA dwa e DEbugging Sys em). HADES-J is a amewo k 10 exploi he mos specialised cha ac e is ics o ed anced FPGA's. I eonsis s o a p o o ypmg boa d which is p esen ed as a digi al mic oelec onic in- sys em emula o [34]. The e a e h ee main lines ha ha e hecn ex ensi ely de eloped in HADES-I: • Fo la ge digi al sys em analysis, an ad anced FPGA is used wi h an ex ensi e use o i s high lexibili y, capaci y and pe o mance. • Fo some p ima y pe onnance analysis a sys em clock eon olle is in odueed. now on e e ed o as he C-FPGA). This C-FPGA wo ks as an in e aee be ween he hos PC, he Gene al pu pose Signals o Sys em In e ace Low Speed Con ol Signals Hos Con olle Figu e 2. O e iew o HADES-l Sys em • Fo human analysis pu pose a as and seeu e link wi h a hos PC akes con ol o he in e nal ea u es o he FPGA. This pape is o ganised as ollows. In Sec ion 2 he sys em ha dwa e is desc ibed. sec ion 3 and 4 show he in e ace wi h he in e nal pa s o he FPGA and he sys em clock con olle and, sec ion 5 he link wi h he hos PC is shown and see ion 6 he so wa e is desc ibed. 2. O e iew o HADES-l HADES-I consis s o a sys em o emula ing la ge digi al ci cui s using an ad anced FPGA. HADES-I has been de eloped using a VIRTEX de ice om XILINX, using any membe o his amily wi h a PQ240 oo p in . A pho o o HADES-I is shown in igu e 5. HADES has all he unc ional pins a ailable o being use in he sys em, wi hou any specialisa ion. In his way HADES can be adap ed o he equi emen s o any sys em. Figu e 2 shows a scheme o HADES-I and i s mos in e es ing ea u es. The co e o con ol and analysis ea u es is a second FPGA, one XC40lOXL also om XILINX, ( om 33 VIRTEX p og amming and debugging sys em, he p og ammable oscilla o and some s a ic Inpu /ou pu lines. The C-FPGA sol es he link be ween he hos PC and boa d. This pa will be desc ibed in de ail in see ion 5. In e nally, he C-FPGA is o ganised as a memo y map de iee wi h 32 memo y add esses. This C-FPGA uns wi h he buil -in clock o make i absolu ely independen o he on-boa d oscilla o . C- FPGA has a ixed p og am ha is downloaded du ing boa d s a -up ime. Howe e C-FPGA can be boo ed om ano he p og am due o he a ailabili y o a lash memo y. As clock sys em is an essen ial pa o a p o o ype we ha e in oduced a p og ammable oscilla o dc iec om Dallas, DS-1075. This p og anunable oscilla o can be in- un- hoe p og ammed o m he hos PC in un ime, wi hou any e ec on he Vi ex FPGA. 3. In e ace wi h VIRTEX The as es and simples way o in e ace wi h VIRTEX FPGA ( om now on he S-FPGA) is using he call SeJec Map me hod. Sclec Map is a pa allel po ha can be ead and w i en in an asynch onous p ocess, his is he as es con igu a ion me hod. F om he hos PC e e y by e o he con igu a ion ile i. downloaded h ough his po and e e y sequence o he con ol signals is gene a ed om an in e nal s a e machine. This s a e machine is also designed o be used o eading S-FPGA, allowing he con igu a ion and he in e nal s a e o he S-FPGA o be ans e ed and analysed in he hos PC. Some in e nal checks a e in oduced in he downloading p ocess o a oid po en ial damages inside he S-FPGA due o an almos impossible (no e "almos ") po en ial misma ch in he p og amming me hod. This equi es he s an-up p ocess o be well con olled. In he case o success ul p og anmling he nos ecei es a lag on he s a -up om he S-FPGA. 4. Sys em Clock Con olle One o he mos in e es ing ea u es o a Rapid P o o yping sys em is a ull con olled Sys em Clock. We ha e selec ed he well-known p og ammable equency clock gene a o om Dallas DS-I075. This oscilla o can gene a e equencies om a base equency cha ac e is ic o e e y DS-l075 model. This oscilla o can be p og ammed o equencies gi en by ,,,,,iN, wi h N=I, ... ,SI2, and bB ., 60, 66, 80 and 100MHz. O he comme cial p o o yping boa ds also use his oscilla o , bu o i s p og amming me hod i needs a powe -o plus powe -on sequence o he p og ammed p ocess. In HADES-l his p ocess has been in odueed au oma ically and con olled by he hos PC h ough he C-FPGA. The Sys em Clock can be s opped i needed, and om he PC he oscilla o ean be p og ammed, inspec ed and modi ied. C-FPGA I I ... ...! L----.Sys em C ock Figu e 3.P og ammablc Oscilla o Con ol Scheme Due o i s p og amming me hod, ha sha es he same wi e o p og amming and o he sys em clock, he clock is connec ed o he C-FPGA o gene a e he p og amming sequence {Dallas I-Wi e p openy)[9], The Powe -o plus powe -on p og amming sequence is only pe o med on DS-1075, as he C-FPGA con ols a se o analog swi ches ha allow he clock powe , and clock s opping as well. 5. Link wi h he hos PC The sys em p og amming and analysis p ocess can only be done using a as and obus link. HADES-l uses a well-known and common p o ocol called EPP[S]. EPP means Enhanced Pa allel Po and is desc ibed in he IEEE-1284 S anda d. EPP is a bi- di ec ional and ha dwa e con olled link ha ean achie e speeds be ween 500Kby es!s o 2Mby es!s ha is mo e han enough o ou pu pose. A Vinex 800 S-FPGA needs 576 Kby es o i s con igu a ion. Due o he con ol p ocess he con igu a ion would be pe onned in less han 2 seconds. The C-FPGA has a s a e machine ha p oduces a dialog be ween he PC and he boa d. I gene a es he neeessa y handshake signals and decouples add esses and da a in he designed memo y map. The s a e machine is depic ed in igu e 4, and i shows how i gene a es a single clock cycle ead, w i e and add ess pulse and he wai handshake signal. Figu e 4. EPP In e ace S a e Machine 6. HADES-l So wa e. The hos PC implemen s he human-machine in e ace. The design is de eloped using he s anda d desigu low using Xilinx ools. When he bi s ea u ile is p oduced, HADES-So wa e can ead his ile and download i in o he S-FPGA, du ing he con igu a ion p ocess. Also, he HADES-So wa e allows an easy con ol o he sys em elock equency, and he con igu a ion and eadback p ocesses om S- FPGA and panial econ ign a ion o he de ice. The so wa e is a Windows based ool and uses a low- le el con ol o he pa allel pan. Figu e 6 shows he dialog window o he Oscilla o and igu e 7 shows he S-FPGA p og amming dialog window, O he use ul ea u es ha ha e been included in lbe so wa e, such as inspec ion chans. These allow he obse a ion o he cu en con en o lbe in e nal 1ip- lops o he S-FPGA a e a cap u e command has been done, The inspec ion pmcess goes as ollows: I. Du ing he s anda d design low wo iles a e gene a ed: bi s eam ile.bi ) and e oss e e ence ( ile.ll), 2. The bi s eam gene a ion ha e o keep he p og amming po ac i e, 3. An speci.l in e nal eading allows a downloading o he in e n.l s a e om he FPGA. A new ile ( ile. CLB) is c ea ed. 4, F om lle ile.!l he exac place o he in o ma ion inside he ile.CLB and can be econs uc ed. The lc,1I only gi es he in o ma ion o hose nodes ha has no been eollapsed by he syn hesis p ocess. I a pa icula node is desi ed o be explici , adequa e cOl unands can be in oduced o p ese e hie a chy. Figu e 8 shows he window cha o he signal selec ion o an example design. Also shows he esul o an inspec ion p ocess uploaded om he boa d. Figu e S. HADES-l Boa d 7. Conclusions and Fu u e Wo k In his pape we ha e p esen ed a new boa d o la ge digi al ci cui emula ion and apid sys em p o o yping. I can un a. an in-sys em ci cui 35 emula o wi h many ha dwa e debugging eapabili ies. I also has ull con ol o he sys em eloek. Cu en ly, we' e unde de elopmen some new ea u es OT HADES-I: 1. De elopmen o a dedica ed po o he cons uc ion o a mul i-boa d sys em, o pa allel p ocessing p o o yping sys em. 2. Easy modi ica ion o he C-FPGA eon igu a ion. 3. HADES-2 will ha e one VIRTEX-E and one SPARTAN o he S-FPGA and he C-FPGA, espec i ely, 4. Run-Time pa ial econ igu a ion using JBITS classes The up o da e in o ma ion abou his p ojec is weekly main ained in he web si e: h p://woody.us.esl-agui elhades.h ml Figu e 6. P og ammable Oscilla n Dialog Window 7. Bibliog aphy [1] Dolla., A. Kanopoulos, N, «Reducing Time o Ma ke Th ough Rapind P o o yping". IEEECompu e , Feb, 1995. [2]A.Bu s , B.Spi ze , M.Wol , K.D. MUlle -Glasse . "On Code Gene a ion o Rapid P o o yping Unsing CDFI". OOPSLA'98, Vancou e , CA [3] Hu chings B., Nelson B. and Wi h lin M.L "Designing and Debugging Cus om Compu ing Applica ions". IEEE Design & Tes o Compu e s. Jan-Ma ch 2000. pp 20-28, [4] Koch A. "A Comp ehensi e P o o yping-Pla o m o Ha dwa e-So wa e Codesign". II" IEEE In e na ion Wn kshop on Rapid Sys em P o o yping. Pa is Jun-2000. pp7S-82. [5] Xilinx. Co, "The P og ammable Logic Da n Book". 2001. [6] Xess Co. XSV Boa d Vl.O Manual. Ma ch 2000 [7] Insigh . Vi lex-E Deyelopmen Ki . Aug-2000 [8] Peacock C. "In e lacing he enhanced pa allel po i". h p://www.sene .com.aw-coeacock. D .... 1997. [9] DS-I075 Da ashee . Figu e 7. S-FPGA P <>g amming Dialog Window Figu e 8 HADES-l Analisy. window 36