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EC-RASP: A new electrical energy static counter based on random signal processing conference topic: IC's for instrumentation and control

Toral, S. L.; Quero Reboul, José Manuel; García Franquelo, Leopoldo

Abstract

This paper concerns the design and development of electrical energy static counter, based on random pulse stream processing. Measurement proceeding, calibration and hardware implementation are checked in a prototype. As a result, a simple low cost measurement system has been obtained. The resulting measures have been compared with the ones obtained using a poly phase commercial analyser. A maximum 2% error has been achieved. This measurement proceeding is patent pending.

Full text

EC-RASP: A new Elec ical Ene gy S a ic Coun e based on Random Signal P ocessing S. To al, J. M. Que o and L. G. F anquelo Dp o. de Ingenie ´ıaElec ´ onica EscuelaSupe io de Ingenie os, A da. ReinaMe cedes s/n, Se illa–41012(SPAIN) Tel.: +34(9)5 45568 57 FAX: +34(9)5 45568 49 e–mail: [email p o ec ed] Con e ence Topic: IC’s o ins umen a ion and con ol Abs ac — Thispape conce ns hedesignandde elopmen o elec i- cal ene gy s a ic coun e , based on andom pulse s eam p ocessing. Measu emen p oceeding, calib a ionand ha dwa e implemen a ion a e checked in a p o o ype. As a esul , a simple low cos measu e- men sys em has been ob ained. The esul ing measu es ha e been compa ed wi h he ones ob ainedusing a poly phase comme cialan- alyze . A maximum 2% e o has been achie ed. This measu emen p oceedingis pa en pending. I. STATE OF ART His o ically he moni o ing o elec ical ene gy consump ion has been done by a ious ypes o induc ion wa me e s. The con en ional induc- ion wa me e , wi h o a ing disc and sha , con- ains a mechanical egis e (d i en by a gea on he sha ) which con inuously displays he o al accumula ed kilowa hou s consumed. Swi ch o clu ch ac i able mechanical demand and ime o use egis e s a e also used on hese me e s o dis- play demand and ime o use quan i ies. Elec onic egis e s a e in common use odaywi h induc ion ype wa me e , o accumula e pulse da a p opo ional o powe consump ion. This pulse da a is usually p o ided o he egis e om an op ical pick up o senso de ice which senses me e disc o a ion. These egis e s ha e he ad- an age ha hey can pe o m calcula ions on ac- cumula ed pulse da a and elec onically display much mo e in o ma ion han ispossiblewi h con- en ional mechanical ype egis e s. Nowadays, be e pe o mances a e equi ed and achie ed using s a ic coun e s. In his sense, elec- ic companiesha e oundi desi able omeasu e, in addi ion o o al kilowa -hou s, powe ac o , KVA, o eac i e ol ampe es. The measu emen o eac i e ol ampe es ypically has been accom- plished by using a second me e in conjunc ion wi h he con en ional kilowa -hou me e . F om he eac i e ol ampe esand he eal ol ampe es, quan i ies such as powe ac o and KVA can be calcula ed. This second me e o measu emen o eac i e ol ampe es is a wa me e connec ed wi hphaseshi ing ans o me sin he ol ageci - cui s. I is also in e es ing o p o ide he capabili y o digi ally con igu e he me e o measu e elec ic ene gy low in any o he di e en elec ical se - ices. Finally, i is desi able he possibili yo con- nec ing o ei he single phaseo poly phasepowe line sys ems. All hese cha ac e is ics should be accomplished by low cos and p ecise simple de- ices. P esen ly, elec onic coun e s and wa me e s use ei he analog ci cui s, o an analog o digi al con- e sion, ollowed by a pu e digi al p ocessing, basedonmic op ocesso sys ems,mic ocon olle sys emso digi al signal p ocesso (DSP). In he ollowing,se e alpa en sa edesc ibed. Eu- opean pa en No. 94110967.0[1] desc ibes a s a ic kWh me e ha makes use o an analog mul i- plie . F om he pulse-wid h modula ed ol age, a pulse-wid h/pulse-heigh modula ed signal, p o- po ional o he powe , is gene a ed, using analog connec o s. A equency signal is hus ob ained, which is passed h ough a di ide ci cui o he coun e o he kWh me e o de e mina ion o he ene gy ha has been consumed. Analog connec- o sha eade imen alp ope y, because heyp o- duce ex a ol age and cu en pulses in he signal o be measu ed. So, i is necessa y o compensa e his e ec , including an addi ional elec onic o sol e he p oblem. Besides, ypical disad an ages o analogelec onic de ices a e p esen : noisesen- si i eness, he mical sensi i eness, manu ac u e ole ances ::: Eu opean pa en No. 94203283.0 [1] uses a digi al signal p ocesso om he analog odigi al con e - sion o ol age and cu en . High numbe o pe - o mances a e achie ed a he expenses o a high cos de ice. In his pape a new s a ic ene gy coun e is p e- sen ed. Tha is, a coun e in which bo h cu en COMP |U| COMP INC/DEC I U |I| (1) (2) (3) (4) (6) (7) (8) (9) (10) (11) (12) (13) (15) (14) CAD CAD sign(I) 10 10 10 10 U II ld m e l m U d I e U e (5) sign(U) SENSOR NUMBER GENERATOR RANDOM COUNTER Figu e 1: De ailed block diag am and ol age change p ope ies o solid s a e elec- onic de ices, gene a ingpulseso equency p o- po ional o kWh. A i s , cu en and ol age a e sensed and digi al con e ed. S ochas ic pulse s eams a e p oduced by compa ing hese digi al numbe s wi h andom numbe s. The mul iplie is achie edbyasimpleANDga e. I sou pu isa an- dom pulse s eam ha ep esen s ins an aneous ac i e powe . Time in eg a ion is achie ed by a digi al coun e . I should be no iced ha s ochas- ic signal p ocessing is en i ely digi al. In con as wi h he las men ioned me hod ou digi al ci - cui sa eex emelysimpleandeasilyimplemen ed in low cos p og ammable de ices o ASICs, p e- se ing all he pe o mances desc ibed abo e. In he ollowing sec ions, i will be explained in de ail he design and de elopmen o he mea- su emen sys em. Fi s o all, i will be desc ibed he mono phase a chi ec u e o an ac i e ene gy coun e , ha has been implemen ed. P o o ype cha ac e is ics, calib a ion p oceeding and illus- a i e measu emen s will be shown nex . Finally, possible gene aliza ions and se e al conclusions will be wi hd awn. II. MONO PHASE ARCHITECTURE Figu e 2 is a simpli ied block diag am o he elec- onic me e : Rec i ied cu en and ol age signals a e digi al con e ed. S ochas ic pulse s eams a e p oduced by compa ing hesedigi al numbe s wi h andom numbe s. The mul iplie is achie ed by a simple AND ga e. Ins an aneous powe , coded in he andom pulse s eam a he ou pu o he AND ga e, is ime in eg a ed by a coun e ha inc easesodec easesi s alueacco ding o he mul iplying signal signs. Figu e 1 is a de ailed logic block diag am. Blocks (1) and (7), connec ed o he wi es o he U I 1 1 ADQUISITION ADQUISITION SIGNAL SIGNAL COUNTER up/down sign(U) sign(I) CONVERSION RANDOM PULSE RANDOM PULSE CONVERSION Figu e 2: Block diag am elec ici y ne wo k gene a es measu es U l and I l , p opo ional o ol age (U) and cu en (I). Blocks (2) and (9) ec i y bo h magni udes and (3) and (10) calcula e he sign. (4) and (11) make analog o digi al con e sion. (5) gene a es pai s o andom numbe oge andompulses eams U e e I e . AND ga e (13) gene a es he andom pulses s eam P e , which codes ins an aneous powe . This powe is in eg a ed by a coun e (14), which inc eases o dec eases acco ding o ol age and cu en signs. III. REALIZATION In igu e3apho og apho hep o o ypeisshown: The p o o ypeisa monophase s a icac i e ene gy coun e . This es boa d has been de eloped as a PC expansion boa d, in o de o debug ha dwa e easily. The es boa d includes a cu en in e ace wi h a i de ices, acco ding oDIN 43864. E e y 3600 W  s , i is gene a ed a cu en pulse g ea e han 30 ms. Measu emen s o bo h cu en and ol age a e aken om wo ansduce s, acco ding o igu e 4. Ac ually, ol age ansduce is no necessa y. I could be used a simple esis o ol age di ide . R 1 − + +12V -12V R 1 Vo = RVi 0 si Vi > 0 5 si Vi < 0 − + +12V -12V (x=i, ) Rx RR R − + +12V -12V Vi Vo Zene Ro se 5 V sign = Zene 4 V I ansduce To A/D inpu To FPGA inpu Figu e 5: Rec i ica ion ci cui Figu e 3: P o o ype Rec i ica ion ci cui is illus a ed in igu e 5. Once signal acquisi ion has been comple ed and digi al con e ed, da a is ed in o an Ac el FPGA, 1020B, 509 logic blocks o 547 [3] [4] (93 %) ( igu e 6). The FPGA has been designed wi h Ve ilog [5] and syn hesized wi h Cadence. Clock and sup- plies a e aken om PC. F equency clock is 8 MHz and sampling speed is 250 kHz. So, o each sam- ple, 32p oduc s o andom s eamsa e compu ed. In e nally, a andomnumbe gene a o anda32bi coun e , acco ding o igu e 1, is implemen ed in- side heFPGA.Thiscoun e canbeei he inc eased o dec eased, and is eadable om he PC. E e y ime he PC eads he less signi ican by e o he coun e , i ese s au oma ically. This unc ionali y has been included o debugging pu poses. IV. CALIBRATION I is necessa y o de ine a calib a ion p oceeding o he measu emen sys em acco ding o he scale limi s. Maximum ol age alue is 380 V, and max- imumcu en alue 7A. Tha means ha he alue (LA 25-NP) I in - + I ou Ri Vss (-12 V) Vcc (+12 V) M Cu en Vol age (LV 25-P) I ou Vss (-12 V) Vcc (+12 V) M R V in + ΗΤ − ΗΤ 25 k Ω Figu e 4: Schema ic diag am o ansduce connec ions . . . da a add esses clk ese Supplies +5, -5, +12, -12 FPGA MAXIM MAXIM 1020BNF MAX151 MAX151 Figu e 6: Tes boa d o a coun e uni will be: 1 pul se = V  I 8  106 W  s = 3 : 325  10 , 4 W  s Maximum coun ing ime is: T ime = 232 8  106 = 536 : 87 s = 8 : 947 min In wo FPGA’s pins, we ex ac ol age and cu - en andom pulse s eams, and, wi h a e y sim- ple ci cui , we eco e analog alue. This ci cui s consis so alow pass il e [6]. Calib a ion is done by wo po en iome e s ha modi y ol age and cu en gain. A DC powe supply has beenused o modi y ol - age be ween 0 and 100 V. Fo 100 V and 3.75 A, analog alue o cu en and ol age has been e- co e ed a he end o he chain, ha is, a he ou - pu o FPGA. Po en iome e s has been calib a ed so ha we ge he equi alen alue o 100 V and 3.75 A a he ou pu o he FPGA. Once calib a ion is inished, in e medium aluesa e aken ocheck calib a ion quali y. The esul is illus a ed in ig- u es 7 and 8. Y axis ep esen s in bo h cases he mean alue a he ou pu o he low pass il e , as men ioned abo e. 0.0 50.0 100.0 150.0 200.0 250.0 300.0 350.0 400.0 0.0 50.0 100.0 150.0 200.0 250.0 300.0 350.0 400.0 450.0 500.0 Vol age Mean alue (mV) Figu e 7: Vol age calib a ion 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 0.0 100.0 200.0 300.0 400.0 500.0 Cu en (A) Mean alue (mV) Figu e 8: Cu en calib a ion I can be obse ed ha we do no co e he whole ol age and cu en scale, because ou DC powe supplyisonlyup o100V.Besides, he eisano se incu en and ol agecalib a ion ha co esponds wi h one bi o he analog o digi al con e e . Con inuous powe measu emen e o , o 2s ime in e als, is de ailed in igu e 9. I has been ep e- sen ed ealpowe andexpe imen alpowe agains ol age. 0.0 100.0 200.0 300.0 400.0 0.0 100.0 200.0 300.0 400.0 ac ual powe measu ed powe Figu e 9: Con inuous powe measu emen e o V. MEASUREMENTS Measu emen sha e been done using a polyphase analyze Equa, based on a DSP echnique, as a e e ence de ice [8]. In e nally, Equa has a 0.2 % e o in measu emen o ol age and cu en . All o he magni udes a e compu ed om hese ones. Re e ence de ice uses he ollowing equa ion o compu e magni udes:  RMS ol age: V L iN = u u P P k = 1  2 L iN k P  RMS cu en : I L i = u u P P k = 1 i 2 L i k P  Ac i e powe : W L i = P P k = 1  L iN k  i L i k P  Reac i e powe : Q L i = P P k = 1  L iN k  i L i ( k , ) P  Powe ac o : PF L i = W L i p W 2 L i + Q 2 L i whe eP=128,i=1,2,3y  =P/4. I canbeno iced e- ac i epowe iscompu edusingold cu en alues ins ead o shi ing ins an aneous cu en alue. Expe imen al esul s a e sepa a ed om load:  Resis i e powe ac o : PF EC-RPS Equa E o 1 553.6 557 0.6 % 1 569.4 573.8 0.76 % 1 1088 1104 1.45 %  Capaci i e powe ac o : PF EC-RPS Equa E o 0.888 439.4 443 0.81 % 0.885 447.5 451 0.77 % 0.693 537 546 1.64 %  Induc i e powe ac o : PF EC-RPS Equa E o 0.994 536 538.7 0.50 % 0.994 556.8 560.6 0.67 % 0.979 1032 1045 1.24 % 0.979 513.5 519 1.05 % 0.979 524.8 530.6 1.09 % 0.923 900 916.3 1.7 % 0.910 86.81 86.13 0.78 % 0.834 81.88 82.3 0.51 % Measu es unde 2% e o a e achie ed. Acco d- ing o [7], his de ice would be a class 2 s a ic coun e . In u u es imp o emen s, lowe e o alues a e expec ed. We can men ion, al hough we ha e no included such esul s, he s abili y o measu emen s. The s anda d de ia ion o esul s is e y low. VI. GENERALIZATIONS F om he mono phase desc ip ion, i s poly phase e sioncanbeeasilydeduced. Acco ding o igu e 2, i s gene aliza ion is d awn in igu e 10: A mul iplexo is u ilized o combine he powe signal s eams o each phase. Each phase is se- quen ially selec ed, inc easing o dec easing he coun e acco ding o signs. The inal esul is a andom codi ica ion o n- h pa o ins an aneous poly phase powe a he mul iplexo ou pu , in e- g a ed in ime by he coun e . Reac i e powe measu emen is done by in eg a- ion o eac i e powe . In he mono phase a chi- ec u e, cu en is he same o he mono phase ci - cui , bu ol age shi s 90 deg ees espec ol age o mono phase ci cui ( igu e 12). U 1 90 o ADQUISITION ADQUISITION STOCHASTIC CONVERSION STOCHASTIC CONVERSION up/down CONTADOR I 1 U 1 ’ SHIFTED SIGNAL SIGNAL Figu e 12: Reac i e ene gy compu a ion: mono phase a chi ec u e Reac i epolyphaseene gywillbe hesumo eac- i e mono phase eac i e ene gy. Again, he same mul iplexo s a egy is applied ( igu e 11). VII. CONCLUSIONS This pape desc ibes he comple e p oceeding o design, de elopmen and calib a ion o an elec i- cal ene gy coun e based on andom signal p o- cessing. I has been de eloped a FPGA p o o- ype wi h sa is ac o y esul s. Abo e, i has been explained all he gene aliza ions o e his simple p o o ype,sowecanachie e simila u ili iesgi en by mode ns measu emen equipmen s, based on DSP. Bu , as a g ea di e ence wi h hese equip- men s,weha eimp o ed alowcos measu emen sys em. One o hese equipmen s ha e been used as a e e ence de ice. A maximum 2 % e o has been ob ained unde any load condi ion. As a u u e imp o e, we can hink in an ASIC implemen a ion. I would be posi i e a mixed echnology ASIC, including analog o digi al con- e e s. This way, i would be only necessa y a p e ious s age o signal acquisi ion be o e ASIC, educing manu ac u ing cos . This measu emen p oceeding is pa en pending [9]. REFERENCES [1] Lah i,Teu o. Eu opeanpa en applica ion,No. 94110967.0 . ENERMET OY. [2] W. R. Ge me , M. Negahban-Hagh, M. J. Ouel- le e, B. Whi e. Eu opean pa en applica ion, No. 94203283.0 . SILICON SYSTEMS, INC. [3] The AC T TM Family Mac o Lib a y Guide Ac- el Co po a ion. [4] Field P og ammable Ga e A ay. Applica ion Handbook . Texas Ins umen s. [5] Ve ilog-XL. Re e ence Manual, ol 1,2,3 . Ca- dence Design Sys ems,Inc. [6] J.G. O ega, C.L. Jane , J.M. Que o and L.G. F anquelo. “Analog o Digi al and Digi al o Analog Con e sion Based on S ochas ic Logic” . P oceedings IECON’95. [7] UNE-EN 61036:1994 . AENOR. [8] Elec ic Powe Quali y Analyze . TeamWa e. [9] J.M. Que o, S. To al, L.G. F anquelo. Elec ical ene gy s a ic coun e based on andom signal p ocessing. No. 9700600 . Se ille Uni e si y. SIGNAL ADQUISITION CONVERSION STOCHASTIC SIGNAL ADQUISITION SIGNAL ADQUISITION SIGNAL ADQUISITION SIGNAL ADQUISITION SIGNAL ADQUISITION SIGNAL ADQUISITION SIGNAL ADQUISITION SIGNAL ADQUISITION SIGNAL ADQUISITION SIGNAL ADQUISITION . . . . . . mux U I 1 1 U I 2 2 U n n COUNTER up/down I Figu e 10: poly phase sys em gene aliza ion SIGNAL ADQUISITION CONVERSION STOCHASTIC SIGNAL ADQUISITION SIGNAL ADQUISITION SIGNAL ADQUISITION SIGNAL ADQUISITION SIGNAL ADQUISITION SIGNAL ADQUISITION SIGNAL ADQUISITION SIGNAL ADQUISITION SIGNAL ADQUISITION SIGNAL ADQUISITION U 1 90 o 90 o 90 o . . . . . . mux I 1 I 2 I n COUNTER up/down 2 U 2 ’ U n ’ n UU U 1 ’ SHIFTED SHIFTED SHIFTED Figu e 11: Reac i e ene gy compu a ion: poly phase a chi ec u e