Contributions to Control of Electronic Power Converters

Proyecto Fin de Carrera Ingeniería de Telecomunicación Formato de Publicación de la Escuela Técnica Superior de Ingeniería Autor: F. Javier Payán Somet Tutor: Juan José Murillo Fuentes Dep. Teoría de la Señal y Comunicaciones Escuela Técnica Superior de Ingeniería Universidad de Sevilla Sevilla, 2013 Ph.D. Thesis Ingeniería Industrial Contributions to Control of Electronic Power Converters Author: Antonio Ventosa Cutillas Advisors: Francisco Gordillo Álvarez Francisco Salas Gómez Departamento de Ingeniería de Sistemas y Automática Escuela Técnica Superior de Ingeniería Universidad de Sevilla Sevilla, 2019 Ph.D. Thesis Ingeniería Industrial Contributions to Control of Electronic Power Converters Author: Antonio Ventosa Cutillas Advisors: Francisco Gordillo Álvarez Catedrático de Universidad Francisco Salas Gómez Profesor Titular de Universidad Departamento de Ingeniería de Sistemas y Automática Escuela Técnica Superior de Ingeniería Universidad de Sevilla 2019 Tesis Doctoral: Contributions to Control of Electronic Power Converters Autor: Antonio Ventosa Cutillas Directores: Francisco Gordillo Álvarez Francisco Salas Gómez El tribunal nombrado para juzgar la Tesis arriba indicada, compuesto por los siguientes doctores: Presidente: Vocales: Secretario: acuerdan otorgarle la calificación de: El Secretario del Tribunal Fecha: A María José A Nicolás A mi familia Contents Contents I Acronyms V Notation VII 1. Introduction 1 1.1. Multilevel Converters 2 1.2. DC-DC Converters 4 1.3. Objectives of the thesis 5 1.4. Thesis overview 6 1.5. List of publications 7 2. Preliminaries 9 2.1. Modulation Techniques 10 2.2. Dynamic Model of the System 15 2.2.1. Alternative Model of the System 19 2.3. Voltage Balance Problem 21 3. Three-Level Converter Control 23 3.1. Current and Power Controllers 25 3.1.1. Current Control 1 25 3.1.2. Current Control 2 26 3.1.3. Instantaneous Power Controller 27 3.2. Total DC-Link Voltage Controller 28 3.3. Voltage Balance Controller 29 3.4. Proposed approaches 32 I II Contents 3.4.1. ICM1 33 3.4.2. ICM2 34 3.4.3. Variant 3 37 3.5. Simulation Results 42 3.6. Experimental Results 50 3.7. Conclusions 55 4. Switched Affine Systems Modelling 57 4.1. Problem Formulation for Systems with High-Frequency Sampling Time 59 4.1.1. Delta Operator for High-Frequency Switching Signals 61 4.1.2. Control objectives 62 4.2. Usual Discrete-Time Formulation for Switched Affine Systems 63 4.2.1. Control Objectives 64 4.2.2. Application to a DC-DC Converter 65 5. Control of Switched Affine Systems 67 5.1. Control Laws for Systems with High-Frequency Sampling time 68 5.1.1. Lyapunov-Based Switching Control 68 5.1.2. Relaxed Switching Control 70 5.1.3. Optimisation Procedure 71 5.1.4. Numerical Validations 72 5.2. Control Laws for the Usual Discrete-Time Formulation of Switched Affine Systems 75 5.2.1. Basic Switching control 75 5.2.2. Robust controlled system 82 5.2.3. Numerical validations 85 5.3. Conclusions 92 6. Conclusions and Future Work 95 6.1. Thesis contributions and conclusions 95 6.2. Future work 97 Appendix A.Design and Construction of a Experimental Prototype Power Converter 99 A.1. Introduction 99 A.2. Schematic and Model 100 A.3. Design and Assembly 102 A.3.1. Components 102 A.3.2. Assembly 108 Contents III A.3.3. Future Work 110 List of Figures 111 List of Tables 115 Bibliography 117 Acronyms AC Alternative Current AF Active Filter CB-PWM Carrier Based Pulse Width Modulation CHB Cascade H-Brigde DC Direct Current DCC Diode Clamped Converter DPC Direct Power Control DTC Direct Torque Control DVR Dynamic Voltage Restorer FACTS Flexible AC Transmission Systems FC Flying Capacitor FS-MPC Finite States Model Predictive Control ICM Integrated Control and Modulation IGBT Insulated Gate Bipolar Transistor LMI Linear Matrix Inequality MPC Model Predictive Control NPC Neutral Point-Clamped NTV Nearest Three Vectors PI Proportional Integral PR Proportional Resonant PWM Pulse-Width Modulation STATCOM Static Compensator V VI Acronyms SHE-PWM Selective Harmonic Elimination Pulse Width Modulation SV-PWM Space Vector Pulse Width Modulation THD Total Harmonic Distortion UPFC Unified Power Quality Conditioner UPS Uninterruptible Power Supply VSVM Virtual Space Vector Modulation Notation |a|Absolute value of a ˙aTime derivative of a a V Estimated value of a A−1Inverse matrix of A CCapacitor [F] C(s)Continuous controller transfer function DLinear reduced model input vector diElement {i} in vector D det(A)Determinant of A eError G(s)Continuous transfer function IElectric current [A] KStatic gain LInductance [H] PActive power [W] QReactive power [Var] RElectrical resistance [Ω] TDDerivative time [s] TIIntegral time [s] tTime trRise time [s] VVoltage [V] VII VIII Notation xState vector yOutput vector abc abc coodinates αβγ αβγ coodinates τTime constant [s] ωFrequency [rad s-1] Subscripts and superscripts max maximum min minimum ref reference uinput 1 Introduction Sometimes it is the people no one can imagine anything of, who do the things no one can imagine. Alan Turing Contents 1.1. Multilevel Converters 2 1.2. DC-DC Converters 4 1.3. Objectives of the thesis 5 1.4. Thesis overview 6 1.5. List of publications 7 The thesis presented here aims to control electronic power converters. Specifically, the objective is to improve the control on the one hand of multilevel converters and on the other hand of DC-DC converters. In the case of multilevel converters, apart from the usual control objectives in this type of power converters [ 1 ], namely reduced total harmonic distortion (THD), achieve total DC-link voltage reference, reduced number of commutations or achieve active and reactive powers reference, this thesis focuses, as a first goal, on the voltage balance between capacitors. In the case of DC-DC converters, 1 2Chapter 1. Introduction the objective focuses on minimizing the output voltage error or chattering [ 2 ], that is the second goal of this thesis. With this intention, an alternative modeling to that performed in the first part of the thesis has been applied, modeling this type of power converters as switched affine systems. 1.1 Multilevel Converters The power converters most used nowadays are multilevel to the detriment of the classic two-level converters (2L). This is due to the fact that, for the same application, classic power converters topologies need high-voltage semiconductors and multilevel converter topologies can use medium-voltage devices. Multilevel topology offers some additional benefits, among which are an improved harmonic distortion for a given switching frequency, a lower overvoltage stress at cables and end windings of transformers/motors, a lower common-mode voltage and substantially lower semiconductor switching losses [ 3 ]. Multilevel voltage source converters also step in as an interesting alternative since they can achieve higher dynamic performance but without the voltage limit of the classic 2L [ 4 ]. Another advantage over two-level converters is that the peaks that occur in the switches when they open are much smaller, because these devices support less load due to be able to distribute it among more switches. Generally, a larger number of voltage levels, applied to a given grid-filter, achieves a lower harmonic range of the current, obtaining a high power quality in the converter’s AC-side. On the other hand, the increase in the number of levels increases the complexity of the control [5]. Multilevel converter technology started with the introduction of the multilevel stepped waveform concept with a series-connected H-bridge, which is also known as cascaded H-Bridge converter, in the late 1960s [ 6 ]. This same year, a Flying Capacitor topology was developed [ 7 ]. In the late 1970s, the diode-clamped converter (DCC) [ 8 ] was first introduced. The DCC concept evolved into the three-level NPC (3L-NPC) converter we know today as it was proposed in [ 9 ]. This converter was based on a modification of the classic two-level converter topology adding two new power semiconductors per phase. These three multilevel converter topologies, neutral-point-clamped (NPC), cascaded H- bridge (CHB) and flying-capacitor (FC), could be considered now as traditional multilevel topologies. NPC converter is one of the most used multilevel converter topologies. Operating in 2 Preliminaries What we know is a drop, what we don’t know is an ocean. Sir Isaac Newton Contents 2.1. Modulation Techniques 10 2.2. Dynamic Model of the System 15 2.2.1. Alternative Model of the System 19 2.3. Voltage Balance Problem 21 Th is chapter is devoted to present the three-level NPC converter as well as its dynamic model and to introduce the voltage balance problem. In the first section of this chapter, a review of the modulation techniques will be done, since they are directly related to the approaches that will be presented later. Some of the different types of topologies of multilevel converters are neutral-point- clamped (NPC), cascaded H-bridge (CHB) or flying-capacitor (FC) [ 29 , 4 , 30 ]. The NPC converter, which was proposed for the first time in [ 9 ], is one of the most used multilevel converter topologies. This is due to advantages like the lower current THD that reduces 9 10 Chapter 2. Preliminaries the filtering effort or the possibility to use IGBTs and diodes with breakdown voltages that are lower than the actual dc-link voltage, producing lower losses and increasing the efficiency [ 31 ]. The usual variables to control in NPC converters are active and reactive powers, currents, total dc-link voltage or number of commutations among others [ 1 ], but NPC converters present an additional objective apart from these usual control objectives that is the voltage balance between capacitors. Operating in rectifier mode, the voltage that drops across each capacitor must be balanced, otherwise it can result in poor output voltage quality, affecting the performance of the control or even damaging the semiconductor devices. Regarding the modelling, the model used in the first part of this thesis is an averaged model. The objective of this model in computing the averaged equations is to obtain a simpler model which retains the important properties of the original. The resulting equivalent circuit is much easier to solve, and allows insight to be gained into the important functional properties of the converter. Additionally, since averaged models are timeinvariant, they can be linearized about any desired operating point for small-signal analysis, i.e., obtaining local transfer functions. It is usual to work with averaged models when the switching frequency is much faster than the frequency range of the system. In that situation, the discrete values of the gating elements can be replaced by their averaged values in a switching period and can be considered as continuous signals [ 29 , 32 ]. This assumption yields that other signals, such as voltage, can also be considered as averaged signals, resulting that the system can be modeled as a continuous system. 2.1 Modulation Techniques In order to implement the control laws obtained with the models commented before, a discretization stage, usually called modulation, needs to be accomplished [ 33 ]. Modulation plays an important role in the overall system performance since properties such as number of commutations and harmonic distortion of currents and voltages are affected by the way modulation is carried out. It should be remembered that increasing the number of commutations also increases losses. Modulation methods can be classified in three main groups [34]: • Pseudo-modulation [ 35 ]: In this method, a simple comparison of the reference voltage is used. One way to do this is to choose the voltage level closest to the desired voltage. The same principle can be used in the nearest vector control technique, applying the nearest space vector to the reference vector. The simplest 2.1 Modulation Techniques 11 form of pseudomodulation is the square-wave modulation, comparing the reference voltage with zero. •Closed-loop control methods with implicit modulator [36, 37, 38]: In this method, control techniques are used that directly generate the switching signals of the converter switches. Among the techniques used in this method are the Hysteresis Current Control, the Direct Torque Control (DTC), the Direct Power Control (DPC) and the Finite-States Model-Predictive Control (FS-MPC). • Pulse width modulation (PWM) [ 39 , 40 ]: As mentioned before, the three approaches presented in this thesis are closely related to PWM modulation techniques. Hence, this section will be devoted to explain this type of modulation. There are two main methods of modulation by PWM that use high switching frequency [ 29 ]: the carrier-based modulation (CB-PWM) and the space vector modulation (SV-PWM). Figure 2.1 Carrier signals: Trailing edge (left), triangular (center) and leading edge (right). In carrier-based modulation, the activation signals of the switches are obtained by comparing the amplitudes of a high-frequency signal called carrier and a lowfrequency signal called modulator. The most common forms of the carrier signal are the triangular, the leading edge (when the mounting slope is infinite) and the trailing edge (when descendant slope is infinite) [ 41 ]. A graph with carrier signals 12 Chapter 2. Preliminaries can be observed in Fig. 2.1. On the other hand, the modulator or reference signal can have different forms such as sinusoidal or discontinuous or forms characteristic of the method used to obtain it, such as Carrier based Space Vector Pulse Width Modulation (CB-SVPWM) or injection of the third harmonic among others [42]. In Fig.2.2 it is possible to observe the operation of the modulation by PWM. If the value of the reference signal (triangle signal) is more than the value of the modulation waveform (sinusoidal signal), the resultant PWM signal is a high signal, Otherwise, the resultant waveform is in the low state. Figure 2.2 Output voltage generated by PWM. An important characteristic in modulation techniques, which affects the PWM modulation, is the level of DC bus utilization. This can be measured by the modulation index, which is defined as the amplitude of the modulating signal, normalized with respect to the maximum amplitude of the carrier: M=A vdc/2(2.1) where A is the maximum amplitude of the carrier signal and ( vdc ) is the total dc-link voltage. If this index is less than or equal to one, the peak of the modulating signal is less than or equal to the peak of the carrier signal and the converter will be in the linear mode 2.1 Modulation Techniques 13 of operation. On the other hand, if the opposite occurs and the index is greater than one, the converter will be in a non-linear mode of operation called overmodulation. In this mode, the intersections between carrier and modulator disappear and the pulses generated in the comparison remain at a single level. The output voltage does not reach to equal the reference value, generating non-linear relationships between the amplitudes and the phase angles of the reference signal and the output signal of the inverter. v α PON v β PNN PNO PNP ONP NNP NOP NPP NPO NPN OPN PPN PPO OON POO ONN POP ONO OOP NNO OPP NOO OPO NON PPP OOO NNN Figure 2.3 Space Vector hexagon. In the Space Vector Modulation (SV-PWM), the Clarke transformation is applied on the three-phase set of modulating signals to create a space vector reference in αβ coordinates. In balanced systems, this vector has constant amplitude and rotates in the αβ plane following a circular path. In this αβ plane, the different switching states of the converter can be represented by vectors that give rise to a so-called space vector hexagon represented in Fig. 2.3. The reference vector is obtained by lineal combination of this vectors. The way to obtain this combination can be reduced to two techniques [ 43 ]. Although there are numerous techniques that use space vector, most of them use variations of these two. The first one is called Nearest Three Vectors (NTV). In this technique, the hexagon is divided into six sectors formed by four triangles each in a three-level converter. Once the sector and the triangle where the reference vector is located are identified, the three closest vectors are 14 Chapter 2. Preliminaries chosen and the switching states are computed. In the second technique, the hexagon is decomposed into six smaller hexagons. In this way, each hexagon is considered as the hexagon of a two-level converter. The new reference vector is calculated based on the original vector and the sector where it is located within this new hexagon is calculated. The switching states are computed based on the two closest vectors in each sector. In Fig. 2.4 it is possible to observe the space vector hexagon divided in the six small hexagons. Figure 2.4 Simplification of the three-level Space Vector hexagon diagram. 2.2 Dynamic Model of the System 15 2.2 Dynamic Model of the System The three-level converter circuit is shown in Fig. 2.5. In this figure, the converter is in rectifier mode, where the electrical power grid is considered as a three-phase voltage source, and where the phase voltages are represented by vsa,vsb and vsc . The converter is connected to the grid through an inductive filter where inductances have the same value L . On the dc-link side, capacitors have the same value C and their voltages are denoted by vc1 and vc2 . Connected to the converter terminals there is a resistive load R . The total dc-link voltage is defined as vdc =vc1+vc2. Figure 2.5 Squematic diagram of the three-phase three-level NPC rectifier. The switches Si j , are Insulated Gate Bipolar Transistors (IGBTs), where i indicates each of the three phases and j indicates the switch number. Si j represents the inverted signal of Si j . Due to this configuration, there are only some allowed combinations of the states of each switch, the rest are destructive or potentially destructive. Table 2.1 and Fig. 2.6 shows the permitted combinations of the switches for phase a and represents the current flow associated with each state, respectively. The phases b and c have the same possible combinations. The signals that control the positions of the switches are represented by the control signals δ∗ a , δ∗ b and δ∗ c , as can be seen in that table. As mentioned before, the circuit has been modeled as an averaged model, so that these control signals can be expressed as averaged duty cycles ( da , db and dc ) for each level in each phase. In this way, the value of the signals varies from zero to one as a percentage of the time the switches have to be 16 Chapter 2. Preliminaries open or closed. Thus, if the duty of phase a at positive level ( dap ) has a value of 0.4, the switches of leg a will be in the position represented by figure 2.6a during 40 percent of the sampling time. Taking this into account, the circuit model is formulated in terms of nine duty cycle variables (three duty cycles per phase) instead of just three (one duty cycle per phase) as in the traditional model, where the duty cycles only takes three possible values (-1, 0, 1) to assign the positions of the switches. It is shown that the formulation used in this thesis allows to explicitly consider, in the control design stage, the extra degree of freedom associated with the injection of homopolar component. The increase in the number of variables does not make the design significantly more difficult since, with an appropriate change of variables, the dc-link voltage and active and reactive power control problems can be formulated with the same facility of other usual approaches. Table 2.1 Switching states of the three-level NPC converter. S1 aS2 aS1 aS2 avaδ∗ aFigure Closed Closed Open Open vc11 2.6a Open Closed Closed Open 0 0 2.6b Open Open Closed Closed −vc2-1 2.6c o n p (a) Positive level. o n p (b) Zero level. o n p (c) Negative level. Figure 2.6 Switching states for phase a. 2.2 Dynamic Model of the System 17 The model considered in this thesis is described in [ 44 ], which is based on a model presented in [45], assuming a symmetric and balanced system without losses. Using abc coordinates: Ldia dt =vsa +−1 3(dap +dan)+ 1 6(dbp +dbn)+ 1 6(dcp +dcn)vdc +−1 3(dap −dan)+ 1 6(dbp −dbn)+ 1 6(dcp −dcn)vd(2.2) Ldib dt =vsb +1 6(dap +dan)−1 3(dbp +dbn)+ 1 6(dcp +dcn)vdc +1 6(dap −dan)−1 3(dbp −dbn)+ 1 6(dcp −dcn)vd(2.3) Ldic dt =vsc +1 6(dap +dan)+ 1 6(dbp +dbn)−1 3(dcp +dcn)vdc +1 6(dap −dan)+ 1 6(dbp −dbn)−1 3(dcp −dcn)vd(2.4) Cdvdc dt = (dap −dan)ia+(dbp −dbn)ib+(dcp −dcn)ic−2vdc R(2.5) Cdvd dt = (dap +dan)ia+(dbp +dbn)ib+(dcp +dcn)ic, (2.6) where vd is the dc-link capacitor voltage difference defined by vd=vc1−vc2 and the control inputs dap,dan,dbp,dbn,dcp and dcn are the duty ratios in abc coordinates. It should be remarked that the duty ratios in abc coordinates are subject to the following constraints dap +dao +dan = 1 (2.7) dbp +dbo +dbn = 1 (2.8) dcp +dco +dcn = 1 (2.9) 18 Chapter 2. Preliminaries dij ∈[0,1],for i=a,b,c and j=p,o,n. (2.10) Introducing the power-invariant form of the Clarke Transform in (2.2)–(2.6), the next equations are obtained in αβγ coordinates. Ldiα dt =vsα −(dαp −dαn)vdc 2−(dαp +dαn)vd 2(2.11) Ldiβ dt =vsβ −(dβp −dβn)vdc 2−(dβp +dβn)vd 2(2.12) Cdvdc dt = (dαp −dαn)iα+(dβp −dβn)iβ−2vdc R(2.13) Cdvd dt = (dαp +dαn)iα+(dβp +dβn)iβ, (2.14) where the control inputs dαp , dαn , dβp and dβn are the duty ratios in αβγ coordinates. Remaining control inputs dγp and dγn do not appear in the model, as mentioned in [ 44 ], because they are multiplied by iγ , whose value is assumed to be zero, thus the equation of the derivative of iγwith respect to time does not appear either. Phase currents iαand iβcan be expressed in terms of powers as iα=1 v2 sα +v2 sβ vsαp−vsβq(2.15) iβ=1 v2 sα +v2 sβ vsβp+vsαq,(2.16) where p and q are the instantaneous active and reactive powers of the system, respectively. Introducing (2.15) – (2.16) into (2.11) – (2.14) and denoting f as the frequency of the grid and ZL= 2πfL as the inductive reactance, the following equations are obtained, which represent the system model in terms of instantaneous powers. 3.1 Current and Power Controllers 25 A third variant is proposed in order to achieve the voltage balance in the capacitors. As has been used in the first two approaches, the balancing task can be carried out in the modulation stage. In carrier-based pulse width modulation (CBPWM), there exists a common component that can be added/subtracted to the three reference signals simultaneously without affecting the overall performance but allowing the control to modify the levels used like in ICM1 and ICM2. Considering this common component and using the nearest-two-level modulation, the minimum amount of commutations is achieved by keeping one phase at one level while the other two commute between two levels each. This is the case of this last variant, where this common component is calculated by solving an optimization problem. 3.1 Current and Power Controllers Current and power controllers are not the main goal in this thesis, but they are necessary to control the converter. Even so, the formulation used here is a novelty since it uses the averaged model described in the previous section. In this way making a change of variables, as will be seen later, the usual method to design controllers can be used. Therefore, any current control of the many existing in the literature can be used. This section shows two of them. It should be noted that the control used in the development of this thesis is the power control although a current control can be used. 3.1.1 Current Control 1 The first current control is based on [ 60 ], where assuming balanced the voltage in the capacitors it is possible to simplify the dynamic equations of the model (2.11) – (2.12) by Ldiα dt =vsα −(dαp −dαn)vdc 2=vsα −u1 vdc 2(3.1) Ldiβ dt =vsβ −(dβp −dβn)vdc 2=vsβ −u2 vdc 2, (3.2) where the next definition of the control variables u1and u2has been used, 26 Chapter 3. Three-Level Converter Control u1˙= dαp −dαn (3.3) u2˙= dβp −dβn. (3.4) Taking into account this model equations, it is possible to define the next control signals, u1=2 vdc vsα +kp(iα−ir α)+kpi Zt 0 (iα−ir α)dτ!(3.5) u2=2 vdc vsβ +kpiβ−ir β+kpi Zt 0iβ−ir βdτ!, (3.6) where design parameters kp and kpi are the proportional and integral gains of the controller. The currents references are defined, respectively, by ir αand ir β, whose expressions are ir α=1 v2 sα +v2 sβ vsαpr−vsβqr(3.7) ir β=1 v2 sα +v2 sβ vsβpr+vsαqr.(3.8) 3.1.2 Current Control 2 Computing {ir α,ir β} as in (3.7)–(3.8), another current controller can be implemented such as to reduce the current tracking error {iα V ,iβ V }={ir α−iα,ir β−iβ} as much as possible. In this way, a non-ideal proportional-resonant controller [ 61 ] tuned at the grid frequency is implemented. The basic functionality of the PR controller is to introduce an infinite gain at a selected resonant frequency for eliminating steady-state error at that frequency, and is therefore conceptually similar to an integrator whose infinite DC gain forces the DC steady-state error to zero. 3.1 Current and Power Controllers 27 GP Rω(s) = kp+2krωcs s2+2ωcs+ω2(3.9) "u1 u2#=2 vdc −GP Rωg"iα V iβ V #+"vsα vsβ#!, (3.10) where {kp,kr} are, respectively, the proportional and resonant control parameters, ωc is the cut-off frequency of the low-pass filter implemented into the resonant part, ω is the resonant frequency—in this case, tuned at the grid one ( ωg= 2πfgrid )—, and {vsα,vsβ} are the grid voltages in the αβγ frame. One disadvantage of the resonant control is that, being tuned to the frequency of the grid, if this frequency changes the control may stop working satisfactorily. 3.1.3 Instantaneous Power Controller In this section an instantaneous power control is defined, as alternative to the current control, in order to transfer the desired amount of active power with a certain power factor. This is the controller used in the development of this thesis. Using definitions (3.3)–(3.4) into the model equations and assuming that the value of variable vd is small enough to be neglected, the active and reactive power dynamics can be expressed by Ldp dt ≃v2 sα +v2 sβ +ZLq−u1vsα +u2vsβvdc 2(3.11) Ldq dt ≃−ZLp+u1vsβ −u2vsαvdc 2. (3.12) These expressions are equivalent to the instantaneous power dynamics of the conventional two-level converter [ 44 ]. Therefore, by the use of the change of variables (3.3) - (3.4), the added difficulty inherent for the adopted formulation disappears, at least at this stage. Thus, implementing a DPC strategy [ 62 , 63 , 64 ], the virtual control variables are 28 Chapter 3. Three-Level Converter Control defined by u1=uz 1+kpvsα (p−pr)+kpivsα Zt 0 (p−pr)dτ −kqvsβ (q−qr)−kqivsβ Zt 0 (q−qr)dτ (3.13) u2=uz 2+kpvsβ (p−pr)+kpivsβ Zt 0 (p−pr)dτ +kqvsα (q−qr)+kqivsα Zt 0 (q−qr)dτ, (3.14) where design parameters kp , kq , kpi and kqi are the proportional and integral gains of the controller; the instantaneous active and reactive powers references are represented, respectively, by prand qr, and terms uz 1and uz 2are defined by uz 1=2 vdc 1+ ZLq v2 sα +v2 sβ !vsα +ZLp v2 sα +v2 sβ vsβ!(3.15) uz 2=2 vdc 1+ ZLq v2 sα +v2 sβ !vsβ −ZLp v2 sα +v2 sβ vsα!. (3.16) These expressions have been obtained by equating the time derivatives in (3.11) – (3.12) to zero and isolating u1 and u2 . Thus, they both represent the specific values of the virtual control variables such that, when they are applied to the system, that is, when u1=uz 1 and u2=uz 2, the instantaneous powers are constant. 3.2 Total DC-Link Voltage Controller In order to maintain constant the dc-link voltage and close to its reference ( vr dc ), as usual, a specific PI controller is used [ 62 , 65 ]. For this controller, the formulation made using averaged duties does not affect the design so traditional techniques can be used. Notice that the instantaneous power dynamics are faster than those of the total dc-link voltage [ 44 ], so it is possible to assume that p≃pr and q≃qr . Considering this and 3.3 Voltage Balance Controller 29 expressions (3.13) – (3.14), equation (2.19) can be expressed as Cdv2 dc dt ≃4pr−v2 dc R. (3.17) This equation shows the relationship between pr and vdc , being able to define a usual PI controller pr=kdc pvr2 dc −v2 dc+kdc iZt 0vr2 dc −v2 dcdτ, (3.18) where constants kdc pand kdc iare controller tuning parameters. 3.3 Voltage Balance Controller The objective of the voltage balance controller is to keep the state variable vd close to zero, avoiding the unbalance of the dc-link capacitor voltages. This controller is based on the definition of two new virtual control variables u3˙= dαp +dαn (3.19) u4˙= dβp +dβn. (3.20) Introduction of (3.19) – (3.20) into (2.20) yields Cdvd dt =vsαp−vsβq v2 sα +v2 sβ u3+vsβp+vsαq v2 sα +v2 sβ u4. (3.21) It is important to highlight that the definition of u3 and u4 causes a decoupling of the model equations for control purposes. Note that u1 and u2 are designed to regulate the state variables p and q ( iα and iβ in the case of using currents control), whereas u3 and u4 can be used to regulate vd(3.21) . This is an important benefit of the proposed control approach. 30 Chapter 3. Three-Level Converter Control Taking into account (3.21), the following control laws were proposed in [44] u3=kd vsαp−vsβq p2+q2(vr d−vd) +kdi vsαp−vsβq p2+q2Zt 0 (vr d−vd)dτ (3.22) u4=kd vsβp+vsαq p2+q2(vr d−vd) +kdi vsβp+vsαq p2+q2Zt 0 (vr d−vd)dτ, (3.23) where positive constants kd and kdi are tuning parameters. The reference for vd is denoted by vr d , which is set to zero to ensure a balanced distribution of the dc-link voltage across capacitors C1and C2. By introducing (3.22)–(3.23) into (3.21), the voltage balance dynamics become linear: Cd2(vr d−vd) dt2+kd d(vr d−vd) dt +kdi(vr d−vd)=0,(3.24) whose stability is assured provided that parameters kdand kdiare positive. A complete schematic block diagram of all controllers is illustrated in Fig. 3.1. As stated above, in this case a power control has been chosen in addition to the total dc-link voltage and voltage balance control. Using all these controllers, the control signals u1,u2,u3 and u4 are obtained. In the next section, several techniques to convert these control signals to duty values will be shown. 3.3 Voltage Balance Controller 31 Figure 3.1 Complete schematic block diagram of the controllers. 32 Chapter 3. Three-Level Converter Control 3.4 Proposed approaches The controller presented in the previous section provides, at each sampling time, the values for u1,u2,u3 and u4 . The corresponding values for dαp,dαn,dβp and dβn can be obtained solving the system of equations (3.3)–(3.4) and (3.19)–(3.20) yielding dαp =1 2(u1+u3)(3.25) dαn =1 2(−u1+u3)(3.26) dβp =1 2(u2+u4)(3.27) dβn =1 2(−u2+u4). (3.28) In order to compute the actual duty ratios dij,i =a,b,c;j=p,n , the Clarke transformation can be used    daj dbj dcj   =r2 3         1 0 1 √2 −1 2 √3 2 1 √2 −1 2−√3 2 1 √2            dαj dβj dγj   , j =p,n. (3.29) where dγp and dγn are remaining degrees of freedom. Obviously, the remaining duty ratios, dao,dbo and dco can be computed using (2.7)–(2.9). As stated in the introduction to the chapter, the two first approaches that are going to be showed here can be considered as a control method with implicit modulator and are called “Integrated Control and Modulation” (ICM) because part of this modulation has been included in the design of the controllers. In the third approach, the injection of a common component in the voltage output of the converter is used explicitly to achieve the voltage balance. This approach is proposed as an optimization problem based on the equation that controls the voltage balance. In this last variant, the control variables u3 and u4 are not used since the optimization problem is applied directly to the equation that governs the voltage balance in the capacitors. 3.4 Proposed approaches 33 3.4.1 ICM1 The first variant, ICM1, was proposed in [ 44 ]. In this variant, dγp and dγn are chosen to be constant and can be considered tuning parameters. To choose their values, it is necessary to express the control variables at steady state by u1≃2 vr dc Vαβcos(2πft+θ)(3.30) u2≃2 vr dc Vαβsin(2πft+θ)(3.31) u3≃0(3.32) u4≃0, (3.33) where θ and Vαβ are the phase and amplitude of the voltages vsα and vsβ and f is the frequency of the grid. From these expressions it is possible to calculate the duty ratios dαp,dαn,dβp and dβn, in αβ coordinates. Transforming these duties to abc coordinates, together with dγp and dγn and restrictions (2.7)–(2.10), gives the limits to choose these last variables, expressed by dγp +dγn ≤√3(3.34) p(2)Vαβ vr dc ≤dγi ≤√3−√2Vαβ vr dc .(3.35) Notice that in the way in which these limits are obtained, very conservative results are obtained. This approach is a simple way to accomplish the modulation but it presents an important drawback: except by chance, none of the dij will result in zero. This implies that, in each sampling time, each phase commutes among the three levels (positive ( p ), zero ( o ) and negative ( n )) which can be considered too many commutations compared with other approaches, even those including voltage balancing. This fact could yield large switching losses. 34 Chapter 3. Three-Level Converter Control 3.4.2 ICM2 In order to avoid the large number of commutations, a new variant is proposed. This variant, takes advantage of the two degrees of freedom associated with dγp and dγn imposing, at each sampling period, one dip and one din (i=a,b,c) to be zero. The two phases for which one of the duty ratios has to be zero need to be chosen carefully and taking into account that the duty cycles in abc coordinates have to be in the interval [0,1] . The result is that these two phases only switch between two levels. One of them only switches between zero and the positive level and the other one only switches between zero and the negative level. The remaining phase commutes among the three levels. This number of commutations is similar to the one in other control strategies that include voltage balance capabilities [66]. In order to select the phases that commute only between two levels, the following procedure is proposed: first of all, it is necessary to check if setting one of the dij,i = a,b,c;j=p,n to zero yields to the fulfillment of the constraints 0≤dij ≤1 for the rest of duty cycle variables. Starting with the case dap = 0 , Eq. (3.29) for j=p can be considered as a set of equations, where dαp,dβp are known, dap = 0 and dbp,dcp and dγp are the unknowns. The resultant system of equations can be solved in order to check if this case is feasible, that is, if dbp and dcp are in the interval [0,1] . Repeating for the other phases, three different cases have to be analyzed for j=p and other three cases for j=n . The associated equations are Case 1: daj = 0 dbj =−√6 2dαj +√2 2dβj (3.36) dcj =−√6 2dαj −√2 2dβj. (3.37) Case 2: dbj = 0 daj =√6 2dαj −√2 2dβj (3.38) dcj =−√2dβj. (3.39) 3.4 Proposed approaches 41    din = 0 if ui≥0 dip = 0 if ui<0i={a,b,c}.(3.58) Also notice that ui=dip −din for i={a,b,c}. 42 Chapter 3. Three-Level Converter Control 3.5 Simulation Results In this section, the results of the simulations carried out on the circuit of Fig. 2.5, with the ICM1, ICM2 and Variant 3 control strategies, are shown. These simulations have been performed using PSCAD environment. The switching sequence has been generated following the implementation steps described in Section 3.4 and considering a PWM strategy with a triangular carrier where a typical stepped sequencing of levels, similar to CB-PWM [70], is implemented. Circuit and control parameters for the simulations are shown in Table 3.2. Table 3.2 Simulation Parameters. Parameter Value Parameter Value fgrid 50 Hz Sampling frequency (fs) 10 kHz vsa,vsb,vsc 230 VRMS Switching frequency (fsw) 10 kHz L2 mH kp,kq1.5·10-7 C3300 µFkpi,kqi 5·10-5 R120 →60 →120 Ωkd0.1 vr dc 700 →800 V kdi 1·10-2 kdc p0.05 kdc i1 In order to show the system behavior under different conditions, several stages with different resistive load values and reference voltages have been implemented. In this way, the different situations to which the converter is subjected are: •[I]vr dc = 700 V, R = 120 Ω : The values at the starting point are R= 120Ω and vr dc = 700 V. •[II]vr dc = 700 V, R = 60 Ω : A step in the resistive load is applied to make R= 60Ω at t = 1s. •[III]vr dc = 700 →800 V, R = 60 Ω : The dc-link voltage reference is modified from 700 to 800 progressively from t = 1.8s to t = 2.45s. •[IV ]vr dc = 800 V, R = 60 Ω : The dc-link voltage reference is maintained at 800 with R= 60Ωuntil t = 4s. •[V]vr dc = 800 V, R = 120 Ω: Finally the load is changed back to 120Ω. 3.5 Simulation Results 43 Figure 3.4 represents the changes made in the reference voltage and the resistive load. Figure 3.4 Evolution of the reference voltage (top) and the resistive load (bottom) under the simulations. A low-pass filter has also been added to the proportional part of the total dc-link voltage controller as it is recommended in [71] in order to reduce the harmonics presence. During the whole simulation, the instantaneous reactive power reference ( qr ) has been assumed to be zero in order to guarantee unity power factor. In this section, the simulation results of an existing method have been included in order to compare with the aproaches proposed in this thesis. This control technique [ 52 ] uses a modification of virtual space vector [ 53 ] (this modification will be denoted as mVSVPWM) to balance the voltage in the capacitors. In it, the voltage reference vector is obtained by creating virtual vectors where the possible switching states are weighted to generate currents that benefit the voltage balance. 44 Chapter 3. Three-Level Converter Control Figure 3.5 Simulation results: evolution of the instantaneous active power p (solid) and its reference value pr (dashed), considering ICM1 (top), ICM2 (mid-up), Variant 3 (mid-down) and mVSVPWM (bottom) through the different stages of Fig. 3.4. In Fig. 3.5 the instantaneous active power achieved for all the control laws and their references are shown. In this figure it is possible to observe how ICM2 presents a ripple smaller than ICM1, as well as Variant 3 with respect to ICM2. In fact, the Variant 3 approach presents a considerable improvement over the rest of the approaches. In the proposed approaches, the reference of active power is calculated by a PI controller from the reference voltage vr dc . This last variable can be seen, along with vdc , in Fig. 3.6 where its tracking can be corroborated. As it is possible to see in this figure, the result in the control of the total dc-link voltage is similar in all the techniques used. 3.5 Simulation Results 45 Figure 3.6 Simulation results: evolution of the total dc-link voltage vdc (solid) and its reference value vr dc (dashed), considering ICM1 (top), ICM2 (mid-up), Variant 3 (mid-down) and mVSVPWM (bottom) through the different stages of Fig. 3.4. Capacitor voltages are represented in Fig. 3.7, showing the behavior from an unbalanced condition with vr dc = 700 V and R = 120 Ω . In this figure it is possible to observe how the voltage is corrected much faster in Variant 3 than in the two previous proposed laws, reaching a convergence rate very close to mVSVPWM. In all of the laws, the voltage balance observed is much faster than the natural balance that can be obtained in the converter when connecting a purely resistive linear load. Notice that ICMs approaches have some tuning parameters ( Kd and Kdi ) that could increase the speed on correcting the unbalance condition at the expenses of worsening the evolution of the currents during the transients because of saturation issues of the control variables u3 and u4 . Therefore, there is a trade-off between balancing speed and transient behaviour in ICMs. In Fig. 3.8, the grid currents are shown for the four algorithms where it can be seen a reduction in the ripple from ICM1 to ICM2 and to Variant 3, while mVSVPWM stays in the middle. This result is due to the presence of dead-times whose effect is lower when fewer commutations are implied. Furthermore, the unbalances are corrected even under non-symmetrical phase currents conditions. This fact is shown in Fig. 3.9 where the phase currents are unequal and the capacitor voltages are corrected from the same 46 Chapter 3. Three-Level Converter Control initial condition as Fig. 3.7. Based on the currents showed in Fig. 3.8, the total harmonic distortion of all the approaches are obtained, yielding a THD of 5.6% in ICM1, 4.2% in ICM2, 3.9% in Variant 3 and 4.6% in mVSVPWM. Variant 3 Variant 3 Figure 3.7 Simulation results: evolution of the capacitor voltages starting from an unbalanced condition, considering ICM1, ICM2, Variant 3 and mVSVPWM. (solid) balancing control activated; (dashed) no balancing control; (dash-dotted) reference voltage. 3.5 Simulation Results 47 Figure 3.8 Simulation results: three-phase grid current considering ICM1 (top), ICM2 (mid-up), Variant 3 (mid-down) and mVSVPWM (bottom). vr dc = 800 V and R= 60Ω. Figure 3.9 Simulation results: Capacitor voltages (bottom) starting from an unbalanced condition when phase currents (top) are distorted, considering ICM1, ICM2, Variant 3 and mVSVPWM. 48 Chapter 3. Three-Level Converter Control Duty cycles and switching states for phase a in steady state are shown in Fig. 3.10 and 3.11 respectively. Notice that Fig. 3.11 also includes the switching state of the mVSVPWM approach which cannot be depicted similarly to Fig. 3.10 as the duty ratios for each level are not concern in this modulation approach. Figure 3.11 also includes its filtered signal in order to depict the output waveform. In this figure, state p refers to when both upper switching devices are closed; state o corresponds to both switching devices in the middle closed; and state n refers to lower switching devices closed according to Fig 2.6. Besides, it is possible to see that the commutations in phase a change among the three levels in ICM1 control law whereas, when using ICM2 and Variant 3, commutation between two levels is more frequent. Notice that shape of the output waveform of ICM2 is similar to those modulation approaches that inject a third-harmonic component to extend the fundamental frequency operative range which makes it possible to increase the modulation index without saturating the control signals. Therefore, this is another advantage of ICM2 when comparing with ICM1. This advantage can be corroborated when looking at figure 3.10 where the maximum values of signals dan and dap are lower in the ICM2 approach. Based on Fig. 3.11 it is possible to obtain the numbers of commutations of the studied approaches, yielding 800 commutations per grid period at 10 KHz of switching frequency in ICM1, 522 in ICM2, 281 in Variant 3 and 412 in mVSVPWM. Figure 3.10 Simulation results: duty cycles of phase a considering ICM1 (top), ICM2 (mid) and Variant 3 (bottom). 3.5 Simulation Results 49 Figure 3.11 Simulation results: switching states of phase a and its averaged signal, considering ICM1 (top), ICM2 (mid-up), Variant 3 (mid-down) and mVSVPWM (bottom). In conclusion, the results of the simulations performed with all the approaches are resumed in the table 3.3. In this table it is possible to observe the improvement in the THD, number of commutations and balance speed form Variant 3 to ICM2 and to ICM1. Table 3.3 Simulations results of the considered approaches. Approach THD value Number of commutations Balancing time (Fig. 3.9) Ripple mVSVPWM 4.6% 412 0.17s + ICM1 5.6% 800 0.60s ++ ICM2 4.2% 522 0.5s + Variant 3 3.9% 281 0.2s - 50 Chapter 3. Three-Level Converter Control 3.6 Experimental Results This section presents the experimental results obtained in the laboratory. To this end, the three-level NPC converter shown in Fig. 3.12, has been used. It has been configured as rectifier and it has the same circuit and control parameters as those provided in Table 3.2. Appendix A shows the design and construction of this converter. According to the simulations, similar changes in the load ( R ) and dc-link reference voltage ( vr dc ) are considered. The evolution of these two parameters was shown in Fig. 3.4. In Fig. 3.13, the evolution of the instantaneous active power and its reference are shown for the proposed approaches and mVSVPWM. Notice a slight reduction in the power ripple Figure 3.12 Experimental prototype of the three-level NPC rectifier. 4 Switched Affine Systems Modelling If everything seems under control, you are not going fast enough Mario Andretti Contents 4.1. Problem Formulation for Systems with High-Frequency Sampling Time 59 4.1.1. Delta Operator for High-Frequency Switching Signals 61 4.1.2. Control objectives 62 4.2. Usual Discrete-Time Formulation for Switched Affine Systems 63 4.2.1. Control Objectives 64 4.2.2. Application to a DC-DC Converter 65 Dy namic systems are usually classified into two types of systems, continuous systems and discrete systems. However, there are certain systems, such as systems that combine analog and digital components such as a power converter, which can be classified into both groups. These types of systems are called hybrid systems [72]. One kind of this type of systems is the switched system that is a hybrid dynamical system consisting of several continuous-time subsystems and a rule that selects between 57 58 Chapter 4. Switched Affine Systems Modelling them [ 73 , 74 ]. These systems present an interesting behavior. For example, it is possible to switch between asymptotically stable systems and obtain an unstable overall system, and on the other hand, to switch between unstable systems and obtain a stable overall switched system [ 75 , 76 ]. A class of switched systems are the switched affine systems which are non-linear systems that are linear in the input [ 73 , 77 ]. The control of this kind of systems presents a challenge since the different subsystems do not necessarily share a common equilibrium. Many different works have been published proposing new control methods to get stabilization, like [ 78 ], where authors reformulate the stabilization of switched affine systems as a classical stabilization problem for nonlinear systems affine in the input, thus obtaining stability into a ball, or [ 77 ], where several control laws are designed in order to obtain stability in a set of equilibrium points. The objective of this last paper is to calculate the set and design the control law so that any system trajectory converges to the interior of the set. In these works, the equilibrium is achieved with infinite arbitrarily switching. In [ 79 , 80 ], it is possible to find similar solutions for switched affine systems with dwell-time guarantees, ensuring a finite arbitrarily switching. In many occasions it is necessary to control these kind of systems with periodic switching which are useful to describe periodic natural phenomena and also arise in linearisation of time-invariant dynamical systems around periodic orbits and when treating multi-rate systems where actuator and sensors operate at different frequencies [ 81 ]. This problem was dealt in [ 82 ], where simple criteria are given to optimize the choice of Lyapunov functions and a sampled-data switching control is designed to ensure robustness in switched affine systems. In that paper, the goal is to provide methods for the design of sampled-data switching laws that practically stabilize the system guaranteeing that the state converges to a compact set. This is first investigated for systems that admit a stable convex combination for the desired equilibrium and then is generalized to the rest of the systems using switched Lyapunov functions. The solution obtained in that paper turns out to be conservative due to the use of the Jensen inequality. In [ 79 ], robust stability for affine discrete systems using sampled-data controllers is investigated. In that paper, the different control strategies are also based on achieving convergence to a compact set. As can be seen, the solution is even more conservative than in [82]. In some applications, when discretizing these systems, if the sample time is very low, problems may appear to achieve convergence to the continuous solution, because of numerical issues. In [ 83 ], a comparison is made between the z operator ( q in that work) and the δ operator to perform this discretization. There, it is possible to observe as the δ operator presents as advantages the natural convergence to a continuous system, while 4.1 Problem Formulation for Systems with High-Frequency Sampling Time 59 avoiding numerical problems when the sampling period is very short. Thus, in [ 84 ] it is possible to observe that the delta operator is used to design the sliding mode fuzzy controller of a DC-DC buck converter due to the need for very fast sampling. Therefore, the use of the δ operator presents a great advantage in the design of controllers with very fast sampling times. To address the control of systems with high-frequency sampling times, two controllers are presented in this thesis, inspired by [ 85 ], where δ operator is used taking into account the advantages of this operator mentioned previously. Therefore, due to the use of δ operator, less conservative results are obtained than those mentioned above for a non-linear affine system with a very fast switching frequency. Using all these resources, in section 5.1, a controller based on the Lyapunov function has been developed as well as another relaxed one in which the selection of the Lyapunov function and the design of the switching control law are decoupled. For the cases when the sampling time is not excessively low and the z operator can be used without numerical problems, other two approaches are presented in section 5.2 without the need to use the δ operator. These control laws are based in the techniques presented in [ 86 ] to design periodic controllers for switching affine systems. These controllers guarantee the global asymptotic stabilization to a minimum invariant set including the origin, thanks to the solution of a simple optimization problem. It is also demonstrated that this relaxed control law includes Lyapunov matrix-based controllers as particular cases. In the controllers presented, the design is based on a quadratic Lyapunov function and guarantee global practical stabilization. The first one is based on a relaxed control law. The second one is a robust control that presents the possibility to apply the method to systems with parameter uncertainties. Although the δ operator has advantages over traditional discretization, it has not been used in these last controllers since they are designed for systems with low switching frequency, so that the traditional approach, based on [ 86 ], has very good results. 4.1 Problem Formulation for Systems with High-Frequency Sampling Time This section focuses on a class of switched affine systems defined by ˙z=Aσz+aσ,(4.1) 60 Chapter 4. Switched Affine Systems Modelling where z∈Rn is the state and it is accessible and Aσ and aσ present suited dimensions. The control action is performed through the high frequency switching signal σ∈KN:= {1,2,...,N} , which may be only modified at sampling instants tk , with k∈N . The length of the sampling interval tk+1 −tk=T is assumed to be constant, known and very small. Thus, this section focuses on the design problem of a feedback law for the high frequency periodic switching signal σ , in such a way to ensure suitable practical convergence properties of the plant state z to a operating equilibrium ze , which is not necessarily an equilibrium for the continuous-time dynamics in (4.1), but can be obtained as an equilibrium for the switching system with arbitrary switching. A necessary and sufficient condition characterizing this equilibrium is then represented by the following standard assumption (see [74, 77]). Assumption 1 There exists λ= [λ1,λ2,...,λN] satisfying Pi∈Kλi= 1 and 0≤λi≤1 , such that the following convex combination holds: X i∈K λi(Aize+ai) = A(λ)ze+a(λ)=0.(4.2) It is emphasized that Assumption 1 is both necessary and sufficient for the existence of a suitable switching signal ensuring forward invariance of the point ze (namely inducing an equilibrium at ze ) when understanding solutions in the generalized sense of Krasovskii or Filippov. Indeed, under (4.2), we can conclude that the error equation of (4.1) is: ˙x=Aσx+Bσ,(4.3) where the error vector is denoted by x:= z−ze and where the matrices Bσ are defined by Bσ:= Aσze+aσ and verify the following convex combination Pi∈KλiBi= 0 . The objective is to ensure that the error state x converges to the equilibrium x= 0 in the Filippov sense. In addition, the following property is assumed. Assumption 2 The matrices Ai, for i∈KNare non-singular and A(λ)is Hurwitz. 4.1 Problem Formulation for Systems with High-Frequency Sampling Time 61 4.1.1 Delta Operator for High-Frequency Switching Signals In this subsection, a discrete-time model based on the δ operator [ 87 ] is proposed, which is suitable for high switching frequencies. The δ operator has been widely used in the literature to avoid numerical problems in the computation of discrete-time dynamics. This is based on the continuous ones in the situation where the sampling period T is potentially very small. The definition of the δ operator is as follows. For any function ξ from R+ to Rn, the vector δξk, at any sampling instant tk∈R+, is defined as follows δξk:= 1 T(ξk+1 −ξk),∀k≥0, where the convention ξk=ξ(tk) and δξk=δξ(tk) have been used, for all integer k≥0 . Hence the dynamics of system (4.1) can be rewritten in the framework of the δ operator, which yields the following dynamics δxk=Eσxk+Fσ(4.4) where the matrices that defines the system dynamics are given by Eσ=1 T(eAσT−I), Fσ=1 TRT 0eAσ(T−s)dsBσ.(4.5) The interest of this formulation compared to the usual discrete-time formulation comes from the fact that, when T goes to zero, matrices Eσ and Fσ converge to Aσ and Bσ , respectively. Another important issue is that matrices Eσ and Fσ depend explicitly on the switching period T . Indeed, considering small values of T , the usual discretization of (4.3) may lead to several numerical problems, which are avoided using the formulation (4.4). Note that if matrix Aσis non singular, then a simple expression of Fσis provided by Fσ=eAσT−I TA−1 σBσ. It is worth noting that model (4.4) does not account for the continuous evolution of (4.1) during the intersampling time. It is however possible to characterize the continuous solution by integrating the solution over a sampling interval, leading, for all t∈[tk, tk+T] 62 Chapter 4. Switched Affine Systems Modelling and for all k∈N, to x(t) = eAσ(t−tk)x(tk)+Zt tk eAσ(τ−tk)dτaσ Since t belongs to the bound interval [tk, tk+T] , the solutions to the system are obviously bounded during the inter sampling time. 4.1.2 Control objectives When considering switching affine system (4.3) , its solutions do not necessarily converge to the origin but to a neighbourhood of it, generating a chattering effect around zero when employing sliding mode control [ 88 ]. Therefore, one has to relax the control objectives and to consider attractor sets, which are not necessarily reduced to the equilibrium set. In this way, an estimation of the attractive set is considered, which is of the following quadratic form E:= x∈Rn, x>Sx ≤1.(4.6) where S is a symmetric positive definite matrix to be optimized. This formulation is quite usual and has been used in other contexts as in [80, 82, 85]. Therefore, the control objective is the design of a feedback law for the high frequency periodic switching signal σ , in such a way to ensure suitable practical convergence properties of the plant state x to zero, which is not necessarily an equilibrium for the continuous-time dynamics in (4.3), but can be obtained as an equilibrium for the switching system with arbitrary switching. A necessary and sufficient condition characterizing this equilibrium is then represented by the standard Assumption 2 (see [ 74 , 77 ]). The problem can be summarized as follows Problem 1 For any small sampling period T , the problem is to find a switching control law that selects, at each sampling time, the mode or subsystem among all possibilities that stabilizes system (4.1) with certain performance guarantees at its equilibrium. 4.2 Usual Discrete-Time Formulation for Switched Affine Systems 63 4.2 Usual Discrete-Time Formulation for Switched Affine Systems This section presents an alternative model to the formulation made in the previous section. In that section, an improvement in the results with respect to existing techniques has been shown, but it has a disadvantage. When using a Lyapunov function based on a matrix P different from the matrix that defines the attractor E , there is a possibility that the evolution of the system reaches a point outside the level set that define ∆V < 0 but remain within of the attractor. This fact can cause the system to become unstable. In this way, a new formulation has been used where the volume of the attractor depends directly on the matrix that defines the Lyapunov function. An improvement has also been included defining the center of the attractor at an optimal point that does not have to be the origin. In this way, inspired by [86], we define again the system model as: z+=Aσz+aσ(4.7) where z∈Rn is the state, z+ represents the update of the system and matrices Aσ and aσ present suited dimensions. The control action is performed through the switching signal σ∈K:= {1,2,...,N}, that selects at each instant of time one of the Nsubsystems. Definition 1 Consider the set Ωegiven by Ωe={ze∈Rn,∃λ∈ΛK,(Aλ−I)ze+aλ= 0}(4.8) where ze is not necessarily an equilibrium for the continuous-time dynamics in (4.7), but can be obtained as equilibrium for the switching system with arbitrary switching, ΛK:= λ= (λ1,...,λN)∈[0,1]N|Pi∈Kλi= 1,Aλ:= Pi∈KλiAiand aλ:= Pi∈Kλiai. Set Ωe only characterizes some possible acceptable equilibriums for system (4.7) . It is important to note that not all acceptable equilibriums belong to this set. For a given ze in Ωe let us define the error variable x:= z−ze , where z is driven by system (4.7). Then, the error dynamics is governed by x+=Aσx+Bσ,(4.9) 64 Chapter 4. Switched Affine Systems Modelling with Bσ:= (Aσ−I)ze+aσ . Then, from Definition 1, the linear combination λ in ΛK implies Bλ:= X i∈K λiBi= 0 for λ∈ΛK.(4.10) 4.2.1 Control Objectives As said in subsection 4.1.2, we will consider an estimation of an invariant set that includes the origin. Then, we introduce the set given by A:= {x∈Rn, V (x,xc)≤1}.(4.11) Which is defined by a level set of a Lyapunov function given by V(x,xc)=(x−xc)>P(x−xc),(4.12) where P is a positive definite matrix. In order to obtain less conservative results, the vector xcwill be used to shift the center of the level sets from the origin. Thus, the objective is to design a robust control law for σ , which ensures that A is a neighbourhood of the origin and is globally asymptotically stable for system (4.9) , which is also sought of minimum volume. This can be summarized as follows (i) If xis not in A, then ∆V (x,xc) = V(x+,xc)−V(x,xc)is negative definite. (ii) The origin x= 0 belongs to A. (iii) If xbelongs to A, then x+also belongs to Aunder the dynamics of (4.9). Asymptotic stability is a fundamental property of dynamical systems due to the fact that provides qualitative information about solutions, especially a characterization of the solutions’ long-term trends [ 72 ]. As said before, the solution of a hybrid system often do not converge to an equilibrium point, so the asymptotic stability of a closed set is studied. Anyway, asymptotic stability of an equilibrium point is a particular case of the asymptotic stability of a closed set, since an equilibrium point is just a closed set formed with a single point. 4.2 Usual Discrete-Time Formulation for Switched Affine Systems 65 u RLS R o i L S 1 2 v c C o Figure 4.1 Schematic diagram of a boost converter. 4.2.2 Application to a DC-DC Converter In order to use the expressions in (4.3) and (4.9) applied to a boost type DC-DC converter like the one shown in Fig. 4.1, it is possible to define the matrices Aσand aσby A1="−R L0 0−1 R0C0#, a1="1 L 0#u A2="−R L −1 L 1 C0−1 R0C0#, a2="1 L 0#u, where S1and S2are the switches, uis the input voltage and R0is the load. Due to the configuration of the converter, N is equal to 2, which are the two states defined by the possible positions of the switches. Thus, when σ is equal to 1, the switch S1 is closed and the switch S2 is open and when σ is equal to 2, the switch S1 is open and the switch S2 is closed. It must be remembered that the positions of the switches have to be the opposite each other, so when S1is open, S2must be closed and viceversa. In this application, the error dynamics is defined by the state variable x= [iLvc]> , where iLdenotes the inductor current and vcthe capacitor voltage. This model will be used in the next chapter to show the numerical examples of the developed control design methods. 5.1 Control Laws for Systems with High-Frequency Sampling time 73 Table 5.1 Numerical values of µ1,µ2,γ1and γ2. Parameters Tsµ1µ2γ1γ2 Th. 1 10−49.84 9.86 0.948 0.0515 10−50.16 0.157 0.777 0.223 10−60.907 0.907 0.782 0.218 Th. 2 10−43.16 3.16 0.916 0.327 10−51 1 0.349 0.1 10−60.313 0.313 10 2.793 switched system state space model (4.1) is defined by the following matrices for i= 1,2: Ai="−R L (1−i) L (i−1) C0−1 R0C0#, ai="1 L 0#u. The chosen simulation parameters are given by ze=h3 120i> , λ = [0.22 0.78] for which simple calculations ensure the satisfaction of Assumption 2. The optimization problems given in Proposition 1 is solved using the CVX solver [ 90 , 91 ]. The results obtained with this software illustrate our the efficiency of the new control law presented in Theorem 2 with respect to the Lyapunov-based controller employed in the literature, presented in Theorem 1. As pointed out in Remark 2, the optimization scheme presented in Proposition 1 delivers different results for different values of γi and µj . Therefore, a random algorithm has been considered to obtain the best tuple of parameters. The values of these parameters µ1,µ2,γ1 and γ2, obtained for several values of the sampling period Tsare provided in Table 5.1. Figure 5.1 shows the state trajectories, set E and δV > 0 surface in the state-plane for the different controllers given in Proposition 1, as well as for different sampling periods. Note that the δV > 0 surface is in the interior of the set E as is expected from Theorem 1 and 2. Remark also as E is reduced, as Ts decreases. We can see that set E is reduced with control law C2 with respect to C1, showing as the control law C2 provide reduced region of attraction with respect to C1. This is consistent with Remark 1. Another important remark concerns the fact that the region where δV > 0 is concentrated in a smaller area in control law C2 with respect to C1. 74 Chapter 5. Control of Switched Affine Systems (a) C1 with T= 10−4. (b) C2 with T= 10−4. (c) C1 with T= 10−5. (d) C2 with T= 10−5. -30 -20 -10 0 10 20 z1 100 110 120 130 140 150 160 170 z2 (e) C1 with T= 10−6. -30 -20 -10 0 10 20 z1 100 110 120 130 140 150 160 170 z2 (f) C2 with T= 10−6. Figure 5.1 Numerical results of Proposition 1. Time trajectories (green), set E (yellow) and δV > 0(red). These simulations demonstrate the advantages of the relaxed control law over the existing Lyapunov-based one. Indeed, the proposed controller C2 allows to control efficiently the DC-DC converter under study even with relatively high sampling period with a notable reduction of the switches of the system, which ensures an increase of the lifespan and the reduction of the dissipated energy. 5.2 Control Laws for the Usual Discrete-Time Formulation of Switched Affine Systems 75 5.2 Control Laws for the Usual Discrete-Time Formulation of Switched Affine Systems In this section two design methods will be presented, the first one is for nominal systems while the second is aimed to obtain robustness against model parameter variations of the usual discrete-time formulation of switched affine systems presented in section 4.2. Also a control design method already existing in the literature will be presented, which will serve to perform a comparison in terms of robustness and optimization. 5.2.1 Basic Switching control In this section, a novel stabilization theorem based on a relaxed control law is proposed. This theorem notably differs from the classical Lyapunov matrix-based min-projection control law developed in [ 82 , 86 , 89 ], for instance. This type of control law implies that the controller corresponding to the smallest Lyapunov function should be selected. The first theorem proposed is formalized as follows Theorem 3 For a given ze in Ωe , assume that there exist P∈Rn×n0 , h∈Rn , Ni=N> i∈ R(n+1)×(n+1) and µ∈(0,1), solution to the optimization problem min P,h,Ni,µ −log(det(P)),(5.10) s.t. P0,(5.11)    Ψi+Nλ−Ni−"0 0 ∗µ#µ"P h># ∗ −µP   ≺0,∀i∈K,(5.12) where λis the linear combination related to zein Definition 1 (Section 4.2) and 76 Chapter 5. Control of Switched Affine Systems Ψi:= "AiBi 0 1 #>"P h ∗0#"AiBi 0 1 #−"P h ∗0#.(5.13) Nλ:= X i∈K λiNi.(5.14) Then, the switching control law, given by σ∈argmin i∈K"z−ze 1#> Ni"z−ze 1#,(5.15) ensures that set A , with x=z−ze , fulfills properties (i), (ii) and (iii) of Problem 1 for system (4.7). It should be note that control law σ in (5.15) is defined as an inclusion to allow the possibility of having several modes resulting from the min-projection control law. This is an important issue for the well-posedness of the system. The minimization problem presented in Theorem 3 is similar to the one presented in [ 86 ]. The main motivation of minimizing −log(det(P)) is related to the minimization of the volume of set A through the maximization of eigenvalues of the positive definite matrix P . Indeed, the volume of the ellipsoid characterized by V(x,xc)≤1 is proportional to (det(P))−1/2 . In this section, the evaluation of performance will be based on the minimum value of (det(P))−1/2 , obtained in several situations. This represents another improvement respect to the formulation made in the section before. Remark 3 The non-convex optimization problem (5.10) - (5.12) can be reformulated as a Linear Matrix Inequality (LMI), and consequently into a convex problem, by fixing parameter µ in (0,1). Then, a line-search routine on µ∈(0,1) allows finding the optimum. In the next proof, it will be demonstrated that the controller designed fulfills (i), (ii) and (iii). 5.2 Control Laws for the Usual Discrete-Time Formulation of Switched Affine Systems 77 Proof. Proof of (i): Assume that there exist a positive definite matrix P , a vector h and symmetric matrices Ni , i∈K that are solution to (5.10) - (5.12) for a given positive parameter µ∈(0,1) , following Remark 3. Then, consider Lyapunov function V(x,xc) = (x−xc)>P(x−xc), defined in (4.12), with x=z−zeand xc=−P−1hgiven by V(x,−P−1h) := (x+P−1h)>P(x+P−1h).(5.16) It is clear that the assumption on the positive definiteness of matrix P ensures the positive definiteness of V . The computation of the forward increment of the Lyapunov function is given by ∆V (x,−P−1h) = V(x+,−P−1h)−V(x,−P−1h) = (x++P−1h)>P(x++P−1h) −(x+P−1h)>P(x+P−1h) =x+>Px+−x>Px +2(x+−x)>h. Replacing x+ by its expression x+=Aσx+Bσ , the forward increment of the Lyapunov function can be rewritten as follows ∆V (x,−P−1h) = "x 1#> Ψσ"x 1#, where σ∈K , corresponds to the active mode at the current time and where Ψσ is defined in (5.13) with i=σ . In order to include the selection of the control law (5.15) and the fact that x /∈A , two additional steps are required. First, the switching control law (5.15) ensures σ∈argmin i∈K"x 1#> Ni"x 1#⇒"x 1#> (Ni−Nσ)"x 1#≥0,∀i∈K, ⇒"x 1#> (Nλ−Nσ)"x 1#≥0,∀λ∈ΛK. (5.17) The second step is related to the fact that the negative definiteness of ∆V is only required outside A , i.e. for any x∈Rn , such that V(x,P−1h)≥1 , which can be easily rewritten as follows ∀x /∈A,"x 1#>"P h ∗h>P−1h−1#"x 1#≥0. 78 Chapter 5. Control of Switched Affine Systems Hence, to summarize the previous computations, (i) holds if, for a given parameter µ∈(0,1) and λsatisfying Definition 1, there exist matrices P,h and Nisuch that "x 1#> Ψσ"x 1#<0 holds for all (x,σ)in Rn×Kthat verify "x 1#>"P h ∗h>P−1h−1#"x 1#≥0,"x 1#> (Nλ−Nσ)"x 1#≥0. Using two successive S-procedures as in [ 86 ], which introduces unavoidably some conservatism, this problem is recast into the existence of a parameter µ > 0such that Ψσ+Nλ−Nσ+µ"P h ∗h>P−1h−1#≺0, σ ∈K.(5.18) The proof is concluded by noting that matrix hP h ∗h>P−1hi can be rewritten as hP h>iP−1hP h>i> , so that the application of the Schur complement leads to condition (5.12). Proof of (ii): The objective is here to prove that LMI (5.12) ensures that the origin belongs to A. Formally, this means V(0,−P−1h) = h>P−1h≤1.(5.19) To proceed with this proof, let us compute the linear combination of (5.18), weighted by λ. This yields X i∈K λi Ψi+Nλ−Ni+µ"P h ∗h>P−1h−1#!≺0. Noting that Pi∈Kλi= 1 and Pi∈KλiNi=Nλ, the previous inequality reduces to Ψλ+µ"P h ∗h>P−1h−1#≺0,(5.20) 5.2 Control Laws for the Usual Discrete-Time Formulation of Switched Affine Systems 79 where Ψλ=Pi∈KλiΨi, and is given by Ψλ=   X i∈K λiA> iPAi−PX i∈K λiA> iPBi−(I−A> λ)h ∗X i∈K λiB> iPBi    ,(5.21) where Bλ= 0 have been used . A necessary condition for this inequality is that the last diagonal term located at position (n+1,n+ 1) is negative definite, which corresponds to Pi∈KλiB> iPBi+h>P−1h−1<0 , which ensures (5.19) since the first term is positive. Proof of (iii): Let us assume that xis in set A. From (5.12), we know that V(x+,−P−1h)−V(x,−P−1h) +µV(x,−P−1h)−1+Cσ<0, where Cσ= [x 1]>(Nλ−Nσ)[x 1] is known to be positive according to (5.17) . Hence, we have V(x+,−P−1h)≤(1−µ)V(x,−P−1h) +µ−Cσ ≤(1−µ)V(x,−P−1h) +µ. Since x belongs to A , we know, by definition, that V(x, −P−1h)≤1 . Since the parameter µhas been selected in (0,1),1−µis positive, so that we have V(x+,−P−1h)≤(1−µ)+ µ= 1, which means that x+also belongs to A. The optimization regarding parameter µ has to be performed using a line-search routine on (0,1), c.f. Remark 3, which concludes the proof.  Remark 4 As mentioned in this proof, condition (5.12) imply inequality (5.20) . Another necessary condition of (5.12) apart from 0∈A , is obtained from the definition of matrices Ψi , which leads to inequality Pi∈KλiA> iPAi−(1 −µ)P≺0 . This necessary condition will be commented in the next section. 80 Chapter 5. Control of Switched Affine Systems Comparison with the optimal control design of [86] In this section, it is shown as the solution given in [ 86 ] for system (4.7) is included in the solutions given in Theorem 3. First of all, the statement of [ 86 , Theorem 3] is recalled. This theorem has been reformulated in order to be consistent with the presentation of this thesis. Theorem 4[86] For a given ze in Ωe , and the associated linear combination λ related to Definition 1, assume that matrices P,W ∈Rn×n0 and parameter β > 0 are the solution to the optimization problem min P,W,β −log(det(P)),(5.22) s.t. P0,(5.23) X i∈K λiA> iPAi−P < −W(5.24) X i∈K λi   βW 0−P ∗1−βB> iPBi−h> ∗ ∗ ∗ P   >0,(5.25) where h∗= (1−A> λ)−1Pi∈KλiA> iPBi. Then, the switching control law, given by σ∗∈argmin i∈K V(Ai(z−ze)+Bi,−P−1h∗),(5.26) where V corresponds to the Lyapunov function (4.12) , ensures that A , with x=z−ze , fulfills properties (i), (ii) and (iii) of Problem 1 for system (4.7). Remark 5 The interest of this theorem relies on the optimality of a min-max problem that provides the smallest upper bound of the decrement of V . This optimal value of the shifting vector h is given by the expression h∗= (1−A> λ)−1Pi∈KλiA> iPBi . However, this selection of h∗is performed regardless the minimization of volume of the invariant set A. In order to validate the potential of Theorem 3 over Theorem 4, there is a need to 5.2 Control Laws for the Usual Discrete-Time Formulation of Switched Affine Systems 81 understand if the optimal solution to Theorem 4 is also a solution provided in Theorem 3. This property is summarized in the following proposition. Proposition 2 Solution (P∗,h∗,β) of Theorem 4 is also solution to the minimization problem of Theorem 3. Proof. Note that the control law (5.26) provided in [ 86 ] can be expressed as the control law (5.15) provided in Theorem 3 using the Ψi matrices defined in (5.13) , with P=P∗ , since σ∗∈argmin i∈K"x 1#> Ψi+"P∗h∗ ∗0#!"x 1#,(5.27) where x=z−ze and the free matrices Ni are given by Ψi+P∗h∗ ∗0 . Hence, reinjecting this expression into (5.12) yields Γi:=    Ψi+Ψλ−Ψi−"0 0 ∗µ#µ"P∗ h> ∗# ∗ −µP∗   , i ∈K :=    Ψλ−"0 0 ∗µ#µ"P∗ h> ∗# ∗ −µP∗   , i ∈K, (5.28) where Ψλ=Pi∈KλiΨi . Already note from the previous expression, that the definition of Γi does not depend on the mode i . Therefore, it is possible to omit the subscript i and only consider Γi=Γ, for all iin K. It can be note from the definition of h∗ ensures that the non diagonal entry of (5.21) , verifies X i∈K λiA> iP∗Bi−(I−A> λ)h∗= 0. Therefore, from (5.21) and (5.24), the following upper bound of Γis derived 82 Chapter 5. Control of Switched Affine Systems Γ≺−µ     µ−1W0−P∗ ∗1−µ−1X i∈K λiB> iP∗Bi−h> ∗ ∗ ∗ P∗      | {z } 0with µ=β−1. ≺0. In order to be complete, it remains to prove that parameter µ=β−1 belongs to the interval (0,1) . To do that, notice that a necessary condition for constrain (5.25) to hold is that matrix hβW −P∗ −P∗P∗i is positive definite or, equivalently, Wβ−1P∗ , which together with (5.24) requires the satisfaction of Pi∈KλiA> iP∗Ai−(1−β−1)P∗≺0. This inequality cannot be satisfied unless µ=β−1belongs to (0,1), which concludes the proof.  The previous proposition demonstrates that the optimal solution presented in [ 86 ] is also a solution of the optimization problem (5.10) – (5.12) . This means that Theorem 3 provides, at least, the same optimal solution as Theorem 4. Moreover, since the control law defined in Theorem 3 has more degrees of freedom, one may expect that it may even relax some constraints and provides less conservative solutions. Another advantage of the unstructured control matrices Ni ’s over the Lyapunov matrix-based control law relies on the fact that they are decoupled from the Lyapunov matrix P . This means that there is no need to introduce an additional parameter to the LMI when applying the S-procedure to account for control law (5.15), which generally introduces additional conservatism. It is possible to see that both Theorems 3 and 4 include the same necessary condition given in Remark 4. This means, again, that both theorems have the same limitations. However, in light of Proposition 2, Theorem 3 can provide a smaller estimation of the set A, thanks to the relaxed control law (5.15). It is worth noting that the conditions of Theorem 4 are computationally less demanding than those of Theorem 3. Indeed, Theorem 3 introduces the control matrices Ni as decisions variables of the minimization problem and the number of LMIs to be verified increases linearly with the number of modes. 5.2.2 Robust controlled system Another interest of the presented approach over [ 86 ] concerns the design of a robust switching control law for uncertain switched affine systems. In this situation, matrices Ai and Bi may be subject to parameter uncertainties. Therefore, it is not possible to define a 5.2 Control Laws for the Usual Discrete-Time Formulation of Switched Affine Systems 89 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 0 50 100 150 Figure 5.3 Evolution of (det(P))−1 2 with unstructured matrices Ni ’s (solid) in (5.34) , and with the Lyapunov matrix-based control law (5.27) (dashed). 90 Chapter 5. Control of Switched Affine Systems Application to a Boost Converter A possible application of the control laws presented in section 5.2 is a boost converter like the one showed in 4.2.2. In that section, the state variable is defined by x= [iLvc]> , where iLdenotes the inductor current and vcthe capacitor voltage. In order to compare the efficiency with the other control laws presented in section 5.1 and in [ 77 ], the considered nominal values of the parameters of the converter are: u= 100V , R= 2Ω , L= 500µH , Co= 470µF and Ro= 50Ω . This parameters define the switched system state space models (4.3) and (4.9) by the following matrices for i= 1,2: Ai="−R L (1−i) L (i−1) C0−1 R0C0#, ai="1 L 0#u. The chosen simulation parameters are given by ze=h3 120i> , λ = [0.22 0.78] and T = 10−4s With this parameters and the value of µ =0.1137 for an example with the values showed before and µ =0.1180 for an example with a variation of 10% less in the value of the resistor R, the Table 5.3 is obtained. Table 5.3 Results from simulation of the application to a DC-DC converter. Control law mu Volume (det−1/2) Nominal case 0.1137 393.4204 10% less R variation 0.1180 394.6410 In this table it is possible to observe that the volume, expressed in term of det(P)−1/2 , of the set Ais practically the same in the nominal case and with variations. The evolution of the error trajectory xand the set Ais showed in Fig. 5.4. 5.2 Control Laws for the Usual Discrete-Time Formulation of Switched Affine Systems 91 Figure 5.4 Evolution of the error trajectory and the set A. 92 Chapter 5. Control of Switched Affine Systems 5.3 Conclusions In this chapter, several controllers for switched affine systems have been presented. Two for systems with high-frequency sampling time and two for an usual discrete-time formulation made to improve the previous formulation. Therefore, in the first instance two main contributions have been presented to control switched affine systems with high-frequency sampling time. The first one deals with the definition of accurate discrete-time model for high-frequency sampling DC-DC converters. The second contribution consists in the extension of the usual Lyapunov-based control laws employed in this domain to a less restrictive control law that encompass this first formulation. This new control law delivers notable improvements with respect to the Lyapunov-based control law in terms when comparing the estimate of the set E of the switched affine system. An usual discrete-time formulation has been proposed, as alternative to the previous formulation, that have some advantages. In this way, the matrix is the same to define the attractor set and the used in the control law, avoiding some possible situations of instability. In this new formulation, the centre of the ellipsoid that define this attractor do not have to be the origin, reducing its volume. Another improve respect to the previous formulation is in the iterative process to search the optimal value of the parameters µ and γ due to that the new formulation only use the value of one parameter ( µ ). The main result presented provides a relaxed control which is not based on the computation of the Lyapunov function as usually considered in the literature. It is demonstrated, by theoretical and numerical validations, that the solution of the optimization problem provided in [ 86 ] is included in this proposed solution. Numerical applications even show a notable improvement of the guarantees on an example. Even so, the results in comparison with the control laws presented for high frequency sample time do not show an improvement due to numerical problems when the parameters of the converter are used. This fact can be observed in the Table 5.4, where the value of det(P)−1/2 is shown for the proposed control laws. In this table it is also possible to observe that the control method of (5.15) does not have solution for T= 10−5 and T= 10−6 showing the difficulty to solve the LMI for high frequency systems due to numerical problems. A possible solution to this may be the use of δ operator in conjunction with the usual discrete-time formulation. Besides, the potential of this last method compared with the existing solution from the literature is the possibility to apply the same control design methodology in the case of uncertain systems, which is not straightforward using Lyapunov matrix-based control laws 5.3 Conclusions 93 because it requires the exact knowledge of the system matrices. The “relative simplicity” of the proposed analysis has, indeed, the price of introducing some degree of conservatism. Table 5.4 Comparison results from the application to a DC-DC converter. Volume (det(P)−1/2) Period C1 (5.4) C2 (5.8) Nominal Case (5.15) T=10−4369.9298 245.9012 393.4204 T=10−523.7921 23.5335 - T=10−62.3222 2.2996 - 6 Conclusions and Future Work One approaches the journey’s end. But the end is a goal, not a catastrophe. George Sand Contents 6.1. Thesis contributions and conclusions 95 6.2. Future work 97 Th is thesis has addressed the control of power electronic converters. On the one hand, the first goal has been the control of the voltage balance in the capacitors of a three-level NPC. In the other hand, two design methods are presented for control the output voltage of a DC-DC converter. The next section explain the thesis contributions and the methods used to reach the objectives. At the end of the chapter some future works are proposed. 6.1 Thesis contributions and conclusions In the first part of this thesis, the model of a three-level NPC converter has been revisited. This model is an average model where the control signals have been expressed as averaged 95 96 Chapter 6. Conclusions and Future Work duty ratios of each level in each phase. This model is not a contribution of this thesis but it has been used to design several new control laws. The main objective of all of this control laws is the voltage balance in the capacitors of the dc-link, taking into account the power or current controllers and the total dc-link voltage control. Thus, three approaches have been presented and compared with the existing technique mVSVPWM. It is important to remember that the first approach (ICM1) was theoretically proposed in a previous work [ 44 ] and in this thesis it has been implemented experimentally. The results of the comparison allow to observe that the THD values obtained in the three proposed variants are similar or better to the mVSVPWM technique. The first two variants improve in simplicity, expressed in the reduction of computational burden, at the cost of a higher number of commutations. This fact is solved in the third variant, where although the computational burden does not decrease so much, the number of commutations is reduced considerably. Regarding the balancing time, again the first two variants are a bit slow achieving the voltage balance in the capacitors, being the third one even faster than mVSVPWM. It should be remembered that the first two variants present a trade-off between balancing speed and transient behaviour, expressed in the modification of some control parameters, which could improve the speed of the voltage balance. As result of the comparison between all the techniques implemented, it can be seen that the first proposed variant (ICM1), even though it is the simplest one, the worsening of THD, number of commutations and balance time is not compensated by the improvement in computational load. However, the modifications made from this technique in the second variant (ICM2) and the proposal of the third one (Variant 3), show very promising results with respect to the rest of the techniques. In the second part of the thesis, the DC-DC converter is modelled as switched affine system due to its hybrid behaviour. In this type of systems, stability to a desired equilibrium point is not possible and the chattering around that point is an effect to mitigate, decreasing the attractor set where the system converges to. Several control design methods have been presented to achieve this objective. Two for systems with high frequency sampling time and two for an usual discrete-time formulation considered for improving the previous ones. Therefore, in the first instance two main contributions have been presented to control switched affine systems with high frequency sampling time using the δ operator. The first one deals with the definition of accurate discrete-time model for high frequency sampling DC-DC converters where the control is based in the Lyapunov function. The second contribution consists in the extension of the usual Lyapunov-based control laws to a less restrictive control law that encompass this first formulation. This new control law delivers notable improvements with respect to the Lyapunov-based control law when comparing the estimate of the attractive set Eof the system. 6.2 Future work 97 In the case of the usual discrete-time formulation, the main result presented provides a relaxed control which is not based on the computation of the Lyapunov function as usually considered in the literature. It is demonstrated, by theoretical and numerical validations, that the solution of the optimization problem provided in [ 86 ] is included in this proposed solution. Numerical applications show the improvement of this methods on the examples. Even so, the results in comparison with the control laws presented for high frequency sample time do not show an improvement due to numerical problems when the parameters of the converter are used. A possible solution to this is outlined in the next section as a future work to do. Besides, the potential of this last method compared with the existing solution from the literature is the possibility to apply the same control design methodology in the case of uncertain systems, which is not straightforward using Lyapunov matrix-based control laws because it requires the exact knowledge of the system matrices. The “relative simplicity” of the proposed analysis has, indeed, the price of introducing some degree of conservatism. 6.2 Future work Some challenging reach lines are still able to be addressed: •Multilevel Converters The control laws presented in the first part of this thesis have been developed for three-level converters, however, it is possible to adapt them to more level systems. In fact, some of them are already been studied and experimentally implemented in a five-level NPC converter [ 92 ]. This is a challenge from the point of view of the control of this type of converters. In fact, due to the difficulty presented to design controllers in more than three levels, another methods could to be used. In this sense, a new control method would compute the on-off values of the switching devices as a mixed-integer linear optimization problem. This optimal switching sequence is computed offline based on normalized values for a given operation point at steady state. A grid period is simulated and the resulting optimal switching sequence is stored in a table. Afterwards, the modulator can look for the more similar situation to the stored ones in the table and apply its switching criteria. In this way, an optimal modulation is computed offline and integrated with very low computational burden. Alternatively, instead of focusing on one operation point, an optimal modulation law can be derived from the data obtained for several operational points. To do 98 Chapter 6. Conclusions and Future Work so, different operation points are simulated and their resulting switching sequences are obtained. Several normalized state variables are used as inputs to distinguish the different switching sequences obtained as outputs. Thus, classification and regression trees are trained with this data, resulting in a simpler way to implement the optimal sequences from the state variables. • Switched Affine Systems In section 5.2.3 it has been shown as the usual discrete-time formulation present numerical problems in the DC-DC converter application when using high-frequency sampling times. It has even been seen that for very small values of the sampling time, the designed method does not find a solution to the LMI. A possible solution to these numerical problems is the use of the δ operator in conjunction with this model formulation. With this new alternative, it is expected to improve the volume of the attractor set Aof the application example. All the control design methods developed to switched affine systems have been applied to DC-DC converters in this thesis. A possible future work in this sense is to extend this methods to other type of converters like the three-level NPC. This future work will surely present the same difficulty that the DC-DC converters respect to numerical problems mentioned before since the sampling time must be very small. To avoid these problems, the same solution indicated above could be used. A.3 Design and Assembly 105 converter are several: • The possibility of creating the converter model and its control strategy using Simulink. • The option to build and automatically download an application in real time from Simulink to the processor. • Adjust controller parameters, monitor the process and store data in real time during the execution of an experiment. • Work at high sampling frequencies, which is important when working with power electronics applications. The processor is configured with an Intel Core i7 3.5 Ghz processor and a 75 MHz FPGA module that has 128 inputs/outputs. 24 of these outputs will be used to send the control signals to the actuators and 6 inputs will be used to send possible error signals to the processor. In Fig. A.5, the real-time machine is shown. To transmit the control signals from the processor, optical fiber have been used. In power converters, common mode voltages can produce enough noise to affect the control signals. For this reason the optical fiber has been used, which is immune to this noise. In this way, the control signal calculated by the processor reaches the conversion board through the Sub-D terminal in a range of 0 to 5 volts and is transformed into a light signal that reaches the actuators through the optical fiber cable. In Fig. A.6 it is possible to see the conversion circuit. Figure A.6 Circuit to adapt votlage signal to optical fiber. 106 Chapter A. Design and Construction of a Experimental Prototype Power Converter Switching elements As switching element, IGBT transistors have been used. These transistors are semiconductor devices that act as a switch controlled by a control signal. The model used in the converter is the SKM100GB12V of the brand Semikron .These IGBTs that support a maximum voltage of 1200 volts have been selected due to the fact that the working voltage in the dc-link will be about 800 volts. The IGBTs are encapsulated in pairs as shown in Fig. A.7. Figure A.7 IBGT by Semikron. Inside these IGBT modules are also switching diodes, which are of vital importance since they are responsible for setting the block voltages of the switches at a fraction of the dc-link voltage. These diodes have fast recovery and must support the nominal voltage of the converter, so modules that support up to 100 amps have been chosen. Once the control signal has been sent, calculated by the Speedgoat, through optical fiber, it is necessary to perform another adaptation of the signal when reaches the IGBT. This new adaptation is made in the circuit shown in Fig. A.8. In this circuit, the signal coming from the optical fiber is read and the IGBTs are triggered through the drivers. These drivers of the brand Semikron and model Skyper 32 PRO R, have the characteristic of switching each IGBT module independently. In addition, they incorporate protection against shortcircuit and soft shutdown. An important characteristic is that they do not introduce dead times between commutations, so in order to avoid shortcircuits in the commutations it will be necessary to produce these dead times from the real-time computer. Snubber Capacitors They are high frequency response capacitor devices. These devices are in parallel with the IGBTs and serve to reduce the electrical stress of these elements, avoiding voltage peaks when performing the commutations. A.3 Design and Assembly 107 Figure A.8 Circuit to adapt the signal from optical fiber cable to the IGBT module. Fans and Heatsinks After carrying out a thermal study on the converter, maximum temperatures were obtained in the IGBT modules of 147 ◦ C, for a simulation with test currents of 15 A and reference voltage in the dc-link of 800 V. For the chosen models of IGBT modules and diodes, the maximum working temperature is 150 ◦ C. In order to make the converter work with favorable thermal conditions or in the case of working with higher currents or voltages, it was decided to include heatsinks for every three IGBT modules. The heatsink P3 / 300B of the brand Semikron was selected with an axial fan at one of its ends. This heatsink is specially designed for the assembly of the IGBT modules. As a result of the simulation including these heatsinks and for an ambient temperature of 40 ◦ C, a maximum sink temperature of 95.75 ◦ C was obtained, with the final temperature in the IGBT module of 114.55 ◦C. Contactor For security reasons, a contactor has been placed at the input of the converter. In this way it is possible to disconnect the power supply if necessary. This contactor of the brand Lovato, supports a power of 15 KW. In addition to that contactor, another one with the same characteristics has been placed to switch to a converter preload circuit. The installed capacitors must not be subjected to sudden voltage changes, so before establishing a high voltage reference, a controlled preload is made by an external circuit to the converter at the beginning of the experiments. 108 Chapter A. Design and Construction of a Experimental Prototype Power Converter Once this preload is done, the contactor connects the converter directly to the grid and disconnects the external circuit. A.3.2 Assembly Figure A.9 Five-level converter. In Fig. A.9, the five-level converter with all its elements is shown. The structure in which the converter has been assembled has a height of 1.8 meters, 60 cm wide and 60 cm deep. This structure has metal panels on all sides as well as a door on the front. For security, a methacrylate structure surrounding the converter has also been installed. The converter has been assembled so that each of the three central trays of the structure correspond to each of the phases of the supply a,b and c shown in the figures A.1 and A.2. In Fig. A.10, the construction of each tray can be observed in detail. It can be seen A.3 Design and Assembly 109 that the connections of the capacitors and IGBTs have been established, using aluminum plates, in three different planes separated by an insulating layer. In this figure you can also see the arrangement of different elements described in previous sections. The filter coils in the supply have been placed in the lower tray next to the current sensors, while the Speedgoat and the voltage sensors have been placed in the upper tray next to the power supplies of the electronics parts. Adaptation circuit Capacitors IGBTs Snubber capacitors Fan + heatsinks Balancing resistance Non-conductor layer Figure A.10 Tray of components in detail. 110 Chapter A. Design and Construction of a Experimental Prototype Power Converter A.3.3 Future Work In the future, it is planned to install a network of contactors so that the converter can be switched quickly and automatically between rectifier and inverter mode. For this, a circuit formed by 10 contactors has already been designed. This network of contactors will be controlled by the digital outputs of the real-time machine. Future extensions include the use of photovoltaic panels emulators and a three-phase motor as power supply of the converter in inverter mode, as well as the use of a non-linear load. List of Figures 2.1. Carrier signals: Trailing edge (left), triangular (center) and leading edge (right) 11 2.2. Output voltage generated by PWM 12 2.3. Space Vector hexagon 13 2.4. Simplification of the three-level Space Vector hexagon diagram 14 2.5. Squematic diagram of the three-phase three-level NPC rectifier 15 2.6. Switching states for phase a 16 3.1. Complete schematic block diagram of the controllers 31 3.2. Graphical representation of the limits of each case 35 3.3. Instantaneous representation of ua,uband ucas a function of xvalue 39 3.4. Evolution of the reference voltage (top) and the resistive load (bottom) under the simulations 43 3.5. Simulation results: evolution of the instantaneous active power p(solid) and its reference value pr(dashed), considering ICM1 (top), ICM2 (mid-up), Variant 3 (mid-down) and mVSVPWM (bottom) through the different stages of Fig. 3.4 44 3.6. Simulation results: evolution of the total dc-link voltage vdc (solid) and its reference value vr dc (dashed), considering ICM1 (top), ICM2 (mid-up), Variant 3 (mid-down) and mVSVPWM (bottom) through the different stages of Fig. 3.4 45 3.7. Simulation results: evolution of the capacitor voltages starting from an unbalanced condition, considering ICM1, ICM2, Variant 3 and mVSVPWM. (solid) balancing control activated; (dashed) no balancing control; (dash-dotted) reference voltage 46 3.8. Simulation results: three-phase grid current considering ICM1 (top), ICM2 (midup), Variant 3 (mid-down) and mVSVPWM (bottom). vr dc = 800 V and R= 60Ω47 111 112 List of Figures 3.9. Simulation results: Capacitor voltages (bottom) starting from an unbalanced condition when phase currents (top) are distorted, considering ICM1, ICM2, Variant 3 and mVSVPWM 47 3.10. Simulation results: duty cycles of phase aconsidering ICM1 (top), ICM2 (mid) and Variant 3 (bottom) 48 3.11. Simulation results: switching states of phase aand its averaged signal, considering ICM1 (top), ICM2 (mid-up), Variant 3 (mid-down) and mVSVPWM (bottom) 49 3.12. Experimental prototype of the three-level NPC rectifier 50 3.13. Experimental results: evolution of the instantaneous active power p(solid) and its reference value pr(dashed), considering ICM1 (top), ICM2 (mid-up), Variant 3 (mid-down) and mVSVPWM (bottom) through the different stages of Fig. 3.4 51 3.14. Experimental results: evolution of the total dc-link voltage vdc (solid) and its reference value vr dc (dashed), considering ICM1 (top), ICM2 (mid-up), Variant 3 (mid-down) and mVSVPWM (bottom) 52 3.15. Experimental results: evolution of the capacitor voltages starting from an imbalanced condition, considering mVSVPWM, ICM1, ICM2 and Variant 3. The dashed lines refers to no-balancing control and the dash-dotted to the capacitor voltage reference 52 3.16. Experimental results: 3-phase grid currents considering ICM1 (top), ICM2 (midup), Variant 3 (mid-down) and mVSVPWM (bottom). vr dc = 800 V and R= 60Ω53 3.17. Experimental results: Harmonic spectrum of the current of phase afor the three approaches considered: ICM1, ICM2, Variant 3 and mVSVPWM 54 3.18. Experimental results: switching states of phase a(solid) and its averaged value (dashed), considering ICM1 (top), ICM2 (mid-up), Variant 3 (mid-down) and mVSVPWM (bottom) 54 3.19. Experimental results: duty cycles of phase aconsidering ICM1 (top), ICM2 (mid) and Variant 3 (bottom) 55 4.1. Schematic diagram of a boost converter 65 5.1. Numerical results of Proposition 1. Time trajectories (green), set E(yellow) and δV > 0(red) 74 5.2. Simulation results of uncertain switched affine system (4.7),(5.35) for three different values of ¯ δ, from top to bottom. From left to right, the figure shows the evolution of the state variables (x1,x2), the control input σand the Lyapunov function V(x,xc)(in a logarithmic scale), with respect to time. The last column shows the trajectories of the state in the phase portrait 88 List of Figures 113 5.3. Evolution of (det(P))−1 2with unstructured matrices Ni’s (solid) in (5.34), and with the Lyapunov matrix-based control law (5.27) (dashed) 89 5.4. Evolution of the error trajectory and the set A91 A.1. Circuit of the five-level diode-clamped 100 A.2. Schematic of the five-level diode-clamped converter in rectifier mode 101 A.3. Measuring circuit and adaptation of voltage sensors 103 A.4. Current sensors and adaptation circuit 104 A.5. Speedgoat real time machine 104 A.6. Circuit to adapt votlage signal to optical fiber 105 A.7. IBGT by Semikron 106 A.8. Circuit to adapt the signal from optical fiber cable to the IGBT module 107 A.9. Five-level converter 108 A.10. Tray of components in detail 109 Bibliography 121 [40] Z. Pan and F. Z. Peng, “A sinusoidal PWM method with voltage balancing capability for diode-clamped five-level converters,” IEEE Transactions on Industry Applications, vol. 45, no. 3, pp. 1028–1034, 2009. [41] S. L. Capitaneanu, B. De Fornel, M. Fadel, J. Faucher, and A. Almeida, “Graphical and algebraic synthesis for PWM methods,” EPE Journal (European Power Electronics and Drives Journal), 2001. [42] L. M. D. Jimena, C. M. G. Alberto, D. C. J. Oscar, and G. L. C. Alberto, “Modulación PWM aplicada a inversores trifásicos dentro del esquema de accionamientos eléctricos AC,” DEIC-FIET, 2007. [43] Z. B. Mahmoud, M. Hamouda, and A. Khedher, “A comparative study between the Nearest Three Vectors and two-level hexagons based space vector modulation algorithms for three-level NPC inverters,” International Journal of Renewable Energy Research, vol. 7, no. 3, pp. 1074–1084, 2017. [44] F. Umbria, F. Gordillo, and F. Salas, “Model-based NPC Converter Regulation for Synchronous Rectifier Applications,” Proceedings, IECON 2014 - 40th Annual Conference of the IEEE Industrial Electronics Society, pp. 4669–4675, oct 2014. [45] S. Alepuz, S. Busquets-Monge, J. Bordonau, J. Gago, D. González, and J. Balcells, “Interfacing Renewable Energy Sources to the Utility Grid Using a Three-Level Inverter,” IEEE Trans. Ind. Electron., vol. 53, no. 5, pp. 1504–1511, oct 2006. [46] Q. Yan, Kai and Wang, Wei and Zhu, Zhongni and lu, “Study on neutral-point balancing for three-level space voltage vector pulse-width modulation inverter,” in 2008 International Conference on Electrical Machines and Systems, 2008, pp. 1571– 1576. [47] R. Krishna, D. E. Soman, S. K. Kottayil, and M. Leijon, “Pulse delay control for capacitor voltage balancing in a three-level boost neutral point clamped inverter,” IET Power Electronics, vol. 8, no. 2, pp. 268–277, 2015. [48] A. Von Jouanne, S. Dai, and H. Zhang, “A multilevel inverter approach providing DC- link balancing, ride-through enhancement, and common-mode voltage elimination,” IEEE Transactions on Industrial Electronics, vol. 49, no. 4, pp. 739–745, 2002. [49] S. Gauthier and F. Okou, “Transformer-less five-level diode-clamped converter based active power filter with auxiliary balancing circuit,” in CCECE 2010. IEEE, may 2010, pp. 1–5. 122 Bibliography [50] H. Hotait, A. Massoud, S. Finney, and B. Williams, “Capacitor voltage balancing using redundant states of space vector modulation for five-level diode clamped inverters,” IET Power Electronics, vol. 3, no. 2, p. 292, 2010. [51] B. Omri, K. Ammous, and A. Ammous, “New Method for Balancing Capacitors Voltages in NPC Inverter without DC-link Voltages Sensors,” International Journal of Computer Applications, vol. 65, no. 22, pp. 17–24, 2013. [52] A. Choudhury, P. Pillay, and S. S. Williamson, “DC-Bus Voltage Balancing Algorithm for Three-Level Neutral-Point-Clamped (NPC) Traction Inverter Drive With Modified Virtual Space Vector,” IEEE Transactions on Industry Applications, vol. 52, no. 5, pp. 3958–3967, sep 2016. [53] S. Busquets-Monge, J. Bordonau, D. Boroyevich, and S. Somavilla, “The Nearest Three Virtual Space Vector PWM - a Modulation for the Comprehensive Neutral- Point Balancing in the Three-Level NPC Inverter,” IEEE Power Electron. Lett., vol. 2, no. 1, pp. 11–15, mar 2004. [54] S. R. Pulikanti, M. S. A. Dahidah, and V. G. Agelidis, “Voltage Balancing Control of Three-Level Active NPC Converter Using SHE-PWM,” IEEE Transactions on Power Delivery, vol. 26, no. 1, pp. 258–267, jan 2011. [55] F. Umbría, S. Vazquez, F. Gordillo, and F. Gómez-Estern, “Observer-based Direct Power Control for three-level NPC rectifiers,” undefined, 2009. [56] F. Grimm, Z. Zhang, M. Abdelrahem, and R. Kennel, “Computationally efficient predictive control of three-level NPC converters with DC-link voltage balancing: A priori state selection approach,” in 2017 IEEE International Symposium on Predictive Control of Electrical Drives and Power Electronics (PRECEDE). IEEE, sep 2017, pp. 72–77. [Online]. Available: http://ieeexplore.ieee.org/document/8071271/ [57] N. Celanovic and D. Boroyevich, “A Fast Space-Vector Modulation Algorithm for Multilevel Three-Phase Converters,” IEEE Transactions on Industry Applications, vol. 37, no. 2, pp. 637–641, 2001. [58] W. Yao, H. Hu, and Z. Lu, “Comparisons of Space-Vector Modulation and Carrier- Based Modulation of Multilevel Inverter,” IEEE Transactions on Power Electronics, vol. 23, no. 1, pp. 45–51, 2008. [59] Sanmin Wei, Bin Wu, Fahai Li, and Congwei Liu, “A general space vector PWM control algorithm for multilevel inverters,” in Eighteenth Annual IEEE Applied Bibliography 123 Power Electronics Conference and Exposition, 2003. APEC ’03., vol. 1. IEEE, 2003, pp. 562–568. [Online]. Available: http://ieeexplore.ieee.org/document/1179268/ [60] F. Umbría, F. Gordillo, and F. Salas, “Modeling and Full Decoupling Control of a Grid-Connected Five-Level Diode-Clamped Converter,” Electric Power Components and Systems, 2016. [61] R. Teodorescu, F. Blaabjerg, M. Liserre, and P. Loh, “Proportional-resonant controllers and filters for grid-connected voltage-source converters,” IEE Proceedings - Electric Power Applications, vol. 153, no. 5, p. 750, 2006. [62] J. Rodriguez, S. Bernet, P. K. Steimer, and I. E. Lizama, “A Survey on Neutral-Point- Clamped Inverters,” IEEE Transactions on Industrial Electronics, vol. 57, no. 7, pp. 2219–2230, jul 2010. [63] S. Vazquez, J. a. Sanchez, J. M. Carrasco, J. I. Leon, and E. Galvan, “A Model-Based Direct Power Control for Three-Phase Power Converters,” IEEE Transactions on Industrial Electronics, vol. 55, no. 4, pp. 1647–1657, apr 2008. [64] M. Malinowski, M. Jasin, and M. P. Kazmierkowski, “Simple Direct Power Control of Three-Phase PWM Rectifier Using Space-Vector,” IEEE Transactions on Industrial Electronics, vol. 51, no. 2, pp. 447–454, apr 2004. [65] P. Antoniewicz and M. Kazmierkowski, “Virtual-Flux-Based Predictive Direct Power Control of AC/DC Converters With Online Inductance Estimation,” IEEE Transactions on Industrial Electronics, vol. 55, no. 12, pp. 4381–4390, dec 2008. [66] J. Steinke, “Switching frequency optimal PWM control of a three-level inverter,” IEEE Transactions on Power Electronics, vol. 7, no. 3, pp. 487–496, jul 1992. [67] A. Videt, P. Le Moigne, N. Idir, P. Baudesson, and X. Cimetière, “A new carrierbased PWM providing common-mode-current reduction and DC-bus balancing for three-level inverters,” IEEE Transactions on Industrial Electronics, 2007. [68] C. B. Jacobina, A. M. N. Lima, E. R. C. Da Silva, R. N. C. Alves, and P. F. Seixas, “Digital scalar pulse-width modulation: A simple approach to introduce non-sinusoidal modulating waveforms,” IEEE Transactions on Power Electronics, 2001. [69] I. Lopez, S. Ceballos, J. Pou, J. Zaragoza, J. Andreu, I. Kortabarria, and V. G. Agelidis, “Modulation Strategy for Multiphase Neutral-Point-Clamped Converters,” IEEE Transactions on Power Electronics, 2016. 124 Bibliography [70] R. Maheshwari, S. Munk-Nielsen, and S. Busquets-Monge, “Neutral-Point Current Modeling and Control for Neutral-Point Clamped Three-Level Converter Drive with Small DC-link Capacitors,” in 2011 IEEE Energy Conversion Congress and Exposition. IEEE, 2011, pp. 2087–2094. [71] G. Escobar, A. Stankovic, J. Carrasco, E. Galvan, and R. Ortega, “Analysis and design of direct power control (DPC) for a three phase synchronous rectifier via output regulation subspaces,” IEEE Transactions on Power Electronics, vol. 18, no. 3, pp. 823–830, 2003. [72] R. Goebel, R. G. Sanfelice, and A. R. Teel, “Hybrid dynamical systems,” IEEE Control Systems, vol. 29, no. 2, pp. 28–93, 2009. [Online]. Available: https://ieeexplore.ieee.org/document/4806347/ [73] C. Albea, G. Garcia, and L. Zaccarian, “Hybrid dynamic modeling and control of switched affine systems : application to DC-DC converters,” in 54th IEEE Conference on Decision and Control, 2015, pp. 2264–2269. [74] D. Liberzon and A. S. Morse, “Basic Problems in Stability and Design of Switched Systems,” IEEE Control Systems, vol. 19, no. 5, pp. 59–70, 1999. [75] R. A. Decarlo, M. S. Branicky, S. Pettersson, and B. Lennartson, “Perspectives and results on the stability and stabilizability of hybrid systems,” Proceedings of the IEEE, vol. 88, no. 7, pp. 1069–1082, 2000. [76] D. Liberzon, Switching in systems and control. Birkhauser, 2003. [77] G. S. Deaecto, J. C. Geromel, F. S. Garcia, and J. A. Pomilio, “Switched affine systems control design with application to DC-DC converters,” pp. 1201–1210, 2010. [78] L. Hetel and E. Bernuau, “Local Stabilization of Switched Affine Systems,” IEEE Transactions on Automatic Control, vol. 60, no. 4, pp. 1158–1163, 2015. [79] P. Hauroigne, P. Riedinger, and C. Iung, “Switched affine systems using sampled-data controllers: Robust and guaranteed stabilization,” IEEE Transactions on Automatic Control, vol. 56, no. 12, pp. 2929–2935, 2011. [80] C. Albea Sanchez, G. Garcia, H. Sabrina, W. Heemels, and L. Zaccarian, “Practical stabilisation of switched affine systems with dwell-time guarantees,” IEEE Transactions on Automatic Control, pp. 1–1, 2019. Bibliography 125 [81] P. Bolzern and P. Colaneri, “Switched periodic systems in discrete time: Stability and input-output norms,” International Journal of Control, vol. 86, no. 7, pp. 1258–1268, 2013. [82] L. Hetel and E. Fridman, “Robust sampled-data control of switched affine systems,” IEEE Transactions on Automatic Control, vol. 58, no. 11, pp. 2922–2928, 2013. [83] B. L. Eidson, J. Y. Hung, and R. M. Nelms, “An experimental evaluation of the PID controller represented by the delta operator,” in Conference Proceedings - IEEE SOUTHEASTCON, 2012. [84] K. Viji, A. Kumar, and R. Nagaraj, “Improved Delta Operator based Discrete Sliding Mode Fuzzy Controller for Buck Converter,” Indian Journal of Science and Technology, vol. 10, no. 25, pp. 1–11, 2017. [85] G. S. Deaecto, M. Souza, and J. C. Geromel, “Discrete-time switched linear systems state feedback design with application to networked control,” IEEE Trans. on Automatic Control, vol. 60, no. 3, pp. 877–881, 2015. [86] G. S. Deaecto and J. C. Geromel, “Stability Analysis and Control Design of Discrete- Time Switched Affine Systems,” IEEE Transactions on Automatic Control, 2017. [87] R. Middleton and G. Goodwin, “Improved finite word length characteristics in digital control using delta operators,” IEEE Transactions on Automatic Control, vol. 31, no. 11, pp. 1015–1021, nov 1986. [Online]. Available: http://ieeexplore.ieee.org/document/1104162/ [88] C. Edwards and S. K. Spurgeon, Sliding mode control : theory and applications. [89] S. Pettersson and B. Lennartson, “Stabilization of hybrid systems using a minprojection strategy,” in Proceedings of the 2001 American Control Conference, 2001, pp. 223–228 vol.1. [Online]. Available: http://ieeexplore.ieee.org/document/945546/ [90] M. C. Grant and S. P. Boyd, “Graph Implementations for Nonsmooth Convex Programs,” in Recent Advances in Learning and Control. London: Springer London, 2008, pp. 95–110. [Online]. Available: http://link.springer.com/10.1007/ 978-1-84800-155-8{_}7 [91] M. Grant and S. Boyd, “CVX: Matlab software for disciplined convex programming, version 2.1,” 2014. [92] P. Montero-Robina, F. Umbria, F. Salas, and F. Gordillo, “Integrated Control of 126 Bibliography Five-Level Diode-Clamped Rectifiers,” IEEE Transactions on Industrial Electronics, vol. 66, no. 9, pp. 6628–6636, 2019. [93] F. Umbría, F. Gordillo, and F. Salas, “A controller for practical stability of capacitor voltages in a five-level diode-clamped converter,” European Journal of Control, vol. 28, pp. 56–68, mar 2016. Bibliography 127