High-performance ΣΔ ADC for ADSL applications in 0.35μm CMOS digital technology

A HIGH-PERFORMANCE SIGMA-DELTA ADC FOR ADSL APPLICATIONS IN 0.35pm CMOS DIGITAL TECHNOLOGY R. del Rio, J.M. de la Rosa, F. Medeiro, B. PCrez-Verdu, and A. Rodriguez-Vazquez lnstituto de Microelectronica de Sevilla - CNM-CSIC Edificio CICA-CNM, C/Tarfia s/n, 4 10 12- Sevilla, SPAIN Phone: +34 95 5056666, Fax: +34 95 5056686, E-mail: [email protected] ABSTRACT: We present a Sigma-Delta modulator designed for ADSL applications in a 0.3Spm CMOS pure digital technology. It employs a 4th-order 3-stage cascade architecture including both single-bit and multi-bit quantizers with programmable resolution, which allows us to use only 16 oversampling ratio. Especial emphasis is placed on technology issues, namely: poor analog performance and substrate coupling. The measured performances are 13-bit dynamic range operating at 2MS/s and 12-bit dynamic range operating at 4MS/s. The modulator consumes 77mW from a 3.3-V supply and occupies 1.32 mm2. 1. INTRODUCTION The connection in cascade of low-order EA modulators (CAMS) to build high-order, unconditionally stable architectures, ofien in combination with robust, calibration-free, multi-bit quantization, has been proven to be a good alternative to achieve the requirements of the xDSL ADCs [ 11-[6]. A claimed drawback of these architectures is that they are suitable only in moderate sub-micron analog technologies where the good matching of passive devices, chiefly capacitors, and the obtainable performance of the analog cells, make them power-efficient in comparison with other =-based architectures or other types of ADCs. In this context, this paper demonstrates that, through a careful design, the above topologies can also be efficiently implemented in a 0.35pm pure digital CMOS technology. The CAM presented here uses a 4th-order 3-stage cascade multi-bit architecture - the 2-12mb modulator [ 11 shown in Fig.1. A detailed discussion on the benefits of the selected topology, as well as on the selection of integrator weights (summarized in Table 1) can be found in [7]. I Cancellation Logic - Fig. I. Block diagram of the 2-12mb W. The paper is organized as follows. Section 2 covers the synthesis of the 2-I2mb modulator. Sections 3 describes the design of the modulator building blocks. Finally, Section 4 is dedicated to layout and measurement results. 2. MODIJLATOR SIZING The evaluation of the circuit requirements for the 2-I2mb ZAM has been done using SDOPT [8], a sizing tool for SC ZAMs. This tool combines accurate analytical expressions for each error contribution degrading the modulator performance and statistical optimization, which allows us to find optimized, non-oversized specifications for the building blocks. Table 2 summarizes the circuit requirements providing 14bit@4MS/s. Most significant error contributions are also shown. Note that quantization noise is the main in-band error source (-85dB). The requirements in Table 2 for the integrator and the amplifier apply only to the first integrator in the cascade. However, some specifications, as amplifier DC-gain, transconductance and output current, can be relaxed for the second, third, and fourth integrator, because their in-band error power contributions are attenuated by increasing powers of the oversampling ratio. The same applies for thermal noise, which allows reduction of the unitary capacitor from O.5pF to 0.25pF for these integrators. Fig2 shows the fully differential SC implementation of the 2-12mb XAM. The first stage is formed by two SC integrators, with one and two input branches, respectively. A single-bit quantizer (comparator) at the end of the first stage, together with two AND gates, provides the feedback signals A ,BE to switch the integrator sampling capacitors to either Vr+ = +lV or Vr- = -lV. Since the circuit is fully differential, the resulting reference voltages are f2V. The second stage has a two-branch integrator. Although three different weights are needed in this integrator - g, , 8,' , and g," - weight values in Table 1 allow splitting g3 between the two branches. The same applies for weight g4 in the fourth integrator. This integrator drives a programmable ADC, whose resolution can be switched between 2 and 4bit for exploration purposes. The third-stage loop is closed through the DAC. The 1-of-16 (4-bit) output code of the last-stage ADC (alternatively 1-of-8 in the 3-bit mode or 1-of-4 in the 2-bit mode) is converted to binary code using a ROM memory, providing outputs Y3,0-3 (alternatively Y3,0-2 or y3,0-1). (*) This work has been supported by the ESPRIT Project 29261 MIXMODEST 0-7803-7057-0/01/$10.00 02001 IEEE. 501 Table 1. Integrator weights for the 2-12mb ,?AM. SPECS: I4bit@4MS/[email protected] Oversampling ratio Modulator Sampling frequency Sampling capacitor Unitary capacitor Reference voltages Table 2. Modulator sizing results. 2-12,,,b 16 64MHz if2V 0.5pF 0.5pF Capacitor non-linearity I Sigma Integrators Bottom parasitic capacitor Switch ON-resistance 5 DC-gain DC-gain non-linearity I Opamps Transconductance 2 I- Maximum output current 2 ~ 20% 20%V.* 250R 68dB 2.5mAN k0.95 mP 3ynarnic range rhermal noise -94.8dB ncornplete settling noise -96.9dB 4armonic distortion -99.4dB The modulator is controlled by two non-overlapped clock-phases. The integrator input signals are sampled during phase and the algebraic operations are performed duringQ2. The comparators and the ADC are activated at the end of $2 - using its complementary phase as strobe - to avoid any possible interference at the beginning of In order to attenuate the signal-dependent clock charge injection, delayed versions of the phases, qld and $2d, are also provided. $30 -70 -60 -50 -40 -30 -20 -10 0 (4 Input Amplitude (dBV) y3.c-3 y3 0.2 Y3.0.1 ’D/A+ “U/A- Fig. 2. SC implementation of the 2-12mb ZAM. The modulator has been extensively evaluated in ASIDES [8], a behavioural simulation tool for ZAMs. Fig.3(u) shows the signal-to-(noise+distortion)-ratio SNDR of the modulator as a function of the input level, when operating with different values of the oversampling ratio (M) and the last-stage quantizer resolution (B). The maximum dynamic range DR is 85.5dB. Fig.3(b) shows its output spectrum for a -6dBV@250kHz input tone. $- -100 -120 0.0 0.5 1 .0 1.5 2.0 (B) Frequency (MFIz) Fig. 3. (a) SNDR curves for different M,B pairs, (b) Output spectrum operating with M = 16 and B = 4. 502 3. CIRCUIT DESIGN 3.1 Amplifiers Most important amplifier design aspects are [9]: (a) Required output swing which, with the weights in Table 1, is reduced to only the reference voltages. (b) Open-loop DC-gain: Simulations with ASIDES show that the 68dB requirement can be relaxed for amplifiers in the second, third and fourth integrator to 62dB, 54dB, and 54&, respectively. (c) Dynamics, influenced by the equivalent capacitive load which is different for each integrator and clock phase. A two-stage architecture, shown in Fig.4(u), was selected for OA 1 in order to fulfil its DC-gain requirement. It uses a telescopic first stage and Miller compensation. A single-stage folded-cascode OTA, shown in Fig.4@), has been used in OA2, OA3, and OA4 - enough to accomplish their medium-, low-DC-gain requirements. Although these amplifiers use the same structure, different sizings have been obtained for each of them, in order to fuIfi1 their specifications with a reduced power consumption. The common-mode feedback nets (not shown) are dynamic - neither static consumption nor voltage range problems. The main features of the four amplifiers, sized using FRIDGE [8], are summarized in Table 3. Table 3. Summarized amplifier performance 3.2 Capacitors and switches Unitary capacitors have been implemented with a multi-metal sandwich structure, using the five metal layers available in the intended technology. According to previous measurements, the standard deviation of the matching error is 0.12%. The bottom-plate parasitic 4 capacitor, especially important for dynamic requirements, is between 20% - 40% of the nominal capacitance. Due to the high-speed operation of the UM, finite switch ON-resistance Ron is mainly constricted by dynamic considerations. In our case, Ron in the range of 25052 - 300S2 can be tolerated, with a minor degradation of the modulator performance. This value is not too demanding for a CMOS transfer gate in the 3.3-V supply intended technology, so that clock-boosting stages or similar techniques can be avoided. 3.3 Quantization Blocks Since comparators have to be very fast, although not very precise, a regenerative latch, without pre-amplifying stage is enough to meet the requirements. The same block has been used as the comparator block of the last-stage 4-bit flash ADC, which uses a fully differential SC front-end to compute the difference between the last integrator output signal and the reference signals generated in a resistive ladder. The latter consists of a simple resistor string of 30 unitaries (R = 50Q) connected between the reference voltages Vr+ = + 1 V and Vr- = - 1 V. The same string has been used for the DAC. The value selected for R ensures that settling errors are small enough. Note that we can afford this simple, calibration-free design because cascade multi-bit ZAMs show low sensitivity to the non-idealities of the last-stage quantization blocks [8]. 4. EXPERIMENTAL RESULTS Fig.5 shows the layout of the prototype fabricated in a 0.35~ CMOS digital technology with epi conductive substrate. It includes centroid techniques in matched devices, separate analog, digital and substrate biasing, and an extra supply dedicated to the digital output buffers, in order to be able to reduce this supply without affecting the rest of the circuitry during the test phase, thus lowering the power of the switching noise. The modulator occupies 1 .32m2 without pads and consumes 78.3mW: 60.2mW for the analog blocks, 4.5mW for the digital part, and 13.6mW for the output drivers. The modulator samples were soldered (without socket) on a two-layer PCB, Fig.6, including separate analog and digital planes, de-coupling capacitors in the supply lines and reference voltages, termination resistors for impedance coupling at the digital output lines and ESD protec- V- D T- I I I I I I I Id L Fig. 4. Schematics of the amplifiers: (a) Two-stage amplifier, (b) Folded-cascode OTA. 5 03 -15dBV@103kHz D U Fig. 5. Layout of the 2-12mb ZAM Fig. 6. Two-layer PCB tions. An external 1 st-order low-pass anti-aliasing filter was placed at the modulator input. Fig.7 shows the measured output spectrum of the complete modulator and those corresponding to the first stage (2nd-order) and to the combination of the first and second stages (3rd-order). Note the increase in the order of the shaping of the quantization noise. The measured SNDR vs. input level are shown in Fig3 for two different clock frequencies: 35.2MHz and 64MHz, and constant oversampling ratio = 16. Note that the achieved dynamic range is 8 1 dl3 in the fmt case and it is 6dB smaller in the second. Our measurements show that this degradation is larger the larger the sampling frequency and that the performance improves when the biasing of the output buffers is the switching noise coupled through the highly conductive substrate of the epi technology [lo]. Further results in this respect will be presented at the conference. Nevertheless, with the achieved performance, the modulator here compares favorably with the state-of-the-art modulators in Fig.9, especially because previous results have been achieved in analog technologies. REFERENCES lowered. Because of that, such degradation could be due to [ 11 F. Medeiro, B. PCrez-Verdu and A. Rodriguez-Vizquez: “A 13-bit, 2.2-MS/s, 55-mW Multibit Cascade CA Modulator in CMOS 0.7-pm Single-Poly Technology,” IEEE J. of Solid-State Circuits, vol. 34, pp. 748-760, June 1999. [2] A. M. Marques, V. Peluso, M. S. J. Steyaert, and W. Sansen: “A 15-b Resolution 2-MHz Nyquist Rate AX ADC in a 1 -1m CMOS Technology,” IEEE J. of Solid-State Circuits, vol. 33, pp. 1065-1075, July 1998. [3] Y. Geerts, A. Marques, M. Steyaert, and W. Sansen: “A 3.3-V, 15-bit, Delta-Sigma ADC with a Signal Bandwidth of 1.1 MHz for ADSL Applications,” IEEE J. of Solid-state Circuits, vol. 34, pp. 927-936, July 1999. [4] A.R. Feldman , B. E. Boser, and P. R. Gray: “A I3-Bit, 1.4-MS/s Sigma-Delta Modulator for RF Baseband Channel Applications,” IEEE J. of Solid-State Circuits, vol. 33, pp. 1462-1469, October 1998. o -60 2 a -80 -0 .- - 3 -100 -120 I .‘.I I.. .I ..I .I .I.... ..i - --~ , 0 0.5 1 .o 1.5 2.0 Fig. 7. Measured spectra %O -70 -60 -50 -40 -30 -20 -10 0 Fig. 8. Measured SNDR 1 10-61 . , , , , , , . , , . . . , , , , , , . , , , . , . . I 1.0 1.5 2.0 2.5 3.0 3.5 4.0 DOR (MS/s) Fig. 9. State-of-the-Art high-speed Z4Ms B. Brandt and B. A. Wooley: “A 50-MHz Multibit XA Modulator for 12-b 2-MHz A/D Conversion,” IEEE J. of Solid-State Circuits, vol. 26, pp. 1746- 1756, Dec. 199 1. I. Fujimori, et al.: “A 90dB SNR, 2.5MHz Output Rate ADC using Cascaded Multibit Delta-Sigma Modulation at 8x Oversampling Ratio,” IEEE J. of Solid-state Circuits, vol. 35, pp. 1820-1828, Dec. 2000. R. del Rio, F. Medeiro, B. Perez-Verdu, and A. Rodriguez-Vbzquez: “High-Order Cascade Multibit U Modulators for xDSL Applications,” Proc. In?. Symp. Circuits and Systems, V01.2, pp. 37-40, May 2000. F. Medeiro, B. PCrez-Verdu, and A. Rodriguez-Vazquez: Top-Down Design of High-Performunce Modulators, Kluwer Academic Publishers, 1999. R. del Rio, F. Medeiro, J.M. de la Rosa, B. Perez-Verdu. and A. Rodriguez-Vizquez: “A 14-bit 4-MS/s Multi-bit Cascade SD Modulator in CMOS 0.35-pm Digital Technology,” Proc. Design of Integrated Circuits and Systems Conf., pp. 133-138, November 2000. [IOIX. Aragonts, et al.: Analysis and Solutions for Switching Noise Coupling in Mixed-Signal ICs, Kluwer Academic Publishers, 1999. 504