High-performance ΣΔ ADC for ADSL applications in 0.35μm CMOS digital technology

A HIGH-PERFORMANCE SIGMA-DELTA ADC FOR ADSL APPLICA- TIONS IN 0.35pm CMOS DIGITAL TECHNOLOGY R. del Rio, J.M. de la Rosa, F. Medei o, B. PC ez-Ve du, and A. Rod iguez-Vazquez lns i u o de Mic oelec onica de Se illa - CNM-CSIC Edi icio CICA-CNM, C/Ta ia s/n, 4 10 12- Se illa, SPAIN Phone: +34 95 5056666, Fax: +34 95 5056686, E-mail: [email p o ec ed] ABSTRACT: We p esen a Sigma-Del a modula o designed o ADSL applica ions in a 0.3Spm CMOS pu e digi al echnology. I employs a 4 h-o de 3-s age cascade a chi ec u e including bo h single-bi and mul i-bi quan ize s wi h p og ammable esolu ion, which allows us o use only 16 o e sampling a io. Espe- cial emphasis is placed on echnology issues, namely: poo analog pe o mance and subs a e coupling. The measu ed pe o mances a e 13-bi dynamic ange ope - a ing a 2MS/s and 12-bi dynamic ange ope a ing a 4MS/s. The modula o consumes 77mW om a 3.3-V supply and occupies 1.32 mm2. 1. INTRODUCTION The connec ion in cascade o low-o de EA modula o s (CAMS) o build high-o de , uncondi ionally s able a chi ec u es, o ien in combina ion wi h obus , calib a- ion- ee, mul i-bi quan iza ion, has been p o en o be a good al e na i e o achie e he equi emen s o he xDSL ADCs [ 11-[6]. A claimed d awback o hese a chi ec u es is ha hey a e sui able only in mode a e sub-mic on ana- log echnologies whe e he good ma ching o passi e de ices, chie ly capaci o s, and he ob ainable pe o - mance o he analog cells, make hem powe -e icien in compa ison wi h o he =-based a chi ec u es o o he ypes o ADCs. In his con ex , his pape demons a es ha , h ough a ca e ul design, he abo e opologies can also be e icien ly implemen ed in a 0.35pm pu e digi al CMOS echnology. The CAM p esen ed he e uses a 4 h-o de 3-s age cascade mul i-bi a chi ec u e - he 2-12mb modula o [ 11 shown in Fig.1. A de ailed discus- sion on he bene i s o he selec ed opology, as well as on he selec ion o in eg a o weigh s (summa ized in Table 1) can be ound in [7]. I Cancella ion Logic - Fig. I. Block diag am o he 2-12mb W. The pape is o ganized as ollows. Sec ion 2 co e s he syn hesis o he 2-I2mb modula o . Sec ions 3 desc ibes he design o he modula o building blocks. Finally, Sec ion 4 is dedica ed o layou and measu emen esul s. 2. MODIJLATOR SIZING The e alua ion o he ci cui equi emen s o he 2-I2mb ZAM has been done using SDOPT [8], a sizing ool o SC ZAMs. This ool combines accu a e analy ical exp essions o each e o con ibu ion deg ading he modula o pe o mance and s a is ical op imiza ion, which allows us o ind op imized, non-o e sized speci- ica ions o he building blocks. Table 2 summa izes he ci cui equi emen s p o iding 14bi @4MS/s. Mos sig- ni ican e o con ibu ions a e also shown. No e ha quan iza ion noise is he main in-band e o sou ce (-85dB). The equi emen s in Table 2 o he in eg a o and he ampli ie apply only o he i s in eg a o in he cascade. Howe e , some speci ica ions, as ampli ie DC-gain, ansconduc ance and ou pu cu en , can be elaxed o he second, hi d, and ou h in eg a o , because hei in-band e o powe con ibu ions a e a enua ed by inc easing powe s o he o e sampling a io. The same applies o he mal noise, which allows educ ion o he uni a y capaci o om O.5pF o 0.25pF o hese in eg a o s. Fig2 shows he ully di e en ial SC implemen a ion o he 2-12mb XAM. The i s s age is o med by wo SC in eg a o s, wi h one and wo inpu b anches, espec- i ely. A single-bi quan ize (compa a o ) a he end o he i s s age, oge he wi h wo AND ga es, p o ides he eedback signals A ,BE o swi ch he in eg a o sam- pling capaci o s o ei he V + = +lV o V - = -lV. Since he ci cui is ully di e en ial, he esul ing e e ence ol ages a e 2V. The second s age has a wo-b anch in eg a o . Al hough h ee di e en weigh s a e needed in his in eg a o - g, , 8,' , and g," - weigh alues in Table 1 allow spli ing g3 be ween he wo b anches. The same applies o weigh g4 in he ou h in eg a o . This in eg a o d i es a p og ammable ADC, whose es- olu ion can be swi ched be ween 2 and 4bi o explo a- ion pu poses. The hi d-s age loop is closed h ough he DAC. The 1-o -16 (4-bi ) ou pu code o he las -s age ADC (al e na i ely 1-o -8 in he 3-bi mode o 1-o -4 in he 2-bi mode) is con e ed o bina y code using a ROM memo y, p o iding ou pu s Y3,0-3 (al e na i ely Y3,0-2 o y3,0-1). (*) This wo k has been suppo ed by he ESPRIT P ojec 29261 MIXMODEST 0-7803-7057-0/01/$10.00 02001 IEEE. 501 Table 1. In eg a o weigh s o he 2-12mb ,?AM. SPECS: I4bi @4MS/[email p o ec ed] O e sampling a io Modula o Sampling equency Sampling capaci o Uni a y capaci o Re e ence ol ages Table 2. Modula o sizing esul s. 2-12,,,b 16 64MHz i 2V 0.5pF 0.5pF Capaci o non-linea i y I Sigma In eg a o s Bo om pa asi ic capaci o Swi ch ON- esis ance 5 DC-gain DC-gain non-linea i y I Opamps T ansconduc ance 2 I- Maximum ou pu cu en 2 ~ 20% 20%V.* 250R 68dB 2.5mAN k0.95 mP 3yna nic ange he mal noise -94.8dB nco nple e se ling noise -96.9dB 4a monic dis o ion -99.4dB The modula o is con olled by wo non-o e lapped clock-phases. The in eg a o inpu signals a e sampled du ing phase and he algeb aic ope a ions a e pe - o med du ingQ2. The compa a o s and he ADC a e ac i- a ed a he end o $2 - using i s complemen a y phase as s obe - o a oid any possible in e e ence a he begin- ning o In o de o a enua e he signal-dependen clock cha ge injec ion, delayed e sions o he phases, qld and $2d, a e also p o ided. $30 -70 -60 -50 -40 -30 -20 -10 0 (4 Inpu Ampli ude (dBV) y3.c-3 y3 0.2 Y3.0.1 ’D/A+ “U/A- Fig. 2. SC implemen a ion o he 2-12mb ZAM. The modula o has been ex ensi ely e alua ed in ASIDES [8], a beha iou al simula ion ool o ZAMs. Fig.3(u) shows he signal- o-(noise+dis o ion)- a io SNDR o he modula o as a unc ion o he inpu le el, when ope a ing wi h di e en alues o he o e sampling a io (M) and he las -s age quan ize esolu ion (B). The maximum dynamic ange DR is 85.5dB. Fig.3(b) shows i s ou pu spec um o a -6dBV@250kHz inpu one. $- -100 -120 0.0 0.5 1 .0 1.5 2.0 (B) F equency (MFIz) Fig. 3. (a) SNDR cu es o di e en M,B pai s, (b) Ou pu spec um ope a ing wi h M = 16 and B = 4. 502 3. CIRCUIT DESIGN 3.1 Ampli ie s Mos impo an ampli ie design aspec s a e [9]: (a) Requi ed ou pu swing which, wi h he weigh s in Table 1, is educed o only he e e ence ol ages. (b) Open-loop DC-gain: Simula ions wi h ASIDES show ha he 68dB equi emen can be elaxed o ampli ie s in he second, hi d and ou h in eg a o o 62dB, 54dB, and 54&, espec i ely. (c) Dynamics, in luenced by he equi alen capaci i e load which is di e en o each in eg a o and clock phase. A wo-s age a chi ec u e, shown in Fig.4(u), was selec ed o OA 1 in o de o ul il i s DC-gain equi emen . I uses a elescopic i s s age and Mille compensa ion. A sin- gle-s age olded-cascode OTA, shown in Fig.4@), has been used in OA2, OA3, and OA4 - enough o accom- plish hei medium-, low-DC-gain equi emen s. Al hough hese ampli ie s use he same s uc u e, di e - en sizings ha e been ob ained o each o hem, in o de o uI i1 hei speci ica ions wi h a educed powe con- sump ion. The common-mode eedback ne s (no shown) a e dynamic - nei he s a ic consump ion no ol age ange p oblems. The main ea u es o he ou ampli ie s, sized using FRIDGE [8], a e summa ized in Table 3. Table 3. Summa ized ampli ie pe o mance 3.2 Capaci o s and swi ches Uni a y capaci o s ha e been implemen ed wi h a mul i-me al sandwich s uc u e, using he i e me al lay- e s a ailable in he in ended echnology. Acco ding o p e ious measu emen s, he s anda d de ia ion o he ma ching e o is 0.12%. The bo om-pla e pa asi ic 4 capaci o , especially impo an o dynamic equi e- men s, is be ween 20% - 40% o he nominal capaci ance. Due o he high-speed ope a ion o he UM, ini e swi ch ON- esis ance Ron is mainly cons ic ed by dynamic con- side a ions. In ou case, Ron in he ange o 25052 - 300S2 can be ole a ed, wi h a mino deg ada ion o he modula- o pe o mance. This alue is no oo demanding o a CMOS ans e ga e in he 3.3-V supply in ended ech- nology, so ha clock-boos ing s ages o simila ech- niques can be a oided. 3.3 Quan iza ion Blocks Since compa a o s ha e o be e y as , al hough no e y p ecise, a egene a i e la ch, wi hou p e-ampli ying s age is enough o mee he equi emen s. The same block has been used as he compa a o block o he las -s age 4-bi lash ADC, which uses a ully di e en ial SC on -end o compu e he di e ence be ween he las in e- g a o ou pu signal and he e e ence signals gene a ed in a esis i e ladde . The la e consis s o a simple esis o s ing o 30 uni a ies (R = 50Q) connec ed be ween he e e ence ol ages V + = + 1 V and V - = - 1 V. The same s ing has been used o he DAC. The alue selec ed o R ensu es ha se ling e o s a e small enough. No e ha we can a o d his simple, calib a ion- ee design because cascade mul i-bi ZAMs show low sensi i i y o he non-ideali ies o he las -s age quan iza ion blocks [8]. 4. EXPERIMENTAL RESULTS Fig.5 shows he layou o he p o o ype ab ica ed in a 0.35~ CMOS digi al echnology wi h epi conduc i e sub- s a e. I includes cen oid echniques in ma ched de ices, sepa a e analog, digi al and subs a e biasing, and an ex a supply dedica ed o he digi al ou pu bu e s, in o de o be able o educe his supply wi hou a ec ing he es o he ci cui y du ing he es phase, hus lowe ing he powe o he swi ching noise. The modula o occupies 1 .32m2 wi h- ou pads and consumes 78.3mW: 60.2mW o he analog blocks, 4.5mW o he digi al pa , and 13.6mW o he ou - pu d i e s. The modula o samples we e solde ed (wi hou socke ) on a wo-laye PCB, Fig.6, including sepa a e analog and digi al planes, de-coupling capaci o s in he supply lines and e e ence ol ages, e mina ion esis o s o imped- ance coupling a he digi al ou pu lines and ESD p o ec- V- D T- I I I I I I I Id L Fig. 4. Schema ics o he ampli ie s: (a) Two-s age ampli ie , (b) Folded-cascode OTA. 5 03 -15dBV@103kHz D U Fig. 5. Layou o he 2-12mb ZAM Fig. 6. Two-laye PCB ions. An ex e nal 1 s -o de low-pass an i-aliasing il e was placed a he modula o inpu . Fig.7 shows he measu ed ou pu spec um o he comple e modula o and hose co esponding o he i s s age (2nd-o de ) and o he combina ion o he i s and second s ages (3 d-o de ). No e he inc ease in he o de o he shap- ing o he quan iza ion noise. The measu ed SNDR s. inpu le el a e shown in Fig3 o wo di e en clock equencies: 35.2MHz and 64MHz, and cons an o e sampling a io = 16. No e ha he achie ed dynamic ange is 8 1 dl3 in he m case and i is 6dB smalle in he second. Ou measu emen s show ha his deg ada ion is la ge he la ge he sampling equency and ha he pe - o mance imp o es when he biasing o he ou pu bu e s is he swi ching noise coupled h ough he highly conduc i e subs a e o he epi echnology [lo]. Fu he esul s in his espec will be p esen ed a he con e ence. Ne e heless, wi h he achie ed pe o mance, he modula o he e com- pa es a o ably wi h he s a e-o - he-a modula o s in Fig.9, especially because p e ious esul s ha e been achie ed in analog echnologies. REFERENCES lowe ed. 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