RD53 pixel readout integrated circuits for ATLAS and CMS HL-LHC upgrades

Journal of Instrumentation PAPER • OPEN ACCESS RD53 pixel readout integrated circuits for ATLAS and CMS HL-LHC upgrades To cite this article: G. Alimonti et al 2025 JINST 20 P03024 View the article online for updates and enhancements. You may also like Effects of data quality vetoes on a search for compact binary coalescences in Advanced LIGO’s first observing run B P Abbott, R Abbott, T D Abbott et al. - LOCALIZATION AND BROADBAND FOLLOW-UP OF THE GRAVITATIONALWAVE TRANSIENT GW150914 B. P. Abbott, R. Abbott, T. D. Abbott et al. - Multi-messenger Observations of a Binary Neutron Star Merger B. P. Abbott, R. Abbott, T. D. Abbott et al. - This content was downloaded from IP address 193.147.173.198 on 16/04/2025 at 09:35 2025 JINST 20 P03024 Published by IOP Publishing for Sissa Medialab Received: May 29, 2024 Revised: November 6, 2024 Accepted: February 7, 2025 Published: March 19, 2025 RD53 pixel readout integrated circuits for ATLAS and CMS HL-LHC upgrades The RD53 collaboration G. Alimonti,11 A. Andreazza,11 F. Arteche,22 M.B. Barbero,1P. Barrillon,1R. Beccherle,16 G. Bonomelli,20 G.M. Bilei,15 W. Bialas,3D. Bortoletto,5G. Calderini,26 A. Caratelli,3 A. Cassese,9J. Christiansen,3,∗E. Conti,3,15 F. Crescioli,26 M. Daas,35 L. Damenti,9,10 S.D’Auria,11 F. De Canio,13 G. De Robertis,8N. Demaria,17 J. DeWitt,31 Y. Dieter,35 A. Dimitrievska,25 W. Erdmann,29 S. Esposito,3D. Exarchou,3D. Fougeron,1L. Gaioni,13 M. Garcia-Sciveres,25 D. Gnani,25 C. Gozalez Renteria,36 M. Grippo,17,18 A. Guardino,36 M. Hamer,35 T. Heim,25 T. Hemperek,35 F. Hinterkeuser,35 S. Huiberts,34 L.M. Jara Casas,3 J.J. John,5J. Kampkötter,33 M. Karagounis,33 I. Kazas,27 Y. Khwaira,23 R. Kluit,28 D. Koukola,3A. Krieger,25 H. Krüger,35 J. Lalic,3M. Lauritzen,34 F. Licciulli,8Peilian Liu,21 F. Loddo,8E. Lopez Morillo,6A. Lounis,23 F. Luongo,17,18 M. Manghisoni,13 S. Marconi,3,15 F. Marquez Lasso,6C. Marzocca,30 K. Mauer,35 A. Mekkaoui,4Lingxin Meng,24 M. Menichelli,15 M. Menouni,1M. Minuti,16 M. Mironova,25 S. Miryala,2M. Missiroli,29,32 E. Monteil,17,18 K. Moustakas,35 F. Muñoz Chavero,6G. Neue,7S. Orfanelli,3 A. Paccagnella,12 L. Pacher,17,18 F. Palla,16 F.R. Palomo Pinto,6A. Papadopoulou,25 A. Paterno,17,18 A.R. Petri,11 P. Placidi,15 R. Plackett,5A. Pradas,22 A. Pulli,3B. Raciti,19 L. Ratti, 14 V. Re, 13 A. Rehman, 34 P. Rymaszewski, 35 P. Sander, 20 M.C. Solal, 23 M. Standke, 35 B. Stugu,34 E. Thompson,25 G. Traversi,13 D. Vogrig,12 M. Vogt,35 Tianyang Wang,35 Hongtao Yang37 and J. Zdenko7 1Aix Marseille Université, CNRS/IN2P3, CPPM, Marseille, France 2Brookhaven National Laboratory, Upton, NY, U.S.A. 3CERN, European Organization for Nuclear Research, Geneva, Switzerland 4Clevert Systems LLC , West Henrietta, NY, U.S.A. 5Dept. of Physics, Oxford University, Oxford, United Kingdom 6ETSI, Universidad de Sevilla, Sevilla, Spain 7Faculty of Nuclear Sciences and Physical Engineering, Czech Technical University in Prague, Prague, Czech Republic 8INFN Sezione di Bari, Bari, Italy 9INFN Sezione di Firenze, Florence, Italy 10Università di Firenze, Florence, Italy ∗Corresponding author. ©2025 The Author(s). Published by IOP Publishing Ltd on behalf of Sissa Medialab. Original content from this work may be used under the terms of the Creative Commons Attribution 4.0 licence. Any further distribution of this work must maintain attribution to the author(s) and the title of the work, journal citation and DOI. https://doi.org/10.1088/1748-0221/20/03/P03024 2025 JINST 20 P03024 11INFN Sezione di Milano and Università degli Studi di Milano, Milano, Italy 12INFN Sezione di Padova and Università di Padova, Padova, Italy 13INFN Sezione di Pavia and Università di Bergamo, Bergamo, Italy 14INFN Sezione di Pavia and Università di Pavia, Pavia, Italy 15INFN Sezione di Perugia and Università di Perugia, Perugia, Italy 16INFN Sezione di Pisa, Pisa, Italy 17INFN Sezione di Torino, Torino, Italy 18Università di Torino, Torino, Italy 19Institut für Experimentalphysik, Universität Hamburg, Hamburg, Germany 20Institute for Particle Physics, ETH, Zurich, Switzerland 21Institute of High Energy Physics, Beijing, People’s Republic of China 22Instituto Tecnologico de Aragon, Zaragoza, Spain 23Laboratoire de Physique des 2 Infinis Iréne Joliot Curie, Orsay, CNRS / Universitè Paris-Saclay, Paris, France 24Lancaster University, Lancaster, United Kingdom 25Lawrence Berkeley National Laboratory, Berkeley, CA, U.S.A. 26LPNHE, Sorbonne Université, Université Paris Cité, CNRS, Paris, France 27National Center for Scientific Research, DEMOKRITOS, Agia Paraskevi, Greece 28National Institute for Subatomic Physics (NIKHEF), Amsterdam, Netherlands 29Paul Scherrer Institut, Villigen, Switzerland 30Politecnico di Bari, Bari, Italy 31SCIPP, University of California, Santa Cruz, CA, U.S.A. 32Universität Zürich, Zürich, Switzerland 33University of Applied Sciences and Arts Dortmund, Dortmund, Germany 34University of Bergen, Bergen, Norway 35University of Bonn, Bonn, Germany 36University of California, Berkeley, CA, U.S.A. 37University of Science and Technology of China, Hefei, China E-mail: [email protected] Abstract: The RD53 collaboration has since 2013 developed new hybrid pixel detector chips with 50 ×50 μ m 2 pixels for the HL-LHC upgrades of the ATLAS and CMS experiments at CERN. A common architecture, design and verification framework has been developed to enable final pixel chips of different sizes to be designed, verified and tested to handle extreme hit rates of 3 GHz/cm 2 (up to 12 GHz per chip) together with an increased trigger rate of 1 MHz and efficient readout of up to 5.12 Gbits/s per pixel chip. Tolerance to an extremely hostile radiation environment with 1 Grad over 10 years and induced SEU (Single Event Upset) rates of up to 100 upsets per second per chip have been major challenges to make reliable pixel chips. Three generations of pixel chips, and many specific mixed signal building blocks and radiation test chips, have been submitted and extensively tested to get to final production chips. The large, complex and high rate pixel chips have been developed with a strong emphasis on low power consumption together with a concurrent development and qualification of novel serial powering at chip, module and system level, to minimize detector material budget. Keywords: Front-end electronics for detector readout; Particle tracking detectors (Solid-state detectors); Radiation-hard electronics; VLSI circuits 2025 JINST 20 P03024 Contents 1 Introduction and requirements 1 2 Pixel detector system 6 3 Chip architecture 8 4 Analog front-ends and hit digitization 10 4.1 CMS Linear front-end 19 4.2 ATLAS differential front-end 24 5 Data buffering and triggering 29 6 Control and readout 33 7 Power and references 37 8 Monitoring 45 9 Radiation tolerance 46 10 Implementation 52 11 Verification 56 12 Test and characterization 59 13 Conclusions 63 1 Introduction and requirements This paper gives an overview of the general requirements, design, architecture and measured performance of the RD53 pixel chips, developed for the ATLAS and CMS High Luminosity Large Hadron Collider (HL-LHC) upgrades. This development has been a major effort by a large number of people ( ∼100 ) over 10 years. The RD53 collaboration [ 1 ], with 24 institutes, was established in 2013 to develop the required hybrid pixel detector readout integrated circuits for the ATLAS [ 2 ] and CMS [ 3 ] pixel detector upgrades for the HL-LHC. The two experiments have very similar requirements to their pixel detector upgrades and both are using lpGBT (low power GigaBit Transceiver) links [4] for control and readout. It was therefore agreed to do such a challenging chip development in common among ATLAS and CMS pixel detector groups with ASIC design and test experience. A common architecture, design and verification framework has been developed to make final production pixel chips, with slightly different chip sizes to enable optimal integration into the two pixel detector systems. The general layout of the ATLAS and CMS pixel detectors are indicated in figure 1. –1– 2025 JINST 20 P03024 Figure 1. Upper: ATLAS tracker layout with pixel detector at its centre. Lower: one quarter of CMS pixel detector layout. The pixel detectors are highly compact at the center of the experiments with critical material budget and difficult access. Both detectors are constructed from overlapping ladders/staves of multi (2,3 or 4) chip pixel modules for the central barrel part and concentric rings for the forward regions. Inner layers are specifically constructed to enable partial replacement during long shutdowns, in case of significant performance degradation from radiation damage in pixel sensors or pixel chips. RD53 chips have been developed to meet the stringent rate and radiation requirements for operation at the HL-LHC, projected to begin operation in 2030. The HL-LHC will operate at an instantaneous luminosity of up to 7.5×1034 cm −2 s −1 corresponding to an average pileup of 200 inelastic proton-proton collisions per bunch crossing. This translates into an average pixel hit rate of up to 3 GHz/cm 2 in the innermost pixel layer at the 40 MHz bunch crossing rate. Inner pixel layers will have to work reliably in an extremely hostile radiation environment with up to 1 Grad Total Ionizing Dose (TID) and a Non Ionizing Energy Loss (NIEL) dose of 10 16 1 MeV n eq cm −2 over 10 years operation. It is assumed that innermost pixel layer(s) will possibly need replacement after 5-10 years, depending on the actual integrated luminosity and pixel sensor and chip performance degradation. The integration of the pixel detectors in the experiments has been made to enable partial replacement of inner pixel layer(s). The extreme radiation levels require the pixel chip design to be made with a strong emphasis on rad-hard design and effective SEE (Single Event Effects) protection. An inner layer pixel chip can be estimated to have up to 100 Hz of SEUs (Single Event Upsets) and SETs (Single Event Transients) and must function reliably despite these upsets in its internal data buffers, –2– 2025 JINST 20 P03024 state-machines and configuration registers. This unprecedented radiation tolerance requirement is a factor ∼10 higher than what has previously been made for High Energy Physics (HEP) applications and a factor ∼10 ,000 higher than normally required for rad-hard space applications. The general chip requirements are outlined in table 1. The RD53 chip will be bump-bonded to sensors with a pixel size of 50 ×50 μ m 2 in the forward layers and 25 ×100 μ m 2 in the central barrel layers. These sizes are ∼4 times smaller than in previous generation ATLAS and CMS pixel sensors. This combined with the increased hit rate (factor ∼4 ) and extended trigger latency (factor ∼2 ) implies that effective trigger latency hit buffering has been increased by a factor of more than 10 compared to current ATLAS [ 7 ] and CMS [ 8 ] pixel detectors. The increased trigger rate, from 100 kHz to 1 MHz, combined with higher hit rate and smaller pixels implies that effective readout bandwidth is increased by a factor ∼100 , maintaining a 4 bit charge measurement per pixel hit. Requirements for pixel sensor capacitance and radiation induced leakage together with appropriate charge detection threshold have been determined from scaling from previous pixel detectors and measurements on pixel sensor prototypes in the two experiments. Table 1. General requirements to RD53 pixel chips for use in ATLAS and CMS pixel detectors at HL-LHC. At the pixel detector level it is critical to keep the material budget of pixel detector modules and related services as small as possible, so as not to deteriorate significantly tracking performance –3– 2025 JINST 20 P03024 from particle scattering and conversions in the pixel detector and its related cooling, powering and readout services. The chip power consumption must be kept as small as possible, at similar level as the previous generation pixel chips, despite significantly higher pixel density and complexity with higher hit and readout rates. The use of a scaled CMOS technology is critical to keep an acceptable power consumption, from reduced capacitive loading of on-chip gates and the reduction of power supply voltage (Power scales with power supply voltage as 𝑉2 DD ). An unfortunate side effect of power supply voltage scaling is that for the same power consumption, the required power supply current increases, posing problems making an appropriate low mass power distribution system. The use of switched mode DC-DC power conversion on the pixel chip, or on the pixel module, was investigated, but excluded because of the required radiation tolerance and associated space and material budget of local inductive or capacitive power converters. A novel serial powering scheme has therefore been adopted, with on-chip SLDO (Serial Low DropOut) power regulators, based on initial feasibility demonstrations with the FEI4 chip [ 5 , 26 , 31 ]. This particular serial power distribution system has been developed, tested and qualified at the chip, module and system level, while the RD53 pixel chips were actively being developed. The first years of development in RD53 were focused on radiation tolerance studies of the chosen 65 nm CMOS technology and implementing and testing the required radiation hard building blocks: Digital to Analog Converters (DAC), Analog to Digital Converter (ADC), Analog pixel Front-Ends (AFE), biasing structures, band-gap reference, Phase Locked Loop (PLL), Input-Outputs (IO), SLDO power regulator and temperature and radiation sensors. An appropriate hit buffering, processing and readout architecture for the high hit and trigger rates was developed and extensively simulated and verified in a flexible simulation and verification framework with detector Monte Carlo hit data. A first 1/2 sized pixel chip called RD53A, submitted in 2017 on a shared submission, has been used for verification of developed building blocks and general architecture. RD53A has also been instrumental as a test vehicle to test and qualify different pixel sensors [ 6 ] and for system studies, covering serial powering, design and testing of pixel modules and testing with lpGBT based readout system with optical links to the off-detector DAQ. A large set of irradiation test campaigns have been made with this chip to get a good understanding of reliable functionality of such a complex chip covering TID (Total Ionizing Dose) effects as a function of temperature, dose rate effects, and initial SEE tests. Three different analog front-ends were present in this chip together with two different trigger latency buffering schemes to determine the most appropriate implementation for final chips. A second generation of RD53 chips, named RD53B-ATLAS & RD53B-CMS [ 9 , 10 ], are complete full sized pixel chips made with the chosen latency buffer architecture and improved building blocks. RD53 developed a flexible parameterized design and verification environment where full custom macros and Register Transfer Level (RTL) code are instantiated according to the specific ATLAS or CMS implementations. The RD53B generation chips were made specifically for each experiment (RD53B-ATLAS, known as ITkPixv1 in ATLAS, and RD53B-CMS, known as CROCv1 in CMS) with their specific AFEs and chip size adapted to specific integration constraints of each experiment. These two chips, submitted in 2020 and 2021, are functionally equivalent with the same control and readout interfaces, with minor specific features related to the analog front-ends and specific features and bugs. The RD53B-ATLAS chip unfortunately had non-functional TOT (Time Over Threshold) charge measurement and could only be used with binary readout. The RD53B generation chips have been instrumental for extended chip testing in RD53 and pixel module and –4– 2025 JINST 20 P03024 Figure 2. RD53A to RD53C chip generations with chip submission dates. system developments, testing and qualification in the ATLAS and CMS pixel detector groups. The evolution of the RD53 chips is shown in figure 2. Bug fixes and improvements have been made in the final generation production chips: RD53CATLAS and RD53C-CMS [ 11 ]. Monitoring functions have been improved and extended. SEU and SET tolerance have been significantly improved based on extensive RD53B ion, proton and laser beam testing and SEU/SET simulations at transistor, gate and RTL level. Testing of serially powered quad chip pixel detector modules, in the ATLAS and CMS pixel detector groups, have enabled system issues to be identified and corrected. An extended verification framework was specifically developed for exhaustive functional and SEU/SET verification. The large scale prototype chips RD53A, RD53B-ATLAS and RD53B-CMS have been produced and extensively tested as reported in this paper. Final production version chips, RD53C-ATLAS and RD53C-CMS, have recently been submitted and are in production for use in the experiment upgrades. The RD53C chips have recently been through extensive chip testing and characterization, with test results as reported in this paper. They are used for pixel module pre-production for large scale system tests. Wafer level production test setups have been developed and qualified for the two experiments. Test results shown in this paper are in general for the bare pixel chip without a pixel sensor, unless specifically mentioned in the figure caption. Bump bonded pixel chip and pixel sensor assemblies have only recently become available in sufficient quantity and quality to make detailed chip characterization of these with measurements shown in section 12. Extensive pixel module test, characterization and qualification is currently ongoing in the ATLAS and CMS pixel groups with their specifically chosen pixel sensors. The chip architecture and implementations are outlined together with circuit details of critical blocks to achieve required performance in the hostile radiation environment. Most of the discussions make no distinction between the ATLAS and CMS chips, as these are based on a common architecture with only minor implementation differences. The paper is organized as follows. Section 2provides a short overview of the planned use of the pixel chips in the ATLAS and CMS pixel detectors. Section 3 gives an overview of the pixel chip architecture. Section 4describes the analog front-ends, performing pixel hit detection with a 4 bit charge measurement. Section 5outlines hit data buffering during the trigger latency and following data processing. Section 6defines the control and readout interfaces. Section 7covers the on-chip serial power regulator and the generation of biasing and references. Section 8describes the implemented on-chip monitoring features. Section 9summarizes radiation tolerance aspects. Section 10 outlines the integration and implementation. Section 11 describes final functional and SEU/SET verification. Section 12 summarizes general test results and wafer probing. Finally section 13 concludes the paper. –5– 2025 JINST 20 P03024 2 Pixel detector system The upgraded pixel detector systems of ATLAS [ 2 ] and CMS [ 3 ] are made to have the same front-end control, readout and powering interfaces defined for the RD53 pixel chips. Pixel chips are integrated on dual, triple or quad pixel chip modules with a single bump-bonded pixel sensor. Effective hit rates and required readout rates have a strong dependency on the radial distance to the interaction point ( 𝑟−2 ). Inner layer chips require up to 5.12 Gbits/s readout bandwidth, while pixel chips in outer layers only need a factor 20–50 lower readout bandwidth (depending on detector layout, number of layers and barrel versus forward). The readout via the lpGBT has therefore been defined to allow a high level of readout link modularity to minimize the number, and material, of required readout links. Each pixel chip can use from 1 up to 4 serial Electrical links (E-links) at 1.28 Gbits/s (lpGBT max E-link speed). RD53 pixel chips can also be used in a primary-secondary configuration, where readout data from 2 or 4 pixel chips are merged into a single 1.28 Gbits/s link as illustrated in figure 3with pixel module prototypes shown in figure 4. Multiple chips on the same pixel module are controlled with a single 160 Mbits/s control link carrying clock, configuration and real-time control information. In ATLAS, control and readout links between pixel chips and the lpGBT are up to 8 m long [ 24 ], using a dedicated cable driver and equalizer GBCR ASIC [ 23 ] . In CMS, with an E-link distance limited to 1.5 m, the pixel chips are connected directly to the lpGBT. Serial powering is used in both pixel detector systems to minimize the material budget for the power distribution. The power supply current on a single power cable pair is used to power up to 16 pixel modules in series as shown in figure 5. Multiple pixel modules are powered in series with a constant current and on-chip SLDO regulators dynamically adjust their chip power impedance, to have constant and well regulated local voltages for the analog and digital parts of the chip. In such a powering scheme it is critical to minimize fluctuations in circuit power consumption and have sufficient current headroom and local decoupling capacitors to enable the local power regulators to absorb such fluctuations, as shown in figure 5in upper right plot. Each chip has separate analog and digital SLDO regulators, connected in parallel to the common input power, to assure the best possible isolation of the sensitive analog front-ends from switching noise induced in the power rails by the digital circuits. The effective load impedance is dynamically regulated with a controlled shunt current, maintaining constant input voltages and currents, independently of the actual current consumed by the analog and digital circuits in the chip. Such a constant current (and constant voltage) powering system is highly advantageous in systems where low noise is primordial and where long power cables will have significant voltage drops. Assuring constant power supply currents also prevents power cables in strong magnetic fields to have induced dynamic forces with possible resonances. System drawbacks of serial powering are the power dissipated in the on-chip regulators , with necessary current (10–20 %) and voltage (0.2–0.3 V) headrooms, adding up to a total power overhead of 20–40 %. In particular, if the pixel chip goes into a low power state, the on-chip regulators will have to dissipate the full nominal chip power as shown in figure 5lower right thermal image. Both pixel detectors will be cooled with highly efficient high pressure CO 2 cooling systems that will be designed to cope with this. Another system issue with serial powering is the requirement that all control and readout links to/from the pixel chips must have AC coupling, with appropriate DC balanced link encoding. Special care must be taken for system grounding as pixel module grounds can not be connected to system ground, which implies the need for good galvanic isolation between pixel chips and local CO 2 cooling. The High –6– 2025 JINST 20 P03024 enforcing a short average TOT time below 133 ns. In outer low rate layers a longer TOT time can be used to get better charge resolution. It can be mentioned that if the charge integrated analog signal has amplitude saturation effects, the TOT charge measurement can be corrected off-line, when used at low thresholds as indicated in figure 11. If the detection threshold is set at a charge level below where the saturation effect sets in, the leading edge is detected at the correct level. Saturation effects occurring above the threshold detection level will affect the TOT pulse width. This can be corrected for offline if this non-linearity has been appropriately characterized. This TOT non-linearity can though have relatively large variations between individual pixels and be sensitive to temperature and radiation effects. Small hit signals, just above threshold (e.g. at edge of pixel clusters), will get time walk from the combined effect of analog signal shape and the discriminator reacting slower when having small signal over-drive. For a time-walk below 20 ns (25 ns clock period minus 5 ns sampling margin for system jitter and time alignment to collisions) the hit will be detected in the appropriate bunch crossing for triggered readout. For time walk larger than this, the hit can be seen as a low TOT/charge ′′ noise ” hit in the following bunch crossing and will therefore not be read out for the corresponding trigger (unless forcing double triggering). Each experiment has chosen their specific low power AFE implementation based on their specific emphasis on particular performance characteristics. The differential AFE used in the ATLAS chip has particular emphasis on low noise and small time-walk. The linear AFE used in the CMS chip has particular emphasis on linearity ( ∼5 %) and capability to work with short analog/TOT dead-time in inner high rate pixel layers [ 16 ]. The two AFEs have similar effective area and interfaces and are integrated into the RD53 design framework with a few design configuration parameters. Multiple biasing levels for the AFEs are defined by global configuration registers connected to biasing DACs driving the analog pixel array via column drivers as shown in figure 12: • Pre-amplifier bias: determines the effective speed of AFE charge integration, but also affects effective gain, noise and dispersion. Major contributor to AFE power consumption. • TOT discharge current: determines the discharge rate of integrated charge, thereby defining TOT resolution and related analog dead-time. •Discriminator bias: determines the effective speed (and time-walk) of discriminator. • Global threshold: global chip threshold onto which local pixel threshold adjustment is applied. •Threshold adjust range: determines the range of local threshold adjust DACs. Biasing of the AFEs has significant effects on their behavior and is a delicate optimization to be done according to the allowed power consumption, hit rate, noise, time walk and pixel sensor characteristics. It will also be needed to take into account accumulated radiation effects in both pixel sensor and the pixel chip itself. Edge and corner pixels have separate pre-amplifier biasing as they are typically 2-4 times larger to cover the gap between pixel chips on multi-chip pixel modules (e.g. quad pixel modules) and minimize insensitive areas at pixel module edges. This is organized in 6 groups: Main, Left side, Right side, Top, Top Left corner, Top Right corner, as indicated in figure 12, to enable flexible adaptation to different pixel sensor and module configurations with enlarge pixels in boundary regions between pixel chips. – 13 – 2025 JINST 20 P03024 Figure 12. AFE bias distribution with different pre-amp biasing of different pixel regions: Main (M), Left side (L), Top Left side (TL) , Top (T), Right side (R), Top Right (TR). The leading edge of the discriminator hit signal is a measure of the particle Time Of Arrival (TOA), with associated time walk, and the Time Over Threshold (TOT) is proportional to the collected charge. The leading edge is synchronized to the 40 MHz sampling clock and the pulse width is measured with the rising or both edges of the 25 ns sampling clock (40 and 80 MHz TOT sampling) for a 6 bit TOT count. The 6 bit TOT count can be mapped directly into 4 bit TOT, ignoring the 2 MSB (Most Significant Bits) bits with saturation, or can be mapped into 4 bits with a dual slope mapping. With dual slope mapping the full TOT resolution is maintained in the first half of the 4 bit dynamic range, whereas extended dynamic range is obtained in the second half as illustrated in figure 13. Dual slope mapping assures good position interpolation at the edge of pixel clusters, where the collected charge is normally small, and high dynamic range for dE/dx measurements of pixel clusters that can be used to identify highly ionizing particles and contribute to general particle identification [ 15 ]. Capture of the discriminated hit signal can be performed synchronously or asynchronously. For synchronous/simple sampling, short hits not present at the rising edge of the sampling clock will be ignored. For asynchronous/latched sampling, a discriminator hit pulse is kept high until it has been captured by the first coming 40 MHz sampling clock edge. Async sampling is guaranteed to capture short hit pulses, but will have slightly higher sensitivity to noise hits as indicated in figure 14. One should also be aware that short/small hits will typically also be affected by time-walk. In RD53B chips the hit sampling mode was configurable. For the final RD53C chips, ATLAS has chosen the async sampling mode, given the low noise and low time-walk AFE and issues fitting both modes in available area. For the RD53C-CMS chip it has been possible to maintain both sampling modes. The 40 MHz sampling clock for the hit detection in the individual pixels is carefully distributed across the pixel array with typical (maximum) time skew across the whole array below 1 ns (2 ns) – 14 – 2025 JINST 20 P03024 Figure 13. Measured Linear and Dual slope TOT with 40 MHz and 80 MHz sampling using digital pulse width injection. Left: CMS chip with pulse width in BX units (25 ns) and TOT=15 representing no hit (so not shown). Right: ATLAS chip with pulse width injection in ns and TOT=0 representing no hit. Does not include analog non-linearity of the AFE (described later). Figure 14. Hit sampling with synch/asynch sampling. Indication of optional 80 MHz TOT sampling. to assure that hits are captured in the correct bunch crossing for triggering and readout. This gives short digital power surges over the pixel array at the rising edge of the clock that can affect the analog front-ends and hit digitization. Local decoupling capacitors are distributed across the array to minimize this effect and the AFEs have been decoupled as much a possible from the digital with separate power domains and the use of separate triple wells for analog and digital. A threshold variation over the 40 MHz clock period has been observed in the full RD53 chips as indicated in figure 15 and figure 16. This can be seen to be related to on-chip power distribution with four distributed sub-instances for each SLDO. The magnitude of this effect is dependent on the sampling mode used (sync or async) and on the configured TOT discharge rate (fast/slow). The Async sampling mode, assured to capture incoming hits in the full clock cycle is intrinsically less sensitive to the arrival time of hits. At a 1000 e threshold the async sampling will have a 50 e (fast shaping assumed use in final application) - 450 e (slow shaping) threshold variation effect. This has been measured to be proportional to the number of pixel core columns actively being clocked and will therefore also in practice depend on power decoupling and wire-bonding (resistance and inductance) on a pixel module. The measured threshold variation across the pixel array is caused by static and dynamic voltage drops in the on-chip power distribution network within the pixel array and four distributed instances of the SLDOs. In – 15 – 2025 JINST 20 P03024 Figure 15. Left: RD53B-ATLAS threshold variation (async sampling) across clock cycle from power supply perturbations [ 56 ]. Right: threshold variation amplitude across pixel array overlayed on RD53B layout with indication of distributed SLDOs in four groups. DVCAL is digital threshold configuration DAC in steps of 5 e. sync sampling mode, the effective hit capture threshold has a relatively large dependency on the relative phase to the sampling clock and used TOT discharge rate as shown in figure 16, because short hits can be missed depending on its relative timing/phase to the sampling clock. It has not been possible to improve this further for a one-side powered chip, needed for quad chip pixel modules with no dead detection zones between chips. It should be noted that direct particles from the bunch collisions of the LHC arrive within a relatively narrow time window ( ∼1 ns) and will therefore not be significantly affected by this. It is for each experiment to determine how they want to time align their pixel detector to the bunch collisions, using programmable delays in their timing distribution system and in the RD53 chip, and how to obtain appropriate absolute threshold and charge measurement calibration, using calibration pulse injections in the RD53 chip. Discriminated hit signals from individual pixels, with local enables, are also connected to a configurable hit-OR column network to measure Time Of Arrival (TOA) and TOT with 640 MHz precision TDCs (Time to Digital Converter) in the Digital Chip Bottom (DCB). The hit-OR signals are also used for a flexible self-trigger function that can be used for detailed chip and sensor characterization in test beams and with radioactive sources. An example of using the precision TOA is shown in figure 17 to measure calibration injection and hit-OR skew along pixel columns in the RD53B-ATLAS chip (improved in RD53C chips to have reduced skew), and measure analog pulse shape with a threshold scan using the precision TOA and TOT. An analog injection circuit is implemented in each pixel, with an equivalent circuit as shown in figure 18, to perform precise threshold tuning and calibration. The calibration injection circuit uses two distributed DC voltages (Vcal_Med and Vcal_Hi), from two on-chip 12 bits DACs, followed by in-pixel switches to generate charge injections via a pixel injection capacitor (Cinj). Having two charge injection voltages enables precise differential charge injections (Vcal_Hi - Vcal_Med), independent of ground voltage drops across the pixel array, as well as making two consecutive injections (Vcal_Hi - Vcal_Med followed by Vcal_Med - ground) into the same pixel. The timing of the injection is – 16 – 2025 JINST 20 P03024 Figure 16. RD53B-CMS Threshold variation across clock cycle. Upper left: sync sampling mode for different TOT discharge rates from Fast (Krum=190) to Slow (Krum=50). Upper right: async sampling mode. Lower left: 2D map of async threshold variation across pixel array in fast mode with 10 e color step. Lower right: estimated max threshold variation effect for fast (inner) and normal (outer layers) discharge rate for 3D and planar pixel sensors. Reproduced with permission from [17]. 24 Recent Studies — Front-end Scope Scan Adjusting parameters of the analog front-end and measuring their impact on the analog front-end output DiffVff controls the constant-current discharge in the feedback circuitry in the first stage of the analog frontend As the discharge rate increases, the pulse width (ToT) decreases — but also the pulse amplitude (the discharge rate begins to overtake the charge-up rate) Figure 17. RD53B-ATLAS precision TOA and TOT. Left: digital pixel injection across pixel array with measured TOA using the high resolution TDC via the hit-OR network. Right: analog pulse shape reconstructed from measured TOA and TOT with high resolution TDC, over different charge injections. DiffVff sets the charge integration discharge current of the Differential AFE and the shaded area indicates the spread among pixels in the pixel array. – 17 – 2025 JINST 20 P03024 controlled by a digital pulse generator with programmable injection time (0.78 ns resolution) and time between two consecutive injections, using the two calibration voltages plus local ground. The same pulse generator can be used for direct digital hit injections. Two 12 bit voltage DACs located in the ACB generate the charge injection voltages, driven with dedicated voltage drivers to the in-pixel charge injection circuits in each pixel. The DAC characteristics are shown in figure 18. Calibration injection has an effective resolution of ∼5 e when being used concurrently on a limited number ( ∼100 ) of pixels. Used for massive concurrent injections in a large number of pixels, the effective precision is deteriorated by dynamic capacitive loading from the voltage switches in the pixels. Injection capacitance spread among chips on the same wafer has been seen to be 1 - 1.5 % with a 5-10 % difference between wafers. Figure 18. Calibration injection voltage as function of DAC setting with a linear fit and extracted DNL (Differential Non-Linearity) and INL (Integral Non-Linearity). Pixel charge injection circuit shown as an insert with its two injection voltages (Vcal_Med, Vcal_Hi) and local ground, enabling two consecutive charge injections to be made. A dedicated charge injection capacitor calibration circuit, shown in figure 19, is available in the ACB to make a precise injection capacitor measurement per chip, during wafer probing to enable calibrated charge injections in the final systems. Shown AFE test results are in general for bare chips without bump-bonded pixel sensors. Bump bonded assemblies with sensors have only recently become available in sufficient quantity and quality to make detailed AFE characterization with these. No significant changes in pixel chip performance have been seen when tested with a bump bonded pixel sensor, except an AFE noise increase of 10–30 e, as can be expected when having increased input capacitance [ 19 ]. – 18 – 2025 JINST 20 P03024 Figure 19. Left: Pixel Injection capacitor (Ctest) measurement circuit measuring the average current, with on-chip ADC (GADC) or external pin (V_Mux_pad), when charging and discharging the injection capacitor at a constant injection rate. An equivalent branch, without injection capacitor, enables to measure parasitic capacitance (Cp) of the circuit. Right: measured injection capacitor dispersion over two wafers from the same production lot. 4.1 CMS Linear front-end The schematic of the linear analog front-end [ 18 , 19 ] adopted in the RD53B/C-CMS chip is shown in figure 20 with a Charge Sensitive Amplifier (CSA) with Krummenacher feedback [ 14 ] complying with the expected radiation induced detector leakage and providing a linear discharge of the feedback + CF Vref IK IK/2 VDDA Vth Injection circuit Vout,csa sensor bump PAD CK Vout,comp 5-bit threshold tuning DAC Figure 20. Schematic of CMS linear analog front-end. – 19 – 2025 JINST 20 P03024 Figure 21. Transistor level implementation of linear AFE pre-amplifier (left) and comparator (right). capacitor 𝐶𝐹 . The choice of a single amplification stage is dictated by power consumption and area constraints with a charge sensitivity, set by 𝐶𝐹 , of around 26 mV/ke − . The signal from the CSA is fed to a low power comparator with a 5 bit, current-mode binary weighted DAC for local threshold tuning. The front-end has been optimized for a linear response for an input charge up to 30 ke and features an overall current consumption of 5 μ A. The charge sensitive amplifier, shown in figure 21 left, is based on a folded cascode input stage with two local feedback networks, composed of the M4-M5 and M7-M8 pairs, boosting the signal resistance at the output node. A 3 μ A biasing current in the input branch and 200 nA in the cascode branch are responsible for most of the power consumption with a simulated open-loop DC gain of 76 dB with −3 dB cutoff frequency at 140 kHz with an effective closed loop peaking time of 22 ns. Noise is dominated by the input device and the PMOS transistor in the feedback. The comparator shown in figure 21 right, has a transconductance stage (M1-M5) followed by a Trans-Impedance Amplifier (TIA) (M6-M10) for fast switching, with an optimized feedback network (M6 and M7) for acceptable time-walk. Two inverters are used at the output to assure fast signal transitions to the digital pixel sampling logic. The layout and measured analog pulse shape are shown in figure 22. Figure 22. Left: linear AFE layout. Right: typical analog waveform before comparator, with 1–10 ke charge injections, measured on analog output of the RD53A chip. – 20 – 2025 JINST 20 P03024 Figure 23. RD53B-CMS Linear AFE pulse shape and threshold linearity. Left: reconstructed pulse shape from threshold and time scan combined with high precision TDC information, in fast mode with short TOT charge encoding. Right: threshold as function of global threshold setting. GDAC: global threshold setting, DeltaVCAL: injection voltage DAC setting (5 e per LSB). Figure 24. RD53B-CMS Linear AFE time-walk as function of injected charge (Left), at slow discharge and sync mode, and at different temperatures (right), at 1000 e threshold for different combinations of sync/async mode and fast/slow discharge rate. A reconstructed AFE pulse shape from a combined scan of injection time and threshold with TOT is shown in figure 23 together with threshold linearity as function of global threshold setting. Figure 24 shows the time-walk measured as function of injected charge together with time-walk dependency on chip temperature with sync and async sampling and for fast (inner layers) and slow (outer layers) TOT discharge times. TOT linearity, with saturation, is shown in figure 25 together with its dependency on sampling clock phase for different charge injections and TOT spread across the pixel array. Figure 26 shows untuned (before local threshold trimming) threshold dispersion over the full pixel array together with a 2D map of appropriate pixel trimming to obtain tuned pixel threshold dispersion as shown in figure 27, when using the optimal trimming DAC range to cover the full dispersion range with the best possible resolution. Tuned pixel threshold dispersion at 1000 e before and after 1 Grad irradiation is shown in figure 28 with only a small degradation of threshold dispersion (after re-tuning at 1 Grad). Finally pixel noise distribution is shown in figure 29 at room temperature and cold with mean noise as function of temperature for fast and slow TOT discharge. No noticeable change of noise has been observed with irradiation up to 1 Grad. – 21 – 2025 JINST 20 P03024 0 500 1000 1500 2000 2500 3000 3500 VCal∆ 0 2 4 6 8 10 12 14 ToT D_B(0)_O(0)_H(0)_Gain_Chip(15) Entries 5806080 Mean x 1901 Mean y 7.462 Std Dev x 1125 Std Dev y 4.704 1 10 2 10 3 10 4 10 5 10 D_B(0)_O(0)_H(0)_Gain_Chip(15) Entries 5806080 Mean x 1901 Mean y 7.462 Std Dev x 1125 Std Dev y 4.704 2000 4000 6000 8000 10000 12000 14000 16000 18000 Charge (electrons) Figure 25. RD53C-CMS Linear AFE TOT linearity and spread. Left: average TOT value as function of injected charge with linear encoding up to 15 ke, of interest for hit position interpolation between pixel hits in pixel cluster, for different relative clock phases (CE unit = 25 ns/32 = 0.78 ns). Right: measured TOT linearity and spread across pixel array. Figure 26. RD53B-CMS Linear AFE untuned threshold dispersion together with 2D trim DAC values to get uniform threshold (effectively shows untuned threshold map). Delta VCAL = 5 e. A column structure is clearly visible, coming from columns of pixel islands with their biasing drivers. No differences have been seen for the linear AFE in the RD53B-CMS and RD53C-CMS chips. In short it can be summarized that the linear AFE with a planar (or 3D) bump-bonded pixel sensor complies with the defined requirements in table 1and works fully satisfactory for the CMS pixel detector upgrade at a 1000 e threshold with ∼50 e dispersion, mean noise below ∼70 e (80-100 e with pixel sensor), time walk below 17 ns with a linear TOT charge measurement and radiation tolerance up to 1 Grad. At the time of writing, extended testing of the RD53C-CMS chip is ongoing in the CMS pixel detector project with different sensor types on pre-production modules in test beams and after irradiation. – 22 – 2025 JINST 20 P03024 Figure 39. RD53C-ATLAS Differential AFE noise variation at 1000 e threshold. Left: before and after 1 Grad Irradiation. Right: variation across pixel array after 1 Grad. 0 100 200 300 400 500 600 700 800 900 1000 Noisy pixel threshold [e] 1 10 2 10 3 10 4 10 Number of pixels ITkPix-V1.1 Chip SN: 0x162D7 (a) 0 200 400 600 800 1000 Pixel threshold [e] 0.95 0.96 0.97 0.98 0.99 1 Fraction of good pixels ITkPix-V1.1 Chip SN: 0x162D7 (b) Figure 40. RD53B-ATLAS Differential AFE noisy pixels as function of threshold. Left: number of noisy pixels (relative noise occupancy greater than 10−6). Right: fraction of not-noisy pixels. The differential AFE can be seen to have excellent noise performance with thresholds as low as 500 e. pixel detector upgrade at a 1000 e threshold with ∼50 e dispersion, noise of ∼55 e (65-85 e with pixel sensor), time walk as low as ∼15 ns, a compressed TOT charge measurement, and radiation hardness up to 1 Grad. At the time of writing, extended testing and qualification of the RD53C-ATLAS chip is ongoing in the ATLAS pixel detector project with final pixel sensors on pre-production modules in test beams and after irradiation. 5 Data buffering and triggering Alternative hit buffering and triggering architectures have been evaluated to choose a final implementation fulfilling trigger latency buffering requirements, with the lowest possible hit loss and acceptable power consumption. Fitting the logic in the available area in the pixel array is a critical design constraint. Sharing of hit buffering between 4 neighbor pixels was quickly identi- – 29 – 2025 JINST 20 P03024 fied to be critical to profit from locally clustered hits from a single particle (typically from 1–4 pixel hits per cluster). Initial studies found a pixel region of 2×2 pixels to be ideal for the high hit rate in the middle of the inner barrel layer. Further studies, with detailed Monte Carlo hit data from different parts of the detectors, with both 50 ×50 μ m 2 and 25 ×100 μ m 2 sized pixels, determined that a pixel region of 4×1 pixels is a better overall optimization for the two pixel detector layouts. Pixel hits are clustered from traversing particles depending on multiple factors: location of traversing particle, particle angle, sensor thickness, magnetic field, and also radiation damage in the pixel sensor. Two alternative buffering architectures were implemented in the RD53A prototype [ 12 ]. The “zero-suppressed FIFO” architecture uses two levels of shared FIFOs to minimize the required number of storage bits, at the cost of increased logic complexity. The “distributed latency counter” architecture minimizes logic complexity, at the cost of an increased use of memory cells. Both schemes were found fully functional in simulations and in the RD53A chip. The final choice of using the distributed latency counter architecture was based on effective hit losses, and minimizing logic and layout complexity to assure best possible SEU/SET tolerance. Sampled pixel hit signals are processed and buffered in small local pixel regions consisting of 4 pixels. When one, or multiple, pixels in a pixel region have a hit, a 4 bit TOT register per pixel stores the measured TOT. The four TOT values in the pixel region are stored in a local latency buffer location together with a 9 bit Bunch ID time-stamp from a central 40 MHz Bunch-ID counter, as indicated in figure 41. A TOT register value of 1111 bin indicates that no pixel hit has been detected. Writing to a 4 pixel buffer location is completed when all 4 TOT counting measurements are finalized. The pixel region hit capture and buffering is non-blocking so a new hit arriving in following clock cycles, on a pixel not part of the first cluster, is captured in the next free buffer location. Each pixel region has 8 local latency buffer locations. Hit losses from the limited hit buffering, at the highest hit rates of 3 GHz/cm 2 , have been modeled and simulated with Monte Carlo hit data and shown to be well below 1 % [ 12 ], as shown in figure 42. Significant design efforts have been invested to fit the required latency buffering in the highly constrained pixel area, using a custom made compact multi-bit latch and highly optimized logic. Effective hit losses have been measured with X-ray irradiations of a pixel module, as shown in figure 43 and scaled to anticipated HL-LHC hit rates (compensated for different cluster size between X-rays and particles in the HL-LHC environment). When a latency buffer location is in active use, the stored Bunch ID is continuously compared to a global latency counter with a relative offset, defining the effective trigger latency. When they match and an active trigger is generated, the buffer location is flagged as triggered, or the buffer location is released. Bunch ID information is then replaced with a trigger event ID to handle the readout of multiple pending triggered events with hit data. Digital logic in the pixel array uses optimized clock gating to obtain significant power savings. The hit capture logic in the pixel region has active local clocking only during the capture window of a hit (effective time window depends on TOT length), making the instantaneous power consumption dependent on hit rates. This requires careful optimization of local power decoupling capacitors, both on-chip and on pixel modules, to work reliably with serial powering. Readout of triggered hit data from the local pixel region latency buffers is controlled by a core column readout controller at the end of each core column bus. Pixel cores, consisting of 2×8 pixel regions ( 8×8 pixels), share a core column readout bus, with its associated controller in the DCB. – 30 – 2025 JINST 20 P03024 Figure 41. Pixel region logic for distributed latency counter buffering with TOT and Bunch-crossing ID time tags (Timestamp count). Hit detection is made per pixel, with storage of associated hit TOTs (blue). Hit time stamps are stored in common with associated buffer management logic, handling triggering and token based readout from the pixel array (yellow). Reproduced with permission from [12]. Figure 42. Left: pixel region latency buffer occupancy probability for the two alternative architectures evaluated. The selected architecture is the distributed latency counter buffers for 4×1 pixel regions. It has lowest hit loss for high hit rates and has the simplest and most compact implementation. Right: hit loss probability for distributed latency counter buffers with detector Monte Carlo hits at 3 GHz/cm 2 for 7, 8 and 9 buffer locations. Eight Buffer locations are used in final chip implementations as it fits in the available area and have acceptable hit loss in the highest rate regions (below 0.25 %). Reproduced with permission from [12]. – 31 – 2025 JINST 20 P03024 012345678 0.80 0.85 0.90 0.95 1.00 AllPrimary ROC3 [12.5 s] Digital Efficiency D = / A -corrected X-ray Hit rate [ GHz / cm 2] 0123456 ] 2 Experiment hit rate [GHz/cm 0.92 0.93 0.94 0.95 0.96 0.97 0.98 0.99 1 1.01 1.02 CROC buffering efficiency (regionto pixel-rate ratio: 0.655) = 0 inner ladder)η(TBPX layer 1, after simulation-based rate correction sµefficiency @ L1 latency = 12.5 Measured average CROC buffering Phase 2, PU 200 (14 TeV) CMS Simulation Preliminary Figure 43. RD53B-CMS X-ray hit loss probability from latency buffering as function of hit rate, measured in a non irradiated chip with a planar sensor. Left: corrected for analog TOT dead-time. Right: for estimated equivalent HL-LHC hit rate, with particle cluster size of 1.53 hits/cluster. Readout from the pixel array is initiated by the core column controller signaling the event ID and asserting a readout token. Pixel regions having triggered hit data await the arrival of the readout token and then assert their hit data on the readout bus together with its pixel region address and passes the token. When the token finally returns to the pixel core column controller, all event data in the core column for this event ID has been collected. Pixel core columns have independent readout controllers that can be in the process of reading out different events. This improves the effective readout rate from the array when having multiple pending triggered events. A central trigger table keeps track of events awaiting readout from the pixel array. A pixel core column bus is covering a large number of pixel regions. This limits the effective readout speed on this long bus and makes it significantly affected by radiation degradation of its bus drivers and handshake logic. The effective readout time is two clock cycles per pixel region with hit data, that with radiation degradation can get as long as 3(4) clock cycles (configurable). It has been confirmed in simulations that such a reduced pixel array readout speed is compatible with required hit and trigger rates. In practice it has not yet been seen necessary to use this extended readout period for highly irradiated chips. It is possible by configuration to constrain the maximum number of pixel regions to read out from each core column per event, to prevent possible readout congestion from events with excessive number of hits. It is also possible to constrain the maximum time available to readout all pixel core columns, thereby effectively constraining the maximum number of hits per event. An extended two level trigger mode for potential future trigger upgrades has been implemented. In this mode, L0 triggered hits remain in the pixel region latency buffers for a configurable time-out period (max 25.6 μ s). During this time-out period (L1 trigger latency), events can be flagged for readout (L1 accept), or by default be rejected (L1 reject). Event data accepted for readout will go through multiple levels of processing, event building, buffering and formatting, as shown in figure 44, before being ready for final readout via the serial readout links. Total event data buffering before final readout is of the order of 25 kBytes in the DCB. Significant hit data buffering also takes place in the pixel array, from when a trigger is received until having been read out from the pixel array. This buffering assures efficient hit data de-randomization that enables good readout bandwidth utilization. – 32 – 2025 JINST 20 P03024 Figure 44. Outline of processing and buffering of event data in multiple stages from pixel core columns, processed by End Of Column (EOC) logic, to final readout link Aurora formatting via Clock Domain Crossing (CDC) buffer. Intermediate FIFO’s are used for data buffering to enable the different stages to work concurrently to sustain the required bandwidth. Barrel-shifters are used for effective data merging and re-packaging of zero-suppressed event data between processing stages. Colors shown in data buffers represent event data, belonging to same triggered event, in different stages of processing. Data flow: triggered hits are read out of the pixel array with circulating read tokens in the core columns to hit map encoders with column addresses to EOC buffers. Hit data from EOC buffers are merged in two buffering stages (DC and CDC buffers) to form 64 bit data words for chip readout. 6 Control and readout The control and readout interfaces of the RD53 chips are highly constrained from their specific use in an inner high rate and low mass detector with lpGBT based optical links to DAQ and control systems. An efficient variable length hit data encoding format, called binary tree encoding, has been developed to minimize readout bandwidth. The use of 1, 2, 3 or 4 readout links per pixel chip, and the option of merging data from 2 or 4 chips into one link, enables the number of required readout cables to be optimized and minimized for different system configurations. Control and readout links use DC balanced encoding, for the AC coupled links required in a serially powered detector system. A 160 Mbits/s DC balanced differential control link, with transmission error detection, has been specifically developed to address up to 15 chips (e.g. chip specific configuration) and with broadcast capability (e.g. common configuration). It has an embedded 40 MHz reference clock with sub-ns timing control, to appropriately align pixel hit sampling with bunch collisions. Real time commands at 25 ns level have priority over control, configuration and monitoring commands. The control link has sufficient bandwidth to perform continuous scrubbing of pixel configuration, in case needed in the hostile radiation environment (see section 9). – 33 – 2025 JINST 20 P03024 A radiation hard 1.28 GHz Phase Locked Loop (PLL) has been developed for appropriate Clock and Data Recovery (CDR) from the control link and generate the clock for the serial readout links. Initial prototypes have been extensively tested and gradually improved to get lower jitter with sufficient TID and SEU/SET tolerance [ 21 , 22 ]. The PLL locks to the 160 Mbits/s control stream and generates the required on-chip clocks. The 40 MHz hit sampling clock is generated with a frame alignment circuit, based on regular sync symbols. It can be phase shifted in steps of 0.78 ns to perform precise time alignment to particles from the HL-LHC collisions. The PLL is separately powered to allow additional external filtering of the analog chip power in case needed. The classical PLL architecture, with frequency and phase detectors, is shown in figure 45 with measured jitter and eye diagram of a readout link shown in figure 46. Figure 45. PLL generating high frequency clocks used in the chip. PLL control loop with combined Phase Detector (PD) and Phase - Frequency Detector (PFD) controlling a Voltage Controlled Oscillator (VCO) via analog Charge Pumps (CP) and loop filter. Frequency multiplication from the 160 Mbits/s control link to the 1.28 GHz serializer clock is obtained with SEU protected counters (CNT and DIV). Figure 46. Measured eye diagram and PLL jitter on 1.28 Gbits/s serial readout. Particular emphasis has been put on efficient and reliable startup, resetting and configuration of the chips for use in a serially powered detector system in a hostile radiation environment. At – 34 – 2025 JINST 20 P03024 power-on startup (see also SLDO startup in section 7) the chip will initially use a default hardwired configuration. Only when all critical re-configuration data have been downloaded, will these settings be activated with a dedicated enable code. Full chip data path and buffers can be cleared quickly or specific parts of the chip can be reset with specific commands. In a worst case scenario where control link synchronization is lost, and it does not self recover as it should normally be the case, a dedicated link reset can be applied that initializes all chip configuration and starts a full chip re-synchronization (as done at power up). This is done by running the control link at a low frequency (invalid link bit rate, but still compatible with AC coupling), that is detected by the chip to be out of normal working range. This removes the need of using power cycling to recover chip operation, which is highly undesirable in a large serial powered system with high voltage sensor biasing. Up to 4 readout links of 1.28 Gbits/s (or 640 Mbits/s or 320 Mbits/s) are available per chip for readout and monitoring. A subset of the Aurora encoding [ 20 ] is used as it supports all the required features: DC balanced 64B/66B encoding, framing with minimum overhead, multi lane support, data and service type frames. Aurora formatting is well documented and well supported for FPGAs in test and DAQ systems, with general event and service data formatting as indicated in figure 47. When used in final ATLAS/CMS pixel detectors with lpGBT optical links, two levels of link encoding (Aurora 64B/66B plus lpGBT FEC) will be present, to be decoded by the DAQ system FPGAs. It should be noted that Aurora formatting does not use Forward Error Correction (FEC). Single bit transmission errors (or SEUs in pixel chip serializer) can therefore occasionally cause the corruption of event fragments. The use of FEC was considered but it was found to have too large bandwidth overhead, especially in combination with the extensive error correction used in the lpGBT. The RD53C-CMS chip has the option to add a CRC (Cyclic Redundancy Check) at the end of each event. Raw zero-suppressed hit data from the pixel regions consist of a pixel region address followed by 4 bit TOT information from the 4 pixels in the region, with TOT=1111 bin indicating no hit. This is already a relatively efficient data format for clustered hits, compared to individual pixel hit addresses with TOT (18 bit pixel address + 4 bit TOT = 22 bit per hit). An optimized binary tree hit encoding scheme can further reduce readout bandwidth by 10–20 %. It is also possible to suppress TOT charge readout information, having only binary hit information, giving a data reduction of ∼30 %. In binary three encoding, the 16 bit hit map from 4 pixel regions covering 8×2 pixels, is encoded to produce a compressed hit map representation, with fewer than 16 bits per hit on average for clustered hit data. The algorithm divides the hit map, containing one or multiple hits, in half (e.g. upper and lower half as shown in upper right corner of figure 47) and labels each half as containing hits (1) or not (0). This is applied recursively to every non-empty hit pattern until only 2 bit hit patterns are left. A bit code substitution is then applied to compress this. In any step, the two-bit code 00, for the two halves without hits, is zero-suppressed. Code 01 is represented by a single bit set to 0, while 10 and 11 are kept as a 2 bit code. This results in a compressed 16-pixel hit map with between 5 bits (single hit) and 30 bits (all 16 pixels hit). The encoded hit map is preceded by a pixel hit map address (location in full pixel array) and followed by pixel hit TOT(s). This encoding is in the chip implemented with simple and fast logic based on a small look-up table. A complex Huffman encoding was in simulations seen to obtain 10-20 % better compression on HL-LHC data, but requires complex on-chip processing. The effective number of bits per hit with binary tree encoding has with Monte Carlo hit data been seen to be in the range of 10-15 bits/hit, as shown in figure 48 depending on cluster size. This can be compared to the raw zero-suppressed hit data format with 14-28 bits/hit. – 35 – 2025 JINST 20 P03024 Figure 47. Outline of event building with binary hit encoding and readout formatting. Upper left: event building, with hit encoding (Enc) and buffering (FIFO), between event fragments (triggered hits) from pixel array core columns, made from pixel cores with pixel regions, to final event data streams. Upper right: binary tree hit encoding, taking advantage of multiple pixel hits in local clusters. Lower: encoding of pixel data (physics event data) and service data (monitoring or register reads), indicated in 64B/66B frames. Pixel data consists of a 8 b event tag/ID and binary tree encoded pixel addresses, followed by corresponding TOT information that can optionally be omitted. Pixel data from single triggered events can be contained in well separated single-event streams, indicated with EOS (End Of Stream) = 1, with required 64B/66B frame bit padding at the end. Alternatively pixel data readout can be made with multi-event streams, with reduced bit padding overhead. Service data frames are sent at regular intervals (configurable) with requested monitoring and configuration read-back data. Reproduced with permission from [11] When having a small number of pixel hits per chip, as is the case for outer pixel layers, a relatively large overhead is used for event header information and required 66 bit frame padding at the end. An optional multi-event stream formatting, with multiple events sharing a single transmission stream, can reduce this overhead. It must though be kept in mind that a single bit transmission error (or SEU, SET) can then corrupt multiple events. It is therefore encouraged to use single stream event formatting when ever possible, as this enables correct data decoding to be reestablished at the start of each event. Data merging between chips is available for low rate outer pixel layers, to merge readout data from 2 or 4 chips on a pixel module into a single readout link, thereby significantly reducing the number of – 36 – 2025 JINST 20 P03024 6− 10 5− 10 4− 10 3− 10 2− 10 Pixel occ. 10 2 10 Avg. hit size [Bit] ηCluster extends in Cluster size = 1 Cluster size = 2 Cluster size = 3 Cluster size = 5 Cluster size = 10 6− 10 5− 10 4− 10 3− 10 2− 10 Pixel occ. 0.6 0.8 1 1.2 1.4 Binary/Plain Figure 48. Simulated number of bits per hit with binary tree encoding and 4 bit TOT as function of pixel hit occupancy and cluster size. Lower: relative data bandwidth gain from binary tree encoding. required readout links/cables. A primary chip is driving a single 1.28 Gbits/s readout link and 1 or 3 secondary chips drive 320 Mbits/s serial data on a local single or dual lane link to the primary chip. Chip to chip data merging requires the chips to be driven by the same control link and the interface is based on oversampling at 640 MHz in the primary chip. Used in a flexible manner, a quad pixel chip module can be configured to have 4, 3, 2 or only 1 readout links as shown in figure 49. Data merging uses simple frame by frame time multiplexing with a 2 bit source ID, so the DAQ system must handle 2 or 4 independent event streams on the readout link. Event readout latency (time interval from receiving trigger message to completion of corresponding event readout) will have a complex dependency on statistical fluctuations in hits and triggers and the available readout bandwidth as indicated in Monte Carlo simulations shown in figure 50. The readout latency can become particularly long if the readout bandwidth is highly utilized (e.g. above 90 % ). The chip will eventually be forced to drop events, if on-chip data buffers run full (flagged in chip monitoring). Readout links are driven by differential CML (Current Mode Logic) drivers with configurable drive current and pre-emphasis. The driver has a 100 Ohm differential output impedance, assuring the best possible matching to low mass 100 Ohm differential electrical cables (twisted pair, flex micro strip-lines, twinax), with the absorption of possible transmission reflections. 7 Power and references RD53 chips have on-chip SLDO power regulators for serial powering of pixel modules, with chips on the same module connected in parallel [ 30 ]. Serial powering of parallel connected chips on a pixel module enables the use of a single shared pixel sensor for multiple chips and also assures system reliability when having pixel chip power failures (opens). The SLDOs can also be (hardware) – 37 – 2025 JINST 20 P03024 Figure 49. Data merging between primary and secondary chips on a flexible quad module that can be configured to have 4, 3, 2 or 1 active readout links. Up to four 1.28 Gbits/s readout links shown in blue on module connector in center. Local 320 Mbits/s data merging links between chips shown in yellow. Figure 50. Simulated readout latency for pixel chip with 3 readout E-links. Upper: at 2.7 GHz/cm 2 hit rate, for different trigger rates. Lower: at 1 MHz trigger rate, for different hit rates. It can be noticed that the readout latency gets excessively long above an average readout link utilization of 90-95 % . Above a readout link utilization of 95% there is a significant risk of loosing event fragments. – 38 – 2025 JINST 20 P03024 8 Monitoring RD53 chips have extensive on-chip monitoring capabilities [ 36 ] covering: on-chip temperature sensors, pixel module temperature with external NTC (Negative Temperature Coefficient) thermistor, SLDO input and output voltages and currents, internal references and biasing levels, plus radiation effects monitoring. Analog monitoring is performed with an ADC conversion request command on the control link followed by an ADC read request. Monitoring data are read out in dedicated Aurora service frames on the readout links as indicated in figure 47. Analog monitoring is made with a multiplexed 12 bit switched capacitor ADC [ 37 , 38 ] with layout shown in figure 60 and with measured resolution and linearity as shown in figure 61. Absolute ADC calibration per chip is performed during wafer probing, with ADC calibration parameters for each chip being stored in a central data base. Figure 60. 12 bit switched capacitor monitoring ADC layout with analog monitoring multiplexer. Figure 61. 12 bit ADC linearity and INL. The switched capacitor ADC core has been shown to have excellent radiation tolerance. However, radiation test campaigns have shown a significant drift of about 5% for 500 Mrad, 10% for 1 Grad, for monitored voltages. This originates from a TID drift of the ADC reference, which directly impacts – 45 – 2025 JINST 20 P03024 voltage measurements as shown in figure 62. A method to correct for the TID drift of the ADC reference has been developed, based on specific properties of the used temperature sensors as described below. Three temperature sensors in the chip bottom, close to the SLDO power regulators, are based on large-area NMOS transistors biased in sub-threshold region. Temperature measurement accuracy has been greatly improved by making multiple measurements at different currents (configurable) in the NMOS sensor. It has been possible to demonstrate an effective temperature linearity and resolution of ∼1◦ C as shown in figure 63 with good TID tolerance. This measurement does not depend on the ADC reference voltage and allows to contain TID effect drifts to values lower than 2 ◦ C at 500 Mrad [ 36 ]. This allows to deduct the real voltage across the temperature sensors and use the apparent voltage measured by the ADC to correct other voltage measurements accordingly to get an effective TID drift of 1–2% for voltage monitoring. Two resistive temperature sensors with lower resolution are available to measure temperature gradient across the pixel array. These resistive temperature sensors are very narrow to fit on top of the pixel array. Figure 62. RD53B monitoring dependency on radiation induced ADC reference drift. When using the ADC to measure radiation drifts in the biasing reference, VREFA, the apparent TID drift seems small (yellow), as both references have similar TID drifts. If VREFA is measured with an external ADC (blue & green) then its real 5 % TID drift at 500 Mrad becomes visible. Radiation effects monitoring of digital logic is made with a set of digital ring oscillators with different gate types and transistor sizes and for analog transistors by direct analog measurements on a few reference MOS transistors. The ring oscillator frequency is measured using the 40 MHz chip/system clock as reference, from which the effective gate delay can be calculated. Typical gate delays of the implemented ring oscillators can be seen in figure 65 as function of TID. 9 Radiation tolerance Achieving the required radiation tolerance of the RD53 pixel chips of 1 Grad for 10 years operation in inner pixel layers at HL-LHC has been a major challenge. The used 65 nm technology has been seen to have excellent radiation tolerance up to dose levels of ∼100 Mrad [ 39 ]. To reach an effective TID tolerance of up to 1 Grad, the RD53 collaboration has invested significant efforts on radiation effects studies with dedicated radiation test chips. Initially it was thought impossible to implement such a complex mixed signal chip with 1 Grad radiation tolerance, as radiation tests showed large transistor and circuit degradation at radiation levels above 100 Mrad. With systematic radiation tests – 46 – 2025 JINST 20 P03024 Figure 63. Calibration of 3 (A,C,D) on-chip MOS based temperature sensors in climatic chamber. The NTC thermistor is a reference sensor on the test board. The measured temperature difference between the climatic chamber and the NTC sensor is caused by the pixel chip power dissipation. Dotted line showing ideal curve, as an eye guide. of different transistor types and sizes under different irradiation conditions (voltage, temperature, dose rate), indications were found on how to reach 500 Mrad, and potentially higher, radiation tolerance with specific design constraints and under particular operation conditions. Dedicated analog and digital circuit test chips were made to confirm that this seemed viable [ 41 – 43 ]. Finally, it has been confirmed with full sized pixel chips (RD53B/C generations) that 1 Grad is feasible, when using specific design precautions and operation conditions as outlined below. Wide transistors have excellent radiation tolerance without significant leakage (other similar technologies have been seen to have transistor leakage issues). This has enabled appropriately designed analog circuits to demonstrate excellent radiation tolerance. In the RD53B chips, issues were seen with increased mismatch in critical current mirrors for biasing different parts of the chip. The origin of this was traced to be an x-ray shielding effect from thick top copper routing layers above critical transistors, as was seen to be significantly smaller with proton irradiation. In final RD53C chips it is assured to have the same thick copper routing above critical current biasing transistors. Narrow transistors show large radiation degradation, with additional detrimental annealing when operated at elevated temperature, especially under specific biasing conditions, as indicated in figure 64. Narrow 65 nm gate length transistors are critical in high density logic, particularly needed in the pixel array logic. Transistors in digital logic are only under worst case biasing conditions during very short signal transitions. Not using the highest density digital library (with name extension Drive0) but instead the second highest density library (Drive1), with wider transistors, gives significantly improved radiation tolerance. From Drive0 to Drive1 gate cells, the output transistors have increased (double) gate width (W) and therefore significantly improved radiation tolerance. From Drive1 to Drive2 (and higher drive) gates, multiple parallel output transistors are used, of same size as used in Drive1. Drive1 and Drive4 cells therefore have very similar radiation tolerance characteristics. Finally, it was determined that if used cold (below −10 ◦ C) and never (less than a few days) powered at room temperature after high TID exposure, the observed detrimental annealing can be kept under control. The basic mechanism behind this behavior has now been understood [ 39 ] and confirmed. It is caused by radiation induced trapped charges in gate spacers that at elevated temperature and under specific biasing conditions drift into active gate regions. Initially the pixel chip operation temperature – 47 – 2025 JINST 20 P03024 Figure 64. PMOS Ion drive capability radiation degradation of short channel (60 nm digital) transistors of different width under worst case biasing conditions ( 𝑉DS =1.2 V, 𝑉GS =1.2 V) at −15 ◦ C (left) and related detrimental annealing (right) at different temperatures. Reproduced with permission from [ 41 ]. ©CERN 2015. CC BY 3.0. was estimated to be −20 ◦ C, but has with more detailed thermal modeling of the pixel detectors been seen to be up to −10 ◦ C in certain locations. No significant difference in radiation tolerance has been seen between −20 ◦ C and −10 ◦ C operation temperature. With these design and operation constraints (below −10 ◦ C), digital logic will after 1 Grad still have a ∼50 % speed degradation, when irradiated at high dose rates (1 Grad in 1 week). When irradiated at low dose rates the speed degradation was found to be significantly more. Low dose rate effects have been characterized in dedicated long term X-ray, cobalt source and Kr85 source irradiations [ 40 ] with an effective speed reduction of a factor 2–3 for the used digital library, as shown in figure 65. This is taken into account in the RD53 design flow using a specific extreme timing corner case. Initially a dedicated radiation corner for the used digital libraries was developed in RD53. It was then realized that using a very low voltage corner provided by the foundry (0.9 V, worst case process and −40 ◦ C) in practice results in similar timing and have been used for timing closure of final RD53C designs. Full scale RD53B chips have in low dose rate irradiation tests [ 49 ] indicated a projected radiation tolerance to the Grad level as shown in figure 66. This demonstrates that appropriate gate delay radiation models have been used in the full chip design flow, to assure long term irradiation tolerance (low dose rate effects). Integrated on-chip analog and digital radiation effects monitoring (see section 8) allows this to be monitored during operation and can be used to predict if an inner pixel layer needs to be replaced. The current prediction is that final RD53C chips will be capable of taking 1–1.5 Grad over 10 years of operation in an appropriately cooled and operated pixel detector. Pixel assemblies made of sensors and chip have been exposed to 10 16 hadrons/cm 2 and have, as expected, not been seen to be affected by NIEL (Non Ionizing Energy Loss), as it is generally the case for CMOS processes. Final production chips will be produced in the same fab as the prototypes, as there have been indications of differences between fabs of the same technology node. Radiation tolerance tests of production batch samples will be necessary to assure that required radiation tolerance is maintained during the wafer production period. Production batches with indications of reduced radiation tolerance can – 48 – 2025 JINST 20 P03024 Figure 65. Gate delay degradation of Drive0 and Drive4 gates at High Dose Rate (HDR), upper left, and Low Dose Rate (LDR), upper right. Relative delay degradation between Low dose rate and High dose rate at different dose rates. Drive4 uses same transistor width as Drive1, but with multiple parallel output transistors for higher drive capability. They therefore have similar relative radiation degradation. if needed be used for outer pixel layers ( ∼100 Mrad and majority of chips needed). It is planned to make further irradiation tests of final pixel chips to extremely high levels (multiple Grad) until they show signs of failing because of TID. Tolerance to SEU and SET effects is the other critical requirement for a chip with complex digital logic. A RD53 chip is estimated to have ∼100 SEU upsets per second in inner pixel layers, based on the measured SEU cross-section of used memory elements. SETs can be assumed to be of the same order of magnitude. This makes it a major challenge to assure sufficiently reliable operation of thousands of chips. Systematic use of well known general TMR (Triple Modular Redundancy) schemes, and related specific tools [ 44 ], can resolve this, but at an excessive cost in terms of area and power overhead (factor 3). In particular in the large and dense pixel array logic it is not feasible to fit TMR protection. Critical pixel configuration bits have triplicated latches, without auto-correction feedback. Continuous pixel re-configuration can be done at a rate of up to 10 times per second with the available control – 49 – 2025 JINST 20 P03024 Figure 66. Projected low dose rate limit of RD53 chip based on low dose rate irradiation of Drive4 (and Drive1) gates. Gate delays have been measured with low dose rate radiation characterization of ring oscillator test circuits. A maximum tolerable gate delay increase of 200 % has here been defined as the limit, as this is the effective timing margin obtained with the used gate timing models. link bandwidth. Protection from SEUs and SETs with TMR in remaining pixel array logic can not fit in the highly constrained area. This has with simulations been estimated to cause fake or lost hits below 0.01 % of the actual hit rate. The Digital Chip Bottom (DCB) contains critical chip functions that can not be allowed to be upset by SEU/SET, as the chip may then get into a dead-locked state, lose system synchronization or get mis-configured. Critical functions (global configuration, Trigger table, state machines, buffer pointers and critical event information) have full TMR. However, hit data in data buffers and processing pipelines are not protected. This strategy has resulted in ∼25 % of registers in the DCB to have TMR protection. With such a partial protection scheme it is critical not to overlook critical memory elements that require protection. This is a delicate task requiring careful verification with SEU simulations (see section 11). It can also be mentioned that RD53 chips specifically use event tags, included in trigger commands, to prevent event de-synchronization to occur because of SEUs in local chip event ID counters. TMR of selected registers can be done in different fashions that must be carefully chosen based on the characteristics of the design and how best to integrate this into the chip design flow. The selective TMR protection has been made at gate level, after RTL logic synthesis. Based on register names, with a specific name extension, single Flip-Flops (FF) have been replaced with triplicated flip-flops with Majority Voting (MV). Triplicated clocks are introduced in the design for TMR protected FFs in appropriate clock domains (40 MHz, 64 MHz, 160 MHz, 640 MHz, 1.28 GHz). SET filtering for TMR FFs is obtained with a time skew between the triplicated clocks such that short SET glitches will only be seen by a single TMR FF and then filtered by the TMR majority voter as indicated in figure 67 [ 47 ]. This approach does not require triplication of TMR voters and combinatorial logic as it prevents SET glitches to propagate to multiple TMR nodes. Triplicated clock skew was for the RD53B chips set to 300 ps, based on SET glitch width measured with a dedicated test chip [ 48 ]. It – 50 – 2025 JINST 20 P03024 Figure 67. SEU/SET protection used for critical storage nodes in digital chip bottom. Critical flip-flops are triplicated to resolve SEUs. SETs in logic, MVs (Majority Voter) and clock drivers are time filtered by using triplicated clocks with centralized clock skews (dt0, dt1, dt2). This scheme does not require triplication of MVs and logic, giving significant area savings. has been measured that the used partial TMR protection with triplicated skewed clocks has reduce the effective SEU cross section by a factor of 400. The triplicated clock skewing has in final RD53C chips been increased to 400 ps to further diminish the SEU and SET cross-section (see section 10). Quick and efficient production testing of the implemented TMR protection can be done by disabling one by one the triplicated clocks, and check that the chip continues to work correctly. Extensive SEU/SET tests have been made of the RD53B chips [ 45 , 46 ]. Occurrences of relatively long readout link dropouts, as shown in figure 68, were seen in ion beam tests. It was confirmed in dedicated laser injection tests to be caused by short SET glitches in the biasing generating circuit, being extended to multi microsecond long biasing shifts to the PLL. The cause was confirmed with detailed circuit simulations with a dedicated analog simulation setup for SET/SEU sensitivity analysis. Biasing circuit topology changes have been implemented, based on detailed SET simulations at transistor level, to resolve this in final production chips. A critical issue with the chip event readout getting stuck was also identified and resolved based on extensive SEU verification simulations (see section 11). The critical (and sensitive) PLL has been implemented in full custom layout with triplicated counters. During its normal operation it uses a simple bang-bang phase detector, where occasional SEUs and SETs in the phase detector can only introduce very small jitter (few ps). Recent ion and proton beam tests with the RD53C chip have confirmed that final production chips have significantly lower SEU and SET sensitivity. Link dropouts are not observed any more. When actively processing high hit and trigger rates, the RD53C chip is seen to have a HEH (High Energy Hadron) cross section a factor ∼30 better than the RD53B. The effective HEH cross section for event readout getting stuck has recently been measured to be lower than 3×10−13 cm −2 . In inner pixel layers this will correspond to a pixel chip running for an average period of ∼1 hour before having readout issues. This is considered acceptable for a small number of inner layer pixel chips in such a hostile radiation environment. Regular system level fast buffer clear commands can be issued at rates as high as several Hz, without significant system dead-time, when having a DAQ system that – 51 – 2025 JINST 20 P03024 Figure 68. Measured SET occurrence of long link dropout of RD53B chip in an ion test beam. A sudden PLL frequency jump occurs at the time of the SET and it takes 18 μs for the PLL control loop to recover frequency and phase lock. On the upper trace it can be noticed that the serial link output amplitude is also affected by the SET in the central biasing circuit and recovers much slower than the PLL, as not part of an active compensation control loop. can handle this appropriately. Further system level studies are ongoing to determine how the DAQ and control systems of the experiments can handle this efficiently. An unexpected small number of Single Event Latchups (SEL) were observed in the digital part of the RD53B chip at an increased supply voltage of 1.3 V in a dedicated ion test at highest Linear Energy Loss (LET) and 45 ◦ incidence angle with an equivalent LET eff of 88 MeV × cm 2 /mg. This has not been seen before in the used 65 nm CMOS technology and came as a surprise as a digital library with substrate and well taps in each gate has specifically been used to avoid possible latchup issues. It has been verified that events with so high LET eff will not occur in practice in the HL-LHC environment (e.g silicon recoils from nuclear reactions). It has also been verified that SEL is not seen in the ion beam when the digital logic is powered at its nominal voltage of 1.2 V (it is known that SEL is very voltage dependent at low power supply voltages). If such a latchup would exceptionally occur in final systems, it is not expected to cause permanent chip damage in a serially powered system, driven by a constant and limited current. 10 Implementation RD53 chips are implemented in a 65 nm CMOS technology with the maximum allowed metal stack consisting of 7 thin, 1 thick and 1 ultra-thick metal layers, and an additional top redistribution layer also used for power distribution where appropriate. The general floor plan is as shown in figure 8, and consists of the large pixel matrix of 150 k 50 ×50 μm2 pixels and the Digital Chip Bottom (DCB), the Analog Chip Bottom (ACB) and the IO pad frame with SLDO power regulators. The pixel array is assembled from 8×8 pixel cores including sixteen analog islands of 2×2 front-ends embedded in a sea of digital logic as shown in figure 69. Analog and digital circuits are – 52 – 2025 JINST 20 P03024 implemented in separate triple wells to assure best possible noise isolation. Pixel cores have embedded power, analog and digital signal routing to make pixel core columns from abutment of pixel cores, and from this build the complete pixel array. Pixel cores have built-in digital signal buffers and skew compensation for time critical signals (clock and calibration injection) to guarantee a max time skew across the array of 1 ns ( ∼2 ns after 1 Grad). Skew compensation is implemented in the pixel cores as shown on the right of figure 69 with a configurable delay before the local clock distribution network. The configurable skew compensation delay is driven by the pixel core address (defined by location) to get well aligned pixel clocks for different process, temperature and voltage corners as show in figure 70. It can be noticed that the skew compensation delay is effectively adjusted for each four pixel cores. Pixel core logic has been synthesized with appropriate conservative constraints to build a functional pixel core column without timing constraints violations. A timing model of the pixel core has been extracted by the Cadence Liberty tool to assure accurate pixel array timing used for full chip assembly and verification. The pixel core has also been extensively simulated at analog level to assure the best possible verification of AFEs together with the digital pixel logic (see section 11). Figure 69. Pixel chip implementation with physical hierarchy used to build the pixel array. The pixel array is assembled from pixel core columns made from pixel cores with 8×8 pixels. Clock skew compensation along the pixel core column is built into the pixel cores, with its local delay determined by position along the column. Figure 70. Time skew along pixel column for clock and pixel charge injection for different process corners and estimated 1Grad irradiation, from gate level timing models. Logic synthesis, place & route and timing optimization of the DCB, with pre-placed analog blocks in the ACB, has been performed with the pixel core timing model with dedicated conservative – 53 – 2025 JINST 20 P03024 process, voltage and temperature corners (e.g. supply voltage specifically set to 0.9 V instead of 1.2 V, as mentioned in section 9) to get the required TID radiation tolerance. As part of the design flow, triplication of critical FFs is performed at the end of logic synthesis with dedicated triplicated clocks with strict timing constraints (and time skew as mentioned in section 9). Placement is enforced to keep a minimum spacing between TMRed FFs to prevent correlated multi-bit SEU upsets to disturb correct function of the chip. A histogram of final TMR FF distance is shown in figure 71, where it can be seen to have complied to the minimum distance constraint of 15 μm . This distance has by the HEP electronics community been seen to be give good assurance that multi bit flips will be unlikely. Figure 72 shows that an average TMR clock skewing of 400 ps has been obtained in the final RD53C chips (was 300 ps in RD53B chips). For a small number of FFs the effective local clock skew between the three TMR FFs are just below 200 ps (typical case process) which is considered acceptable. It was attempted to get the place and route tools to reduce the tails of the clock skew distribution but convergence was not obtained after several days of running and the tools eventually crashed. Figure 71. Distributions of distance between pairs of triplicated TMR flip-flops in final RD53C chip. Power distribution in such a large complex mixed signal chip is critical and has been verified with dedicated Voltus power simulations as shown in figure 73. Detailed gate level simulations are required to drive dynamic power distribution verification but the RD53 chip is so large and complex that the available tools for this crashed. Dynamic power verification has therefore been made as a combination of a detailed single core column simulation and full chip verification using a simplified core column. This is seen to be compatible with the observed RD53B ground (and VDD) voltage drop measurements as shown in figure 59. All metal layers have been used to get the best possible power distribution, so it is in practice not possible to improve this. The full sized pixel chips with this passive on-chip power distribution have demonstrated that they meet all requirements. The wire-bonding pad-frame, with 100 μm pitch, is identical for all RD53B and RD53C generation chips, enabling the use of common testing infrastructure consisting of single chip test cards and wafer probing cards. A large majority of the wire-bonding pads are used to supply power to the chip and have low inductance connections to external decoupling capacitors, as shown in figure 74. The final RD53 chip implementations contain 660 M transistors, 56 M standard cells and 12 M memory elements. 2.1 M memory elements are used to implement 700 k TMR protected bits, of which 85 % are pixel configuration bits and 15 % are used in the DCB. Overall for the complete design 7 % of logical bits have TMR protection. – 54 – 2025 JINST 20 P03024 the overall yield has been seen to be as good as ∼90 % in 50 pre-production wafers as shown in figure 82. A breakdown of typical chip rejects per wafer, for different tests, is shown in figure 83. Extracted performance and calibration parameters are stored in appropriate databases to be used for configuration and cross checking with pixel module and system tests. Individual chips are traced during dicing, handling and mounting on pixel modules with a chip ID burned in E-fuses during wafer probing. This chip ID can though not be guaranteed to be readable after irradiation ( ∼100 Mrad). A complete test and characterization of a wafer with 131 chips takes 8–16 hours, giving a wafer throughput of 1–2 wafers per day per probing station. Wafer probing facilities have been set up in institutes of each experiment to test all production chips within a year. Figure 80. Example of wafer testing selecting criteria for measured reference current (Iref) and its tuning. Left: untuned reference current, Middle: tuned reference current, Right: Iref tuning settings distribution. Green is acceptance criteria for pixel module production, yellow is acceptance for prototype pixel modules and red is chip reject. Ignored label used to indicate that measured parameter not used for final chip selection (so in this case only based on tuned Iref, and not on untuned Iref and tuning settings. 1.0 1.1 1.2 1.3 1.4 1.5 V 0 250 500 750 1000 1250 1500 1750 # Chips Yield green: 6445 (98.4%) yellow: 16 (0.2%) red: 84 (1.3%) blue: 5 (0.1%) Mean: 1.198 Std: 0.008 VDDD after trimming 1.18 to 1.22 0.0 to 1.1 1.3 to 1.5 1.1 to 1.18 1.22 to 1.3 0 2 4 6 8 10 12 14 Trim Bit 0 200 400 600 800 1000 1200 1400 # Chips Yield green: 6463 (98.7%) yellow: 86 (1.3%) red: 0 (0.0%) blue: 1 (0.0%) Mean: 8.19 Std: 1.784 VDDD Trim Bit 1.9 to 13.1 -0.5 to 1.9 13.1 to 16.0 Figure 81. Wafer level testing of tuned SLDO output voltage (VDDD). Left: tuned SLDO output voltage. Right: used VDDD trimming bits to obtain narrow VDDD voltage distribution among chips on 50 wafers. Pixel module tests with different bump-bonded sensors (planar, 3D, 50×50 μ m 2 , 25×100 μ m 2 ) and different module configurations (single, dual, quad chips) have been performed by the ATLAS and CMS pixel detector groups in test beams and with radioactive sources with fully satisfactory results. Pixel module integration issues related to bump-bonding yield and micro cracks from thinned chip dicing, close to the active chip circuits, have been encountered. These will be resolved with improved chip dicing procedures (e.g. laser grooving followed by saw dicing), improved procedures for bump bonding and improved pixel module production and quality assurance procedures (e.g. gluing with radiation hard glues). – 61 – 2025 JINST 20 P03024 Figure 82. RD53C-ATLAS wafer yield map for 50 wafers. Figure 83. RD53B-CMS chip rejects for 8 wafers for different tests. To be noted that failing chips are often rejected by multiple tests, so typically only 10-20 chip rejects per wafer. Certain test failures also excludes other tests to be performed (e.g. power supply short). – 62 – 2025 JINST 20 P03024 A measured gamma ray spectrum of an Am-241 source is shown in figure 84. Finally a clear beam spot can be seen in figure 85 from a triggered proton beam test together with a X-ray tomography of a quad pixel module, based on detected pixel hits in the module itself. Figure 84. Am-241 gamma source test of RD53B-ATLAS partially bump-bonded single chip module. Left: spectrum measured with the high precision TOT option and threshold of 1000 e. Right: hit map of partially bump-bonded module with Sintef 3D sensor. Unconnected pixel bumps clearly seen as low hit count pixels (blue) with a few noise hits. System integration tests with serial powering and concurrent readout, as shown in figure 5have demonstrated fully satisfactory chip, module and system performance for use in the pixel detectors of the two experiments. Extensive pixel module and system tests will continue to be made in the coming year in the two experiments with RD53C production chips. 13 Conclusions The RD53 collaboration has over the last 10 years successfully developed two large complex mixed signal hybrid pixel detector chips for use in the ATLAS and CMS HL-LHC upgrades. It has been a major challenge to assure required lifetime (TID) and reliability (SEU/SET) for such an unprecedented hostile radiation environment a few cm from the interaction points at the heart of the ATLAS and CMS experiments. A novel serial powering concept has been developed for the on-chip power regulator that has been qualified and verified at system level for low noise use with up to 64 pixel chips in a serial power chain, giving major material budget reductions in the pixel detectors. Flexible control and readout interfaces enable the pixel chips to be employed efficiently across pixel detector systems with highly varying hit and readout rates. Final production chip versions have recently been submitted and are currently under thorough verification and testing at pixel module and system level in the two experiments, so the production of tens of thousands of pixel modules can get started for their integration into the upgraded ATLAS and CMS pixel detectors. It has been a major effort for a large number of collaborators (students, post-docs, physicists and chip design engineers) across 24 institutes to get to this point after 10 years of extensive R&D. Many expected challenges and unexpected problems have gradually been resolved by a collective effort, that constantly had to be adapted to an evolving design team with regular departures of experienced team – 63 – 2025 JINST 20 P03024 Figure 85. RD53B-CMS quad pixel module tests. Upper: triggered proton beam profile with large pixels between chips clearly visible. Lower left: X-ray tomography with X-ray hit count as registered by quad chip pixel module. Lower right: 2D noise map of same quad chip pixel module. members. It has been an additional challenge to handle two slightly different chip versions. For future pixel chips of increased performance and complexity with significantly increased IC technology costs, it is recommended to develop common chips to use efficiently available HEP (High Energy Physics) chip design resources. The RD53 design team has worked very well across the two experiments. It has also been highly beneficial for the two pixel detector communities to have an open information flow on chip, module and system issues and sharing appropriate solutions. Acknowledgments We would like to thank and acknowledge our colleagues in the ATLAS and CMS pixel projects for their help, patience and extensive work getting to final production chips. A large number of people have been involved in defining appropriate chip specifications and make extensive chip and system tests with serially powered pixel modules with different pixel sensors. We would also like to thank the CERN micro electronics group for their extensive technology support and handling communications with IMEC and the foundry for chip prototyping and production, as supported by the EU Europractice chip design program. – 64 – 2025 JINST 20 P03024 The solid and long term support from participating RD53 institutes has been critical for us to reach a successful end of 10 years of challenging R&D for these particularly difficult detector applications in an unprecedented harsh radiation environment. Funding has been provided by the following agencies: CERN; MEYS CR (Czech Republic); CEA and CNRS/IN2P3 (France); HGF and MPG (Germany); GSRI, Greece; INFN, Progetto Dipartimento di Eccellenza, University of Torino (Italy); NWO (Netherlands); RCN (Norway); MCIN/AEI and PCTI (Spain); Swiss Funding Agencies (Switzerland); STFC (United Kingdom); Department of Energy (U.S.A.). References [1] RD53 collaboration web pages, http://cern.ch/RD53. [2] ATLAS collaboration, Technical Design Report for the ATLAS Inner Tracker Pixel Detector, CERN-LHCC-2017-021, CERN, Geneva (2017) [DOI:10.17181/CERN.FOZZ.ZP3Q]. [3] A. Dominguez et al., CMS Technical Design Report for the Pixel Detector Upgrade, CERN-LHCC-2012-016 (2012). [4] lpGBT, low power GigaBit Transfer link chip,https://lpgbt.web.cern.ch/lpgbt/. [5] M. Garcia-Sciveres et al., The FE-I4 pixel readout integrated circuit,Nucl. Instrum. Meth. A 636 (2011) S155. [6] CMS Tracker Group collaboration, Evaluation of planar silicon pixel sensors with the RD53A readout chip for the Phase-2 Upgrade of the CMS Inner Tracker,2023 JINST 18 P11015 [arXiv:2307.01580]. [7] ATLAS collaboration, Letter of Intent for the Phase-II Upgrade of the ATLAS Experiment, CERN-LHCC-2012-022, CERN, Geneva (2012). [8] D. Contardo et al., Technical Proposal for the Phase-II Upgrade of the CMS Detector, CERN-LHCC-2015-010 (2015) [DOI:10.17181/CERN.VU8I.D59J]. [9] RD53 collaboration, RD53B users guide,CERN-RD53-PUB-21-001, CERN, Geneva (2020). [10] RD53collaboration collaboration, RD53B Manual,CERN-RD53-PUB-19-002, CERN, Geneva (2019). [11] RD53 collaboration, RD53C Chip Manual,CERN-RD53-PUB-24-001, CERN, Geneva (2024). [12] S. Marconi, Design and Optimisation of low Power Hybrid Pixel Array Logic for the Extreme hit and Trigger Rates of the Large Hadron Collider Upgrade, Ph.D. thesis, Perugia University, Perugia, Italy (2018). [13] A. Paterno, Ultra high-density hybrid pixel sensors for the detection of charge particle, Ph.D. thesis, Torino University, Torino Italy (2019) https://iris.polito.it/handle/11583/2743337. [14] F. Krummenacher, Pixel detectors with local intelligence: an IC designer point of view,Nucl. Instrum. Meth. A 305 (1991) 527. [15] Y. Chen et al., Optimal use of Charge Information for the HL-LHC Pixel Detector Readout,Nucl. Instrum. Meth. A 902 (2018) 197 [arXiv:1710.02582]. [16] Tracker Group of the CMS collaboration, Comparative evaluation of analogue front-end designs for the CMS Inner Tracker at the High Luminosity LHC,2021 JINST 16 P12014 [arXiv:2105.00070]. [17] L. Damenti, Development of calibration techniques and performance analysis of the CMS Inner Tracker for the High Luminosity phase of LHC, M.Sc. thesis, Università di Firenze, Firenze, Italy (2022) https://cds.cern.ch/record/2893555. [18] L. Gaioni et al., Optimization of the 65-nm CMOS Linear Front-End Circuit for the CMS Pixel Readout at the HL-LHC,IEEE Trans. Nucl. Sci. 68 (2021) 2682. – 65 – 2025 JINST 20 P03024 [19] RD53 collaboration, CMS analog front-end: simulations and measurements,CERN-RD53-PUB-20-002, CERN, Geneva (2020). [20] Xilinx, Aurora 64B/66B Protocol Specification, SP011 (v1.3), 2014, https://docs.xilinx.com/v/u/en-US/aurora_64b66b_protocol_spec_sp011. [21] K. Moustakas et al., A Clock and Data Recovery Circuit for the ALTAS/CMS HL-LHC Pixel Front End Chip in 65 nm CMOS Technology,PoS TWEPP2019 (2020) 046. [22] P. Rymaszewski, Design and characterization of pixel IC electronics and sensors for new pixel detector generations, Ph.D. thesis, Bonn University, Bonn, Germany (2022). [23] L. Zhang et al., The design and test results of A Giga-Bit Cable Receiver (GBCR) for the ATLAS Inner Tracker Pixel Detector,2023 JINST 18 C03005 [arXiv:2301.13399]. [24] ATLAS ITK collaboration, The Opto-electrical conversion system for the data transmission chain of the ATLAS ITk Pixel detector upgrade for the HL-LHC,J. Phys. Conf. Ser. 2374 (2022) 012105. [25] Texas instruments, LM431 Adjustable Precision Zener Shunt Regulator, https://www.ti.com/lit/gpn/LM431. [26] M. Karagounis et al., An integrated Shunt-LDO regulator for serial powered systems, in the proceedings of the European Conference on Solid-State Circuits, Athens, Greece, September 14–18 (2009) [DOI:10.1109/esscirc.2009.5325974]. [27] J. Kampkötter et al., Stabilization and Protection of the Shunt-LDO regulator for the HL-LHC pixel detector upgrades,PoS 370 (2020) 067. [28] G. Traversi et al., A Rad-Hard Bandgap Voltage Reference for High Energy Physics Experiments, in Applications in Electronics Pervading Industry, Environment and Society, Springer International Publishing (2020), p. 19–24 [DOI:10.1007/978-3-030-37277-4_3]. [29] J. Kampkötter et al., Characterization and verification of the Shunt-LDO regulator and its protection circuits for serial powering of the ATLAS and CMS pixel detectors,J. Phys. Conf. Ser. 2374 (2022) 012071. [30] M. Karagounis et al., An integrated Shunt-LDO regulator for serial powered systems, in the proceedings of the European Conference on Solid-State Circuits, Athens, Greece, September 14–18 (2009) [DOI:10.1109/esscirc.2009.5325974]. [31] D.B. Ta et al., Concept, realization and characterization of serially powered pixel modules (Serial Powering),Nucl. Instrum. Meth. A 565 (2006) 113 [physics/0604194]. [32] L. Gonella et al., A serial powering scheme for the ATLAS pixel detector at sLHC,2010 JINST 5C12002. [33] F. Hinterkeuser, Evaluation of a Serial Powering Scheme and its Building Blocks for the ATLAS ITk Pixel Detector, Ph.D. thesis, University of Bonn, Bonn, Germany (2022). [34] CMS collaboration, Characterisation of the first digital modules with RD53B-CMS readout chips for the Phase-2 Upgrade of the CMS Inner Tracker,2023 JINST 18 C01027. [35] A. Pradas et al., RD53A chip susceptibility to electromagnetic conducted noise,PoS 370 (2020) 064. [36] M. Menouni, The RD53 chip monitoring system,CERN-RD53-NOTE-23-001. [37] Y. Zhu et al., Split-SAR ADCs: Improved Linearity With Power and Speed Optimization,IEEE Trans. VLSI Syst. 22 (2014) 372. [38] A.H. Chang, H.-S. Lee and D. Boning, A 12b 50MS/s 2.1mW SAR ADC with redundancy and digital background calibration, in the proceedings of the European Conference on Solid-State Circuits, Bucharest, Romania, September 16–20 (2013) [DOI:10.1109/esscirc.2013.6649084]. – 66 – 2025 JINST 20 P03024 [39] F. Faccio et al., Radiation-Induced Short Channel (RISCE) and Narrow Channel (RINCE) Effects in 65 and 130 nm MOSFETs,IEEE Trans. Nucl. Sci. 62 (2015) 2933. [40] G. Borghello et al., Dose-Rate Sensitivity of 65-nm MOSFETs Exposed to Ultrahigh Doses,IEEE Trans. Nucl. Sci. 65 (2018) 1482. [41] M. Menouni et al., 1-Grad total dose evaluation of 65 nm CMOS technology for the HL-LHC upgrades, 2015 JINST 10 C05009. [42] L.M.J. Casas et al., Characterization of radiation effects in 65 nm digital circuits with the DRAD digital radiation test chip,2017 JINST 12 C02039. [43] RD53 collaboration, DRAD results obtained during irradiation campaigns,CERN-RD53-PUB-20-001, CERN, Geneva (2020). [44] S. Kulis, Single Event Effects mitigation with TMRG tool,2017 JINST 12 C01082. [45] RD53 collaboration, Single event effects on the RD53B pixel chip digital logic and on-chip CDR, 2022 JINST 17 C05001. [46] M. Menouni et al., Single event effects testing of the RD53B chip,J. Phys. Conf. Ser. 2374 (2022) 012084. [47] G. De Robertis et al., Heavy-Ions induced SEE effects measurements for the STRURED ASIC,Nucl. Phys. B Proc. Suppl. 215 (2011) 333. [48] S. Miryala, T. Hemperek and M. Menouni, Characterization of Soft Error Rate Against Memory Elements Spacing and Clock Skew in a Logic with Triple Modular Redundancy in a 65 nm Process, PoS TWEPP2018 (2019) 029. [49] RD53 collaboration, Measurements of the radiation damage to the ITkPixV1 chip in X-ray irradiations, Nucl. Instrum. Meth. A 1039 (2022) 166947. [50] CHIPIX65 and RD53 collaborations, Reusable SystemVerilog-UVM design framework with constrained stimuli modeling for High Energy Physics applications, in the proceedings of the International Symposium on Systems Engineering, Rome, Italy, September 28–30 (2015) [DOI:10.1109/SysEng.2015.7302788]. [51] S. Marconi et al., The RD53 Collaboration’s SystemVerilog-UVM Simulation Framework and its General Applicability to Design of Advanced Pixel Readout Chips,2014 JINST 9P10005 [arXiv:1408.3232]. [52] M. Daas et al., BDAQ53, a versatile pixel detector readout and test system for the ATLAS and CMS HL-LHC upgrades,Nucl. Instrum. Meth. A 986 (2021) 164721 [arXiv:2005.11225]. [53] T. Heim, YARR - A PCIe based readout concept for current and future ATLAS Pixel modules,J. Phys. Conf. Ser. 898 (2017) 032053. [54] ATLAS TDAQ collaboration, FELIX: the Detector Interface for the ATLAS Experiment at CERN, EPJ Web Conf. 251 (2021) 04006. [55] CMS collaboration, The CMS Inner Tracker DAQ system for the High Luminosity upgrade of LHC: From single-chip testing, to large-scale assembly qualification,EPJ Web Conf. 295 (2024) 02028. [56] M.H. Standke, Hybrid Pixel Readout Chip Verification, Characterization and Wafer Level Testing for the ATLAS-ITK Upgrade at the HL-LHC, Ph.D. thesis, University of Bonn, Bonn, Germany (2023). [57] Cocotb open source co-simulation in Python,https://www.cocotb.org/. [58] ATLAS ITk Pixel collaboration, RD53B Wafer Testing for the ATLAS ITk Pixel Detector,J. Phys. Conf. Ser. 2374 (2022) 012087. [59] CMS collaboration, Wafer-level testing of the readout chip of the CMS Inner Tracker for HL-LHC, Nucl. Instrum. Meth. A 1044 (2022) 167496. – 67 –