A 16 [email protected] Mixed-Signal Programmable Fuzzy Controller CMOS-1μm Chip

156 A 16 [email p o ec ed] Mixed-Signal P og ammable Fuzzy Con olle CMOS- ym Chip Fe nando Vidal-Ve du *, Ra ael Na as * and Angel Rod íguez-Vázquez ** *D o. de Elec ónica Uni e sidad de Málaga Complejo Tecnológico, Campus de Tea inos, Málaga, SPAIN FAX: 34 5 2132782; Phone: 34 5 2133326 email: [email p o ec ed] *Dep . o Analog and Mixed-Signal Ci cui Design Ins i u o de Mic oelec ónica de Se illa-Uni e sidad de Se illa Edi icio CICA, C/Ta ia s/n, 41012-Se illa, SPAIN FAX:: 34 5 4231832; Phone:: 34 5 4239923 email: [email p o ec ed] ABSTRACT: We p esen a uzzy in e ence chip capable o e alua e 16 p og am- mable ules a a speed o 2.5M lips (2.5 x IO6 uzzy in e ences pe second) wi h 8.6mW powe consump ion. I occupies 2.89mm2 (including pads) in a CMOS l|im single-poly echnology. Measu emen s .a e gi en o demons a e i s pe o ¬ mance. All he ope a ions needed o uzzy in e ence .a e ealized on-chip using analog ci cui y compa ible wi h s anda d VLSI CMOS echnologies. On-chip dig¬ i al con ol and memo y ci cui y is also inco po a ed o p og ammabili y. The chip a chi ec u e and ci cui y a e based on ou design me hodology o neu o- uzzy sys ems epo ed in [1]. A ew a chi ec u al modi ica ions a e made o sha e ci cui y among ules and, hus, ob ain educed a ea and powe consump ion. The chip pa ame e s can be lea ned in si u, o ope a ion in a changing en i onmen , by using dedica ed ha dwa e-compa ible lea ning algo i hms [1][8]. 1. In oduc ion Fuzzy con olle s employ uzzy logic in e ence o model sys ems whose ma hema ical desc ip ion is unknown, based on insigh s abou local ea u es o hei beha io [2]. These models consis o nonlinea mul idimensional unc ions (called esponse su aces) which map inpu s in o ou pu s. Fo implemen a ion pu poses hese maps a e ep esen ed as expansions o uzzy basis unc ions, one pe each local piece o knowledge om which he global model is buil . These local pieces o knowledge a e exp essed by mean o logic IF-THEN ules, IF xx is An AND x2 is Ai2 AND ... xM is AiM THEN Consequen Ac ion One appealing ea u e o uzzy modeling is ha he s a emen s in hese ules can be o mula ed in na u al language; such as, "i he pole is alling apidly o he le hen he ca mus mo e apidly o he le ", which simpli ies cap u ing human expe ise. Also, he locali y o he pieces o knowledge, he basis on which he global su ace esponse is buil , enables simple model upda ing o changes ha a ec only limi ed egions o he inpu space. Fuzzy echnology has p o en iable o inco po a ion in o new p oduc s wi hin sho de el¬ opmen ime and wi h low de elopmen cos which, oge he wi h i s unc ionali y po en ial, ende i e y well sui ed o build ma ke able in elligen sys ems [3]. In his scena io, dedica ed ha dwa e implemen a ions based on analog pa allel p ocessing ea u e high-speed in e ence, educed powe consump ion and simple in e ace o physical senso s and ac ua o s [2]. 157 The CMOS chip p esen ed he e is based on ou design me hodology o neu o- uzzy ASICs, epo ed in [1]. O he CMOS monoli hic analog uzzy chips ha e been epo ed in [4][5][6][7]. [4] employs swi ched-capaci o ci cui s o ob ain 0.5MFlips. The o he h ee ealize 9 ules@2inpu @ lou pu using con inuous- ime ci cui s. The as es claims lOMFlip® lOmW, and ha e e y limi ed p og ammabili y and no in e nal logic [5]. [6] ob ains O.lMFlip, and gi es no da a abou powe ; [7] ob ains [email p o ec ed], again wi h limi ed p og ammabil¬ i y and no in e nal logic. 2. Chip Desc ip ion: A chi ec u e and Building Blocks The chip ealizes he pa icula case o uzzy in e ence ha uses cons an e ms (single ons) a he consequen o each ule [l].This p ocedu e ob ains y =/(x) as, min {sn (jj), si2(x2),..., s¡M(xM) } y(x) = X "Y* (*)?,*. wi*(x)=- (1) i=l,5 ]T min{sn(kxl),si2(x2),...,siM(xM)} i = .N whe e w,*(x) a e he no malized uzzy basis unc ions which co esponds o no malized ule an eceden ou pu s, Si ixj) a e he membe ship unc ions associa ed o linguis ic labels A p and y¿* a e he single on alues a he consequen o each ule. Fig. 1 is a concep ual a chi ec u e o ealize (1). The e, p ocessing is ealized h ough i e laye s associa ed o he ope a o s in (1) Ins ead o a di ec ansla ion o Fig. 1 in o silicon, ci cui y in he epo ed chip is dis ib¬ u ed o achie e high modula i y. Thus, minimum and no maliza ion ci cui s ha e been spli in o cells, which a e u he g ouped in o wo blocks named label block and ule block in he chip a chi ec u e depic ed in Fig. 2. On he o he hand, membe ship unc ions a e sha ed among di ¬ e en ules. Thus, he e is only one membe ship unc ion o each label in he ule se , and he e is only a se o labels pe inpu . Consequen ly: . Membe ship unc ion ci cui s do no need o be eplica ed a each ule, hus we sa e a ea and powe consump ion. . We can gene a e only g id pa i ions o he uni e se o discou se, ha is, he pa i ion in each sepa a e dimension o inpu de e mine he pa i ion in he o e all mul idimensional inpu space. The e o e, sca e and ee pa i ions [8] a e no allowed. Al hough chip inpu and ou pu signals a e ol ages, much o he in e nal p ocessing is eal¬ ized in cu en mode. Membe ship unc ions a e gene a ed om sigmoid ou pu s o wo c oss- coupled di e en ial pai s, and complemen ed in o de o use a mul iple ou pu maximum ci cui o ealize minimum in (1) h ough maximum plus complemen ope a ions, based on De Mo ¬ gan's law [1]. A he ci cui le el, he sha ing o he membe ship unc ions equi es o eplica e he complemen ed membe ship unc ion ci cui ou pu by mean o a mul iple ou pu cu en mi o . This is shown in Fig.3, which depic s a basic schema ic o he label block, whe e shaded a eas co esponds o he inpu cells o he mul i-inpu maximum ci cui [1]. The inpu o he label block is one o he chip ol age inpu s, and i p o ides ou ol ages as ou pu s. Since i implemen s sha ed membe ship unc ions, he e is one label block o each label in he ule se . The chip con ains eigh label blocks, ou pe inpu . The label blocks ou pu s a e connec ed o inpu s o he ule blocks h ough a ing bus. The e is one ule block o each ule in he knowledge base, six een in ou chip. Besides o illus a ing he inpu space pa i ion achie ed by he chip, Fig. 4 shows he concep ual connec ion be ween bo h building blocks, while Fig. 5 shows he schema ic o a ule block. Two ol age ou pu s 158 om wo di e en label blocks a e connec ed o he inpu o a ule block, whose inpu s age is he ou pu s age o he minimum ci cui . The ou pu o he minimum ci cui d i es he no mal¬ iza ion ci cui uni cell [1]. Besides he uni cells, which sha e nodes Ano and Bno in Fig. 5, he no maliza ion ci cui is comple ed wi h one diode connec ed ansis o a node Anop and one cu en mi o whose ou pu is connec ed o node Bno and eplica es a cons an cu en sou ce . bo h implemen ed in he biasing box o Fig.2. The no maliza ion ci cui ou pu in each ule block is weigh ed by a digi ally p og ammable cu en mi o , hus pe o ming single on weigh ing a he consequen o each ule [1]. Finally, he ou pu o his cu en mi o is con¬ nec ed o he chip global ou pu , whe e agg ega ion a i h laye o Fig. 1 is ealized by KCL. The digi al single on p og amming codes a e s o ed in a shi egis e which is he chip in e ¬ nal memo y elemen - se ially p og ammed h ough wo pads. Apa om he digi al p og am- mabili y o single ons, he wid h and loca ion o membe ship unc ions a e analog- p og ammable by se ing he wo ol ages EjX and Ej2 associa ed o membe ship alue o 0.5 (c osso e poin s) in he membe ship unc ion ci cui ela ed o each label (see Fig. 3). Finally, bias signals a e mainly gene a ed in e nally and sha ed by di e en blocks. They a e imple¬ men ed in he biasing box oge he wi h he sha ed pa s o no maliza ion ci cui . 3. Expe imen al Resul s Fig.6 is a mic opho og aph o he chip; o al a ea is 2.89mm2, and co e a ea is 1.6mm2. The igu es Fig. 7(a) and Fig. 7(b) show wo esponse su aces gene a ed by he chip. Single ons a e se o decimal alues 1 and 15 in Fig. 7(b), whe e he basis unc ions a e clea ly seen. Fig. 7(a) illus a es an exempla y su ace ob ained wi h di e en single on alues. Maximum ci cui delay is 471ns (90% o he ull scale ou pu cu en ) o a s ep inpu , while powe consump ion is 8.6mW and esolu ion is a ound 6.5% o 3a (s anda d de ia ion) e o igu e. Supply ol ¬ age is 5V and he inpu ol age ange is 3.25V As a inal poin , i is wo h men ioning ha we ha e de eloped ha dwa e-compa ible lea n¬ ing algo i hms ha enable he chip o be ained in-si u h ough examples and, hus, compen¬ sa e second-o de ha dwa e non-linea i ies [8]. Thus, highe p ecision can be achie ed by inse ing he chip in a lea ning loop wi h a compu e . Re e ences [1] F. Vidal-Ve du and A. Rod iguez-Vázquez: "CMOS Design o Analog Neu o-Fuzzy Con olle s using Building Blocks" IEEE Mic o, Vol.15, pp. 49-57, Augus 1995. [2] T. Yamakawa: "A Fuzzy In e ence Engine in Nonlinea Analog Mode and I s Applica ion o a Fuzzy Logic Con ol". IEEE T ans, on Neu al Ne wo ks, Vol. 4, pp. 496-522, May 1993. [3] H. Takagi: "Applica ions o Neu al Ne wo ks and Fuzzy Logic o Consume P oduc s", pp. 8-12 in Fuzzy Logic Technologies and Applica ions, New-Yo k: IEEE P ess 1994. [4] J.W. Fa a uso e al.: "A Fuzzy Logic In e ence P ocesso ". IEEE Jou nal o Solid-S a e Ci cui s, Vol. 29, pp. 397-402, Ap il 1994. [5] L. Lemai e e al.: "Analysis and Design o CMOS Fuzzy Logic Con olle in Cu en Mode". IEEE Jou nal o Solid-S a e Ci cui s, Vol. 29, pp. 317-322, Ma ch 1994. [6] T Ke ne e al.: "Realiza ion o a Monoli hic Analog Fuzzy Con olle ". P oc. ESSCIRC93, pp. 66-69, Se ille Sep embe 1993. [7] N. Manna esi e al.: "A Modula Analog A chi ec u e o Fuzzy Con olle s". P oc. ESSCIRC94, pp. 288-291, Ulm Sep embe 1994. [8] F. Vidal-Ve du: CMOS VLSI Design o Neu o-Fuzzy Mixed-Signal ASICs. PhD disse a ion, Uni . Malaga-Spain, 1996. 159 ule block. label block biasing box £j O i Ki y sw Figu e 1 membe ship unc ion ci cui complemen Figu e 2 a- lB .-U-C" UlU3UlS VUA. 'ip- lop ¥ Lji F8T gS y egis e ?4 . 'W lWWW *2 D2. c2: b2: ^G/l ^G;7 ^0/3 ^Gj4 ^ ing bus ule blocks I. - J Figu e 3 maximum ci cui uni cell Figu e 4 no pializa ion ci cui uni cell -*-:-? , «** s o *.! sa Sa y, minimum ci cui ou pu s age single on weigh ing ci cui ¿T* FÍgU cS Figu ed '*.m iï à)&)!Êa k jc2, ol s X , ol s 3 Figu e 7(a) x2, ol s X , ol s Figu e 7(b) 4 5