An Alternative DfT Methodology to Test High-Resolution ΣΔ Modulators
Abstract
In this paper, a novel DfT methodology to test high-resolution ΣΔ Modulators (ΣΔM) is introduced. The aim of the proposal is to reduce the test time required by conventional methodologies without degrading the accuracy of the results. A detailed description of the additional circuitry needed to perform these tests is presented as well as some initial simulation results to show the utility of the approach.
Full text
AN ALTERNATIVE DFT METHODOLOGY TO TEST HIGH-RESOLUTION
6' MODULATORS
S. Escale a, J. M. Ga cía-González, O. Gue a, J. M. de la Rosa, F. Medei o, B. Pé ez-Ve dú and A.
Rod íguez-Vázquez,
(escale a, jmga cia, gue a, j osa, medei o, belen, [email p o ec ed])
Ins i u o de Mic oelec ónica de Se illa (IMSE-CNM-CSIC)
A . Reina Me cedes, 41012-Se illa, SPAIN. Tl no.: 955056666 Fax:955056686
Abs ac
In his pape , a no el D T me hodology o es high- esolu ion
6' Modula o s (6'M) is in oduced. The aim o he p oposal is
o educe he es ime equi ed by con en ional me hodologies
wi hou deg ading he accu acy o he esul s. A de ailed desc ip-
ion o he addi ional ci cui y needed o pe o m hese es s is
p esen ed as well as some ini ial simula ion esul s o show he
u ili y o he app oach.
1.In oduc ion
Al hough much e o has been paid in las yea s o ind a p ac-
ical es me hodology o A/D and D/A con e e s, a he e y
end, i has become a common p ac ice o use s anda d FFT ech-
niques o he dynamic es and his og am-based app oaches o
s a ic es o modula o s [1]. Un o una ely, bo h al e na i es e-
qui e a huge amoun o da a when he esolu ion o he Ci cui s
Unde Tes (CUTs) is beyond 15 bi s. This esul s in a ade-o
among es ime and measu emen esolu ion ha imposes s ong
limi a ions o he es se -up. To alle ia e his p oblem, a new
me hodology, based on a di ide-and-conque app oach is in o-
duced in his pape , paying special a en ion o he p ac ical ci -
cui implemen a ion.
Al hough a decomposi ion o he CUT in o analog and digi al
subsys ems is, a leas a-p io y, easy o pe o m, u he decom-
posi ion wi hin he analog pa is no so di ec . Howe e , a basic
se o ules can be gi en:
• Pe o m he pa i ioning aking in o accoun he speci ica-
ions (i some speci ica ions can be p opaga ed o speci ic
subsys ems, hei con ol can be pe o med by only check-
ing he unc ionali y o hose subsys ems).
• Pe o m he pa i ioning in subsys ems ha a e unc ionally
independen o hei en i onmen .
• Check ha subsys ems ha e non-o e lapping unc ionali y.
• Decompose he sys em in o subsys ems ha can be es ed by
well-known echniques.
• Ca y ou he decomposi ion so ha sys em speci ica ions
can be easily mapped in o subsys em speci ica ions.
• Ca y ou he decomposi ion in a way ha es ing he sub-
sys ems ake less ime han es ing he whole sys em.
This se o ules jus i ies ha analog mac os based on a unc ion-
al decomposi ion a e na u al candida es o es pa i ioning.
Fo 6' A/D con e e s, an ob ious decomposi ion is spli ing
he sys em in o he analog modula o and he digi al decima ion
il e . Howe e , his le el o g anula i y is no enough when es
applica ion ime is a c i ical issue. Tes ing modula o s is a ime-
consuming ask and should be desi able a ine decomposi ion o
he modula o .
2.Re e ence es ci cui and es me hods
The me hodology p oposed in his pape is based on he idea ha
a p ope decomposi ion o he modula o in o se e al blocks can
be used o educe he ime in ol ed in he es o he whole s uc-
u e. I is expec ed ha an adequa e es o he c i ical blocks in
he modula o should educe d ama ically bo h he es ime and
he es complexi y, o e ing also he possibili y o de ec he
sou ces o e o s ha a ec he ci cui pe o mance, hus, p o-
iding he ways o co ec hese aul s.
Wo king ou di e en decomposi ion schemes will also equi e
o combine wi h ano he ideas, o ins ance wi h he use o Sw-
Opamps o any o he mul iplexing scheme.
To de e mine he quali y o he p oposed es app oaches, a sen-
so -in e ace 6'M will be used as he ci cui e e ence. The ci -
cui has been implemen ed ollowing a cascade 2-1 a chi ec u e
as shown in Fig. 1, unde he speci ica ions desc ibed below:
• Resolu ion: DR = 17bi s, SNRpeak > 100dB
• Digi al ou pu a e: 40kSample/s
• Signal bandwid h= Bw = (0.1Hz-20kHz)
• Tempe a u e ange: om -40oC o 175oC
• Minimum powe consump ion
Acco ding o he se o ules gi en abo e a numbe o c i ical
blocks can be iden i ied:
• Fi s , om all he in eg a o s, domina ing e o sou ces a ise
mainly due o he i s one. The e o e, an exhaus i e es o
con ol he i s in eg a o quali y will be o g ea in e es .
• Second, al hough he quan ise non-ideali ies a e a enua ed
by he gain o he in eg a o s, a es o check he pe o m-
ance o his block will enable he de ec ion o aul s du ing
he ab ica ion o he modula o .
• Thi d, he las block o be es ed should be he DAC. This
es is specially c i ical o mul i-bi quan ise s. Howe e ,
his is no he case he e, so his es should no be u he
conside ed.
Taking in o accoun hese esul s, h ee es p oposal should be
Figu e 1. Block diag am o a 2-1 cascade 6' Modula o .
i
DAC
DAC
CANCELLATION LOGIC
ou
oi1
g
1
g
,1
g
2
g
,2
g
3
g
,,3
g
,3
,;,((( ,6&$6
de ined and a e desc ibed now on.
2.1. Tes o he i s in eg a o
A me hodology o de ec he sou ce o e o s ha deg ade he ci -
cui pe o mance due o e o s in he i s in eg a o could be he
ollowing:
• Fi s , he i s in eg a o is con e ed in o an ampli ie .
• Second, he wo emaining in eg a o s a e connec ed o o m
a second o de 6'M.
• Thi d, he inpu signal is connec ed o he inpu o he i s
in eg a o (now ampli ie ) and, a e a delay, connec ed o he
nega i e inpu o he second o de 6'M. Thus, he second
o de 6'M will p ocess he e o signal gene a ed by he non-
ideal pe o mance o he i s in eg a o .
These s eps a e illus a ed in Fig. 2.
Th ee di e en sou ces o e o s can be de ec ed using his a chi-
ec u e:
•DC gain e o s: using a pulse-coded inpu wi h e y low e-
quency o elimina e he in luence o he se ling e o , he
e o signal de ec ed a node oi1 will include in o ma ion
abou he ini e gain o he ampli ie .
I he In-Band-Noise (IBN) powe is measu ed o he 2nd
o de modula o and he il e only, his IBN a he ou pu o
he econ igu ed modula o can be compa ed o he one
ob ained when he ampli ie is included in he ci cui . This
compa ison enables he possibili y o gene a e a signa u e o
decide i he DC gain e o o he i s ampli ie is o no
wi hin he ole ance limi s.
•Se ling e o : wi h he same s uc u e, now inc easing he
equency o he inpu signal, i is possible o ca e o he
e o in oduced by he se ling o he ampli ie . Again, a
measu e o he IBN wi h and wi hou he inpu ampli ie
allows o gene a e a signa u e wi h an ambigui y se o wo
elemen s (DC gain e o and se ling o he i s ampli ie ).
The in luence o he DC gain and se ling e o s has been simula -
ed using ASIDES [2], and p elimina y esul s a e shown in Fig.
3(a).
•The mal noise: i he inpu signal is a sine wa e wi h small
ampli ude and low equency, by dec easing he equency
sampling o he in eg a ion capaci o i is possible o inc ease
he con ibu ion o he he mal noise signi ican ly, hus ena-
bling i s di ec measu emen a he ou pu node. The ini ial
esul s o his simula ion a e also shown in Fig. 3(b).
2.2. Tes o he quan ise
In he case o a single bi , he quan ise block is educed o a com-
pa a o . This kind o ci cui s has e o s domina ed by hei inpu
o se and hys e esis. Howe e , due o he loca ion in o he modu-
la o opology, hese e o sou ces a e la gely a enua ed by he
DC gain o he in eg a o s. In spi e o his, o enable he isola ed
es o he i s in eg a o i is impo an o check ha he quan isa-
ion e o is accu a ely bounded. To his end, accessible nodes
ha e o become a ailable in he ci cui , ollowing he app oach in
Fig. 4. Then, i he modula o inpu is se o ze o and a es signal
(sine-wa e s imulus) is applied, his will esul in an ou pu whe e
he quan isa ion noise can be obse ed by pe o ming an FFT
analysis wi h a educed se o samples. To make accessible his
node, he applica ion o he Sw-Opamp concep desc ibed in he
nex sec ion will be o g ea in e es . An example o he esul ing
es is gi en in Fig. 5 o 16384 samples om he bi s eam.
2.3. Signal pa h deg ada ion
An al e na i e o he me hodology desc ibed be o e, is ela ed o
allow he obse abili y o some c i ical nodes o de ec he co ec
ope a ion o he modula o . Fo he case unde s udy, he c i ical
nodes a e loca ed a he ou pu o each in eg a o . I a bu e is
added o hese nodes and an addi ional inpu is added o he ci cui
o make i swi ch be ween es and no mal ope a ion mode, he
signals a hose nodes can be obse ed. This al e na i e is illus a -
ed in Fig. 6.
3.Building blocks o D T
As in oduced in Sec ion 2, some ci cui y has o be added o he
Figu e 2. Tes ing he pe o mance o he i s in eg a o .
i
DAC
DAC
oi1
Y1Y1
ou
delay
SC-ampli ie
con igu a ion
2nd-o de
6'
Modula o
Unused
blocks
T
in
= nT
s
i
g1
g,1g2
g,2
g3
g,,3
g,3
0 2000 4000 6000 8000 10000
F equency (Hz)
-175
-150
-125
-100
-75
-50
-25
0
PSD x eq. bin (dB)
DCgain=100
DCgain=500
DCgain=1000
DCgain=2500
Figu e 3. DC gain e o s and noise o he i s in eg a o .
1e+02 1e+03 1e+04 1e+05
F equency (Hz)
-175
-150
-125
-100
-75
-50
-25
PSD x eq. bin (dB)
0
1s -in eg a o
ci cui noise
measu emen
(a)
(b)
Figu e 4. Tes signal injec ion in o he Quan ise .
i
DAC
oi1
+
es signal
ou pu
g1g2
g,1g,2
,
modula o i sel in o de o allow he di e en es me hodologies.
The mos c i ical ci cui s a e hose ha a ec in some way o he
signal pa h. Thus, he ou pu bu e s o con ol he p opaga ion and
deg ada ion o he signal h ough he in eg a o s and he Sw-
Opamps wi hin each in eg a o ha e been ca e ully designed o
minimize he deg ada ion o he no mal ope a ion.
3.1. Analog ou pu bu e s
The in e nal a chi ec u e o a bu e able o cope wi h he low-deg-
ada ion equi emen s is shown in Fig. 7.
The speci ica ions achie ed by his bu e a e:
• DC Gain: -0.03 dB
• -3dB: 30.9 MHz (wi h 10 pF ou pu load)
• Powe : 0.68 mW
I is impo an o poin ou ha his kind o blocks can be used as
pa ame isable lib a y cells o be added o he ci cui which is de-
si ed o es .
3.2. Sw-Opamps
The idea he e [3],[4], is o sepa a e he link be ween he analogue
blocks and he es s imuli by changing he ope a ional ampli ie s
used o in eg a ion pu poses by Sw-Opamps, whe e wo di e en
inpu s ages, con olled by a digi al signal, allow ha he ampli ie
wo ks in no mal o in es mode.
A way o ca y all his ask in an e icien , ye simple manne , is o
use Sw-Opamps. They essen ially consis o ope a ional ampli i-
e s in which he di e en ial inpu pai has been duplica ed, hus
p o iding wo ope a ional modes, commanded by a digi al con ol
signal:
•No mal Mode: he ci cui ope a es as an opamp, wi h a
di e en ial inpu and a single-ended (o di e en ial i
equi ed) ou pu .
•Bu e Mode: he ci cui ac s as a bu e , whe e he signal
p esen a an ex a e minal is passed o he ou pu , isola ing
in his mode he egula inpu signal.
This is illus a ed in Fig. 8.
To enable his modi ica ion, he di e en ial inpu pai o he am-
pli ie has o be duplica ed and connec ed o he emaining ci cui -
y by means o swi ches ha con ols he ope a ion mode. Then, a
digi al con ol decides i he ope a ion o he ampli ie is es mode
o no mal mode.
Al hough his ope a ion can be pe o med by simply inse ing he
swi ches as shown in Fig. 9, his al e na i e will esul in a signi -
ican deg ada ion o he ci cui pe o mance due o he pa asi ic e-
sis ance caused by S1,S2 in he signal pa h.
The key poin he e is o design an Sw-Opamp ha minimizes he
impac on he ci cui pe o mance, powe dissipa ion and a ea
consump ion by inse ing he swi ches in app op ia e places.
In Fig. 10 wo al e na i es a e shown, as in oduced in [5]. The
i s one equi es eigh swi ches ex e nal o he ampli ie , while he
second one equi es ou in e nal swi ches. In bo h cases he in-
c ease o a ea is e y small. Also, he powe consump ion should
no be inc eased since he wo ope a ion modes in ol e he same
s uc u e.
Th ee HSPICE simula ions ha e been done o compa e he o igi-
nal beha iou (ampli ie wi hou a Sw-concep ) wi h he al e na-
i es p oposed in Fig. 10.
The esul s o his compa ison is summa ized in Table 1 o he
olded-cascode opamp in Fig. 10, whe e he i s ow co esponds
Figu e 5. Noise ans e unc ion e alua ion.
Bu e
MUX
Bu e
Bu e
Figu e 6. Using bu e s o access o in e nal nodes.
i
DAC
DAC
CANCELLATION LOGIC
ou
g
1
g
,1
g
2
g
,2
g
3
g
,,3
g
,3
M
1
M
2
M
3
M
4
M
5
M
7
M
8
I
b
in
o
M
6
C
c
Figu e 7. Analog bu e p oposed o es objec i es.
op
on
-
+
ip
p
in
n
Digi al con ol p, n: es da a inpu
ip, in: no mal da a inpu
Figu e 8. Basic in eg a o and SW-Opamp concep .
op
on
-
+
ip
in
-
+
ip
oi
1
p
oi
1
n
in
es
es
es
es
S
1
S
2
S
3
S
4
Figu e 9. Inse ion o swi ches.
,
o he o iginal beha iou (Re ), he second o he al e na i e using
in e nal swi ches (in-sw) and he hi d one o he al e na i e based
on inse ing ex e nal swi ches (ex-sw).
I can be seen om he simula ions how he o iginal beha iou is
e y sligh ly a ied by he inclusion o he addi ional ci cui y.
The inal implemen a ion o he i s ampli ie including he Sw-
Opamp concep is shown in Fig. 11.
Also, in Table 2, he simula ion esul s including in o ma ion
abou he compa ison o he wo s -case beha iou in all he co -
ne s es ed o he ope a ional ampli ie s, a e shown.
Finally, he ope a ion o he ci cui in bu e mode has been es ed
o ensu e ha he esolu ion is enough o p opaga e he s imulus
signal wi hou a ec ing he es esul s. The ou come o his es is
shown below:
• Fi s Sw-ampli ie HD3 = -104.81 dB (17.47 bi s)1
• Second Sw-ampli ie HD3 = -101.67 dB (16.95 bi s)
4.Layou
The layou o he p o o ype including he D T ci cui y is shown
in Fig. 12. The D T ci cui y is highligh ed in he Figu e, showing
ha he a ea o e head is small as compa ed wi h he o al a ea o
he p o o ype. This p o o ype has been sen o ab ica ion and i is
expec ed ha , in some weeks, p ac ical expe imen al esul s will
be ob ained.
5.Conclusions
In his pape , se e al al e na i es o he D T o high- esolu ion 6'
modula o s ha depa om he usual echniques a e in oduced.
Ci cui de ails a e gi en on how o implemen he di e en me h-
odologies p oposed and p elimina y simula ion esul s a e shown
while inal expe imen al esul s a e gene a ed.
Re e ences
[1] IEEE S anda d 1241-2000, IEEE S anda d o e minology
and es me hods o analog- o-digi al con e e s, 2001.
[2] F. Medei o, B. Pé ez-Ve dú, A. Rod íguez-Vázquez and J.
L. Hue as, “A Ve ically In eg a ed Tool o Au oma ed
Design o 6' Modula o s”, IEEE J. Solid-S a e Ci cui s,
Vol. 30, No. 7, pp. 762-772, July 1995.
[3] A. H. B a , R. J. Ha ey, A. P. Do ey and A. M. D. Rich-
a dson, “Design- o -Tes s uc u e o acili a e es ec o
applica ion wi h low pe o mance loss in non- es mode”,
IEE Elec onics Le e s, Vol. 29, No. 16, pp. 1438-1440,
Augus 1993.
[4] D. Vázquez, A. Rueda and J. L. Hue as, “Fully Di e en ial
Sw-Opamp o Tes ing Analog Embedded Modules”, P oc.
IEEE In e na ional Mixed Signal Tes Wo kshop,
IMSTW96, 15-18 May, Quebec (Canada), pp. 204-209,
1996.
[5] G. N. S enbakken, T. M. Soude s and G. W. S ewa , “Am-
bigui y g oups and es abili y”, IEEE T ans. on Ins umen-
a ion and Measu emen , Vol. 38, No. 5, pp. 941-947, Oc o-
be 1989.
Table 1. Deg ada ion caused by he sw-concep .
A0
(dB)
GB
(MHz)
PM
(deg)
SR
(V/Ps)
A ea
(Pm2)
Powe
(mW)
Re 72.62 22.67 86.98 21.71 50.86 7.95
in-sw 72.61 22.59 84.49 21.71 51.6 7.96
ex-sw 72.54 22.52 86.43 21.71 51.6 7.94
Table 2. Wo s case ope a ions o i s and second ( hi d) ampli-
ie s wi h and wi hou Sw-Opamp a chi ec u es.
WC (1s )
WC
(1s SW-OP) WC (2nd)
WC
(2nd SW-OP)
a0 (dB) 71.09 69.93 65.13 64.51
gb (MHz) 13.99 13.73 21.08 20.55
PM (º) 85.50 83.33 82.61 76.45
SR (V/Ps) 21.10 20.21 30.23 29.90
os (V) 5.02 5.01 4.99 4.99
powe (mW) 7.24 7.78 2.48 3.06
M
1
M
2
M
3
M
4
M
5
M
6
M
7
M
8
M
9
M
10
M
11
I
b
- +
o
+
o
-
M
12
M
13
M
15
M
14
M
16
M
17
AB
Load
I
A
=I I
A
=I/2
Load
Ou pu
Ou pu
I
B
=I I
B
=I/2
Figu e 10. Folded-cascode opamp and possible sw-
opamp al e na i es.
Ou pu
Load
M
1
M
2
M
3
M
4
M
5
M
6
M
7
M
8
M
9
M
10
M
11
I
b
- +
o
+
o
-
M
12
M
13
M
15
M
14
M
16
M
17
AB
M
1
M
2
M
5
+
M
1
M
2
M
5
-
Figu e 11. Sw-Opamp inal a chi ec u e. 1. HD3 is he mos dominan dis o ion e m due o he di e -
en ial a chi ec u e chosen o he ampli ie s.
Figu e 12. Layou o he 6'M including D T ci cui y.
Bu e
P og. D T
Delay o
Selec ion o
Addi ional
es mode
Swi ches
1s ampli ie
,