Highly Linear 2,5-V CMOS ΣΔ Modulator for ADSL+

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 51, NO. 1, JANUARY 2004 47 Highly Linear 2.5-V CMOS 61 Modulator for ADSL + Rocío del Río, José M. de la Rosa, Belén Pérez-Verdú, Manuel Delgado-Restituto, Rafael Domínguez-Castro, Fernando Medeiro, and Angel Rodríguez-Vázquez, Fellow, IEEE Abstract—We present a 90-dB spurious-free dynamic range sigma–delta modulator (61 M) for asymmetric digital subscriber line applications (both ADSL and ADSL + ), with up to a 4.4-MS/s digital output rate. It uses a cascade (MASH) multibit architecture and has been implemented in a 2.5-V supply, 0.25m CMOS process with metal–insulator–metal capacitors. The prototypes feature 78-dB dynamic range (DR) in the 30-kHz to 2.2-MHz band ( ADSL +) and 85-dB DR in the 30-kHz to 1.1-MHz band (ADSL). Integral and differential nonlinearity are within 0.85 and 0.80 LSB 14 b, respectively. The 61 modulator and its auxiliary blocks (clock phase and reference voltage generators, and I/O buffers) dissipate 65.8 mW. Only 55 mW are dissipated in the 61 modulator. Index Terms—Analog-to-digital converter (ADC), asymmetric digital subscriber line (ADSL), MASH, sigma–delta modulation, switched-capacitor circuits. I. INTRODUCTION SUPPORTED by a considerable commercial success, wireline solutions for broad-band access and home networking are evolving to provide ever increasing data rates and more functionality. An asymmetric digital subscriber line (ADSL) is an example of such applications and extensions of it like ADSL (with doubled number of channels) or very-high-data-rate digital subscriber line (VDSL), providing video-rate reception) are just round the corner. As this trend goes on, the demand for highly linear, fast analog front-ends challenges mixed-signal designers to achieve accuracies of 12–15 b for signal bandwidths ranging from 1.1 to 12 MHz [1]. Although these specifications seem a priori better suited for Nyquist architectures, such as pipeline analog-to-digital converters (ADCs) [2], these architectures do not exhibit enough linearity for some telecom applications, especially in low-voltage implementations, unless the power consumption is significantly increased. For this reason, oversampled ADCs have gained ground in this frequency range. Specifically, sigma–delta modulators Ms [3], [4] exhibit high intrinsic linearity, making use of relatively simple analog circuitry, which render them worth exploring for broad-band wireline and baseband radio-frequency communications [5]–[22]. Manuscript received January 14, 2003; revised August 31, 2003. This work was supported by the European Union under IST Project 29261/MIXMODEST and IST Project 2001-34283/TAMES-2 and the Spanish MCyT and the ERDF under Project TIC2001-0929/ADAVERE. This paper was recommended by Guest Editor O. Feely. The authors are with the Institute of Microelectronics of Seville (IMSE-CNM, CSIC), 41012 Seville, Spain (e-mail: [email protected]). Digital Object Identifier 10.1109/TCSI.2003.821308 Given the high signal bandwidths required in wireline communication, only low-oversampling ratio Ms are feasible. In order to keep the resolution levels with these low values of , the well-known formulas for the dynamic range DR and the effective number of bits ENOB [3] DR ENOB DR (1) dictate that either high-order loop filtering (increasing the order ) or multibit quantization (increasing the resolution of the quantizer ), or both must be used. However, these strategies raise issues that jeopardize robustness of highly oversampled, low-order single-bit Ms. On the one hand, high-order loops are prone to instability and the stabilization methods proposed have resulted in complex architectures whose DR is degraded with respect to that in (1) [3].This degradation is more notorious for single-bit quantizers, so that the combination of high-order loops with single-bit quantization is not a good choice for high-frequency designs [3]. On the other hand, multibit conversion entails extreme sensitivity to the nonlinearity of the digital-to-analog converter (DAC) in the feedback path and forces the use of correction/calibration techniques [23]–[25]. Unfortunately, since DACs cannot be efficiently linearized within an arbitrarily large resolution, the use of low-order multibit modulation may not be enough to obtain a given DR. A direct solution to this problem is to increase both the modulator order and the internal quantizer resolution, giving rise to moderate-order (3–5), multibit architectures. In fact, the use of multibit quantization (typically up to 4 b) in single-loop highorder Ms inherently improves their stability [3], so that these are good candidates to obtain high-resolution, high-frequency operation, provided that the nonlinearity problem is solved [8], [9], [13], [21]. With the same objective, the combination of highorder cascade (MASH) architectures [26] with multibit quantization has been proposed [18], [27]. These modulators gather the unconditional stability of cascade modulators (only secondand/or first-order stages are used) and the advantages of multibit quantization with relaxed requirements for the linearity of the DAC. The feasibility and efficiency of this approach, because it needs no correction/calibration mechanisms, has already been proven [10]–[12], [17]–[20]. In this paper, we present the design of a M for ADSL applications in a 2.5-V, 0.25m CMOS process. With this 1057-7122/04$20.00 © 2004 IEEE 48 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 51, NO. 1, JANUARY 2004 Fig. 1. L th-order 61 modulator using a 2 0 1 cascade. goal, a family of M architectures capable of achieving high resolution with a low oversampling ratio are devised in Section II. Section III studies the impact of deep-submicrometer features on the architecture selection, providing optimized architecture parameters for the specifications considered. Circuit implementation and related design considerations are explained in Sections IV–VI. Finally, Section VII shows experimental results of the M and compares its performance with state-of-the-art designs. II. LOW-OVERSAMPLING CASCADE MODULATORS Fig. 1 shows the generic block diagram of a family of high-order cascades. It is an th-order modulator formed by a second-order stage followed by identical first-order stages M . The values of the integrator weights are (2) As in all cascade Ms [26], the outputs of the stages are processed in the digital domain through simple operators and combined to cancel out the quantization noise generated in each stage but the last one. Additionally, a pseudomultibit operation [18], [27] is achieved by including multibit quantization only in the last stage, while the remaining are single bit. Linearized -domain analysis shows that the modulator output can be expressed as follows [4]: (3) where stands for the input signal, which is simply delayed, is the last-stage quantization error, which is shaped by an th -order function, and represents the nonlinearity error of the last-stage DAC. Note that, since is generated in a -bit quantizer, the modulator response equals that of an ideal th-order -bit M, except for the factor 2. The aim of this factor, that equals ,isto Fig. 2. SNDR versus input level for several modulator orders. compensate for the signal scaling required to avoid premature overloading of the modulator. By integrating the error terms in (3) over the signal band, the in-band quantization error power is obtained [4] as (4) where (5) are the total power associated with the last-stage quantization error and the DAC nonlinearity error, respectively, with INL being the DAC integral nonlinearity relative to the input full scale . Since the factor 2 in (3) quadruples the in-band power of these errors, a 1-b systematic loss of resolution is generated. However, this loss is small when compared to other cascade Ms and, more importantly, it is constant, regardless of the number of stages. In fact, the most appealing feature of this architecture (with the set of coefficients proposed) is that it can be easily set to any order just by changing the number of identical first-order stages. As shown in Fig. 2, a correct operation is maintained with constant overloading point, regardless of the overall order. The coefficients in (2) also have the following interesting properties. 1) The output swing required in all integrators is only the quantizer full-scale. 2) By proper sharing of the switched-capacitor (SC) input stages, they can be implemented with just two-branch integrators, which minimizes the number of unitary capacitors. 3) All first-order stages, but the last one in case of using multibit quantization, contain the same coefficients, so that they can be electrically identical. This considerably simplifies the electrical and physical implementation of the modulator. A. Nonideal Performance SC implementations of cascade modulators suffer from certain nonideal behaviors more than their single-loop counterparts, namely: finite (and nonlinear) amplifier dc gain and ca- DEL RIO et al.: HIGHLY LINEAR 2.5-V CMOS MODULATOR FOR ADSL 49 (a) (b) Fig. 3. Effect of (a) finite dc gain and (b) weight mismatch on the SNDR of single-bit 2 0 161 Ms for M =16 . pacitor mismatch [4]. Both nonidealities modify the ideal integrator -domain transfer function, thus altering the quantization error transfer function. Since this variation is not correlated to changes of the cancellation logic, mismatch appears between the analog and digital processing that precludes perfect cancellation of the low-order quantization error. Into first-order approximation, the in-band power of the error leakages is independent of , because they are generated in the modulator first stage, which is the same for whatever [4] (6) where stands for the first-stage amplifier dc gain, and is the capacitor ratio standard deviation. If we compare (4) and (6) for a given , it is clear that for certain values of , , and these effects may dominate the in-band error power, thus imposing an upper bound to the practical values of . In order to estimate this limit under realistic circuit imperfections, Fig. 3(a) shows the simulated half-scale SNDR as a function of the amplifier dc gain for . Fig. 3(b) shows the SNDR histograms obtained from Monte Carlo simulation assuming 0.1% sigma in capacitor ratios—0.05% is currently featured by metal–insulator–metal (M-i-M) capacitors in CMOS processes. Under these conditions, mainly because of the matching sensitivity, the seventh-order architecture seems not worth implementing for . Nevertheless, the sixth-order modulator provides a 90-dB worst-case SNDR with dc gain of 2500. Especially robust is the fifth-order cascade requiring a dc gain of 1000 to achieve 80-dB worst-case SNDR with . It is important to remark that these gains are basically needed for the first-stage amplifiers. The dc-gain requirement for the integrators in the remaining stages Fig. 4. ENOB versus last-quantizer resolution for a 2 0 1 61 M in the presence of circuit imperfections. of the cascade are much more relaxed. This is also applicable to other circuit imperfections such as electronic noise, finite dynamics, nonlinearity, and mismatch. This practice allows us to use simpler circuit topologies and layouts for these stages, thus saving area and power consumption. Likewise, in practice, the number of bits in the last-stage quantizer cannot be arbitrarily large. As shown in Fig. 4, for a given , the evolution of the overall effective resolution with tends to saturate due to the presence of leakage. Nevertheless, depending on the signal bandwidth, the reduction in oversampling ratio that can be achieved by resorting to multibit quantization may define the border between feasible and infeasible implementations. As we will show further on, proper selection of the three main design parameters ( , , and )is the key to really efficient implementations. III. DEEP-SUBMICROMETER DESIGN CONSIDERATIONS Viability of cascade multibit Ms in deep-submicrometer CMOS is related to two main process features: supply voltage and capacitor performance. The supply voltage, through the selection of the reference voltages, defines the available dynamic range, but also makes an impact on the selection of the amplifier topology and its capability to trade open-loop dc gain, speed, and output swing [28]. An empirical upper bound for a feasible is given by references are (7) where is the saturation voltage of the amplifier output devices and is the number of transistors in the output branch, which again depends on the specific amplifier topology. If a single-stage amplifier is used, cascode devices will be required to achieve enough dc gain, so that . This common choice is not adequate in low-voltage implementations, where an excessive value of will result in a ridiculously small value for . Among the alternatives, we count on two-stage amplifiers [28], whose output branch can contain only two transistors still producing a large open-loop dc gain. This allows us to increase the value of up to useful levels at the price of an increased power dissipation. Apart from the amplifiers, the performance of the switches with supply voltages below 2.5 V needs careful control, especially for dynamic distortion considerations [29]. For broad-band Ms, solutions are in the clock-boosting strategies [30] or in the employment of 50 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 51, NO. 1, JANUARY 2004 Fig. 5. Most efficient cascade 61 M for each region of the resolution-speed plane. high-voltage devices available in double-oxide processes, with the subsequent increase in price, circuit complexity, and power dissipation. The second most relevant technology feature has to do with the quality of the capacitor structures. According to the results shown in Section II, typical capacitor matching requirements range from 0.1% to 0.2% standard deviation. Low parasitics are also of extreme importance for an efficient implementation of a high-frequency modulator, and finally, we have the capacitor linearity requirements, which are less demanding provided that symmetrical fully-differential circuitry is used. Fortunately, M-i-M capacitors are now available in CMOS processes. They exhibit an excellent matching and linearity, with very small bottom parasitics. In order to quantitatively evaluate previous assumptions, we have developed an analytical procedure to estimate the power consumption of different cascade single-bit and/or multibit Ms. In the underlying expressions, detailed in the Appendix, both architecture and technological features are contemplated, together with simplifying assumptions inspired in practical design solutions. The aim here is not only to draw conclusions about architectural choices, but also to track their evolution under technology changes. To this end, the following figure-of-merit (FOM) has been used [31]: FOM Power DOR (8) where DOR stands for the digital output rate, i.e., the Nyquist rate. In a first comparison step, the triads describing specific cascades have been evaluated along the curve in the resolution-speed plane shown in Fig. 5 (dashed line). Although this particular resolution-speed relationship is arbitrary, it fits the usual requirements for wireline telecom ADCs: integrated services digital network (ISDN), ADSL, VDSL, etc., which have been placed in the figure for illustration. For each section of the resolution-speed curve, the architecture with the minimum FOM has been noted. Observe that, as the output rate increases, the oversampling ratio decreases and, simultaneously, the increased number of bits in the multibit quantizer shows up to compensate for the oversampling reduction. Note that the 4.4-MS/s DOR employed in ADSL falls into the Fig. 6. Estimated evolution of the FOM with technology scaling for three cascade architectures obtaining 14 [email protected] MS/s. region led by the architecture , i.e., a fourth-order 2–1-1 cascade with 3-b quantization in the last stage and using a 16 oversampling ratio, which will be our choice. In a second step, we take advantage of the fact that some technology features enter the above formulation to predict how the performance of the cascade Ms is going to evolve under technology changes. Fig. 6 shows the estimated evolution of the FOM of three cascade topologies, namely , , and , aimed at obtaining 14 b at 4.4 MS/s. These are typical specifications for ADSL modems. Two facts are noticeable. •Despite the reduction of the supply voltage, overall, the power dissipation does not decrease below 0.18 m. This is basically due to the reduction in supply voltages, which imposes a reduction in the reference voltage and, hence, a compensating increase in the sampling capacitors. Since the incomplete settling error power must be also kept constant, this mechanism leads to an increased current absorption, which makes the overall power consumption increase below 0.18 m. The location of the inflection point depends on the converter specifications. For instance, if for the same speed, the resolution is to be increased, the inflection point moves to the right in Fig. 6. •Another aspect illustrated in Fig. 6 is the dynamic nature of the architecture selection in Fig. 5. Note that the M outperforms for 0.25 m and above, but it does not below 0.18 m. IV. SC IMPLEMENTATION Fig. 7 shows the fully differential SC schematic of the M. The first stage of the cascade includes two integrators—with one and two input branches, respectively—and switches controlled by the comparator outputs to feed the quantized signal back. The second stage uses an integrator with only two input branches to implement weights , , and , since the values in (2) allow distribution of between the two branches. The same applies for in the third stage. The third-stage integrator drives the 3-b ADC and the loop is closed by a 3-b DAC. The 1-of-8 output code of the ADC is converted DEL RIO et al.: HIGHLY LINEAR 2.5-V CMOS MODULATOR FOR ADSL 51 Fig. 7. SC implementation of the 2 0 1 multibit 61 modulator. into binary by a read-only memory (ROM) that generates the corresponding bitstreams. The modulator operation is controlled by two nonoverlapped clock phases. The integrator input signals are sampled during phase . During phase , the algebraic operations are performed and results are accumulated in the feedback capacitors. In order to attenuate the signal-dependent clock-feedthrough, delayed versions of the two phases ( and ) are also provided. This delay is incorporated only to the falling edges of the signals (switches turn off), while the rising edges are synchronized in order to increase the effective time-slot for the modulator operations [15]. The comparators and the last-stage ADC are activated at the end of —using as strobe—to avoid any possible interference due to the transient response of the integrators at the beginning of sampling. V. SPECIFICATIONS FOR THE BUILDING BLOCKS The converter specifications have been mapped onto basic building block requirements by following an optimization process supported by behavioral simulations [4]. Table I summarizes the modulator sizing achieving 13 [email protected] MS/s. Five groups of specifications are enclosed: modulator, front-end TABLE I MODULATOR SIZING TABLE II MAIN IN-BAND ERROR CONTRIBUTIONS integrator, amplifier, comparator, and A/D/A converter. In this procedure, the worst-case performance has been evaluated in the presence of variations in the process (for instance, changes in the capacitor absolute value), temperature, and supply. Table II shows a summary of the most significant contributions to the in-band error power. Main considerations made for this sizing are described next. The first step of the modulator sizing is the selection of . In this selection, both the overloading characteristics of the modulator and the nature of the signal being converted must be considered. In our case, the overloading point is nearly 5dB 52 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 51, NO. 1, JANUARY 2004 (a) (b) Fig. 8. (a) Time-domain representation of a 0 15-dB DMT signal. (b) SNDR of the converted DMT signal as a function of the reference voltage. (see Fig. 2), while the largest input is the 15-dB discrete multitone (DMT) signal shown in Fig. 8(a). Note that, although its power is not too high, large peaks appear from time to time, thus yielding the high crest factor [32] peculiar to DMT signals (5.4 in our case). Fortunately, the duration of these peaks is short enough not to overload the modulator. In order to illustrate this, Fig. 8(b) shows behavioral simulation results of the modulator SNDR for such an input signal as a function of the reference voltage. In spite of the presence of a signal peak of approximately 1 V, the modulator SNDR is correct up to V (note that this would never be the case for a 1-V amplitude input sinewave, since it would be inside the modulator overloaded region with 1.3-V reference). In order to provide a safety margin, V was taken. Returning to (7), this reference voltage gives us a margin of 500 mV per output transistor in a two-stage fully differential amplifier supplied with 2.5 V. As shown in Fig. 7, is implemented using differential references, so that . In Table II, the in-band error power of quantization error has been split up in its four contributions associated to: the ideal quantization error [first term in (4)], finite dc gain [first term in (6)], capacitor mismatch [second term in (6)], and last-stage DAC nonlinearity [second term in (4)]. Note that the quantization error leakage will be dominated by capacitor mismatch. Although M-i-M capacitors exhibit good matching— for 1-pF caps—the use of small unitary capacitors (0.66 pF) for dynamic considerations increases the sensitivity of the cascade, so that we have assumed twice that value for . The contribution of the 3-b DAC nonlinearity is 6 dB below the ideal quantization noise for INL FS, which is easily achievable without calibration. The noise leakage due to the amplifier dc gain is almost negligible for . However, as we explain further on, this value will not be further relaxed in order to avoid excessive distortion due to dc-gain nonlinearity. Following the discussion in Section III and in the Appendix, a small sampling capacitor pF is used in order to reduce the capacitive load of the integrators and, hence, their power dissipation. So, white circuit noise becomes the dominant error source. A more exact expression (than the one used in the Appendix) for its in-band error power is [3] GB (9) where is the amplifier input-referred white noise and GB is the effective amplifier gain–bandwidth product (in Hz), which during integration can be approximated to GB GB GB GB GB (10) where GB is the amplifier gain–bandwidth product (in Hz), is the switch on-resistance, and is the pole associated with the constant of the SC branch during integration. The first contribution in (9) yields a worst-case value of 86.0 dB—for maximum temperature 110 C and 20 tolerance in the capacitor value. On the other hand, for GB and fixed according to settling considerations to 265 MHz and 150 , respectively, GB will be 250 MHz. An equivalent thermal noise at the amplifier input of 6 nV Hz is therefore enough to obtain a noise contribution similar to that of the noise 87.5 dB . Besides, the worst-case amplifier white noise contribution corresponds to the largest GB , which varies along the process corners. Assuming that it can be as large as twice its nominal value (i.e., 500 MHz), this worst-case contribution yields 84.5 dB. The limited amplifier GB introduces basically a gain error in the integrator transfer function. This error is especially important in the integrators of the first stage of the cascade, because the quantization error of this stage will leak to the modulator output. For the architecture considered operating with , the amplifier must fulfill GB to avoid degradation of the modulator performance due to incomplete settling, being the sampling frequency. If the finite on-resistance of the switch is also considered, the effective amplifier response is slowed down, as stated in (10). This effect is illustrated in Fig. 9(a) that shows behavioral simulation results for the in-band error power as a function of the normalized amplifier GB, for different values of . The corresponding values of the normalized pole are also depicted. Note that, as the pole decreases, the amplifier GB must be increased in order to compensate for the slowdown. A switch resistance of 150 is fixed for this design. On the one hand, as we show further on, this resistance can be obtained using standard CMOS transmission gates, without clock boosting. On the other, the amplifier GB must be increased just to GB in order to maintain the modulator performance. Assuming that approximately 85% of the clock period is left for the integrator operation (after ensuring nonoverlapping and delay in the clock-phase signals), the required GB is approximately 265 MHz. DEL RIO et al.: HIGHLY LINEAR 2.5-V CMOS MODULATOR FOR ADSL 53 (a) (b) Fig. 9. (a) In-band error versus normalized amplifier GB for different switch on-resistances. (b) In-band error versus normalized amplifier SR for different input amplitudes. The required amplifier slew rate (SR) is established guarantying that the slew-rate limited evolution at the beginning of integration and sampling [33] is fast enough for the subsequent linear dynamic to settle to the desired accuracy. For this modulator, a normalized SR SR is sufficient to ensure correct performance. However, since the operation of the front-end integrator is partially SR limited, the dynamic will be also partially nonlinear and appreciable harmonic distortion may arise. This effect is illustrated in Fig. 9(b), where behavioral simulation results are shown for the modulator in-band error power versus the normalized amplifier SR, for different amplitudes of a sinewave input. Note that, for the correct conversion of an input sinewave of maximum amplitude (0.85 V), the normalized SR must be increased up to 6.5. Assuming that 85% of the clock period is left for the integrator operation, the required SR is approximately 800 V s. Thanks to oversampling, some specifications in Table I referring to the front-end integrator can be relaxed for the rest of integrators. Specifically, the value of the sampling capacitor in those integrators can be progressively scaled down, since their contributions to the overall noise are attenuated in the signal band. Nevertheless, matching considerations and reliability preclude using very small capacitors. In this design the scaling of the nominal (0.66 pF) is limited to 32%, which means that 0.45-pF unitary capacitors are used in the rest of inTABLE III SCALING OF THE AMPLIFIER SPECIFICATIONS tegrators. On the contrary, the input-referred white noise of the amplifiers at the modulator back-end can be considerably increased without jeopardizing performance. A more aggressive reduction can be applied to the other circuit requirements. For instance, the amplifier dc gain of the third and fourth integrators can be reduced to 600, because the in-band powers of the respective quantization error leakages are proportional to and , and the effect of their nonlinearity is negligible when compared to that in the front-end integrator. Moreover, the SR can be relaxed to 350 V s, as their settling behaviors are not so important. Table III summarizes the specifications for the four integrators in the cascade after scaling. VI. DESIGN OF THE BUILDING BLOCKS A. Amplifiers The triple tradeoff among dc gain, dynamics and output swing, always present in an amplifier [28], becomes tighter in a low-voltage implementation. We have already shown that the selection of the reference voltage and the topology of the front-end amplifier are interrelated in deep-submicron cascade Ms, the reason being that large enough requires two-stage amplifiers in order to achieve the dc gain and dynamic requirements. Fortunately, this is not the case for the amplifiers at the modulator back-end, whose dc gain can be largely relaxed, so that a single-stage amplifier may be enough. Therefore, in order to avoid over-sizing and optimize the power consumption, two different amplifiers have been designed: a high-dc-gain, high-speed amplifier for the first stage (OPA), and a modest dc-gain, high-speed amplifier for the third and fourth integrators (OPB). OPA is implemented using a two-stage two-path compensated architecture, shown in Fig. 10(a). It uses a telescopic firststage and both Miller and Ahuja compensation [34] through capacitors and , respectively. The common-mode feedback nets (CMFB) employed in the first and second stages are dynamic, because they have no static consumption and help to circumvent voltage range problems. A p-type input scheme has been preferred, the main reason being the possibility of cancelling the body effect in the pMOS devices—one of the mechanisms for substrate noise coupling [35]. Another reason for this choice is that, in the target technology, noise of nMOS devices is considerably larger than that of pMOS ones. Although noise usually plays a secondary role in telecom converters, since it normally does not alias and the low-frequency region of the spectrum is commonly out of the signal band, the noise 54 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 51, NO. 1, JANUARY 2004 (a) (b) Fig. 10. (a) Two-stage amplifier (OPA). (b) Single-stage amplifier (OPB). power spectral density (PSD) of very small devices can be huge [36] and sometimes poorly modeled, thus deserving special attention in deep-submicrometer implementations. This trend precludes using minimal length transistors, even more noticeably than if only matching considerations are taken into account. In our case, the devices contributing most to the amplifier noise are , , , and . In order to make the noise contribution negligible, the length of those devices was increased up to 0.5 m for the pMOS and 2 m for the nMOS. In the worst case, the in-band error power due to the noise of the front-end amplifier is –103.6 dB, low enough not to degrade the performance. OPB is implemented using a folded-cascode architecture, shown in Fig. 10(b), which is enough to accomplish the moderate dc gain requirement with reduced power dissipation. An SC CMFB is also employed. Table IV shows the features of OPA and OPB obtained by electrical simulation after full sizing. Results summarized correspond to the worst-case value of each parameter in a corner analysis—considering fast and slow device models, 5 variation in the 2.5-V supply, and temperatures in the range 40 C 110 C . The amplifier nonlinear features (mainly nonlinear dc gain and dynamics) deserve special attention in a low-voltage implementation. When the amplifier output voltage swings, the drain-to-source voltage of the output transistors changes, and so does the output impedance. This effect, illustrated in Fig. 11 for OPA, translates into a dependence of the open-loop dc gain on TABLE IV WORST-CASE ELECTRICAL SIMULATION RESULTS FOR THE AMPLIFIERS Fig. 11. DC gain nonlinearity of OPA at several process corners. the output voltage, so that the dc gain reaches its maximum at the central point and decreases as the output approaches the rails. Such a nonlinearity is traditionally modeled by a second-order polynomial dependence of the gain on the output voltage [4], but this is only valid for small voltage excursions around the central point. On the contrary, in a 2.5-V implementation, it is expected that small-gain regions of the dc curve (shadowed areas in Fig. 11) are often visited during normal operation of the modulator. In order to accurately account for this nonlinearity in behavioral simulations, we have resorted to a table look-up procedure from amplifier dc curves obtained by electrical simulation. A similar approach has been employed for validating the actual transient response of the front-end integrator. This step is aimed at avoiding inaccuracies of the single-pole SR limited behavioral model employed [33] when applied to the two-stage amplifier with nonconstant SR in the first integrator. B. Switches The design of the CMOS switches has been tackled with two main considerations in mind. First, the nonzero on-resistance heavily affects the integrator dynamic, slowing down its transient response. Second, the switch on-resistance can be highly dependent on voltage in low-voltage implementations. The sampling process with such a nonlinear resistance causes dynamic distortion [29] at the M front-end, the more evident the larger the signal frequency. Among the solutions to these problems, resorting to larger aspect ratios increases parasitics and power dissipation, whereas including clock-boosting [30] increases complexity and leads to a less robust design. According to settling considerations, resistances in the range of 150 can be tolerated in combination with the amplifier dynamics. In our process, such a value can be obtained using DEL RIO et al.: HIGHLY LINEAR 2.5-V CMOS MODULATOR FOR ADSL 55 Fig. 12. Switch on-resistance versus the voltage across it. Fig. 13. Circuit for the evaluation of the distortion introduced by the switches. standard-threshold CMOS transmission gates, with no need for clock boosters. The sizes of the pMOS and nMOS devices were selected to equalize their transconductances, keeping the resistance of the transmission gate as linear as possible. Fig. 12 shows its nominal dc characteristic. In order to evaluate the distortion, the nonlinear sampling has been extensively simulated using the differential circuitry in Fig. 13. Note that the distortion will be mainly determined by switches and (connected to the input), whereas and are connected to the central voltage that is constant. Electrical simulations have been performed to compute the first five in-band harmonics for a 0.85-V, 366-kHz input sinewave. Also, the DMT signal in Fig. 8(a) has been considered. Fig. 14 shows the worst-case results obtained for both type of inputs during the corner analysis: The worst-case total harmonic distortion (THD) is 96 dB for the input sinewave and the maximum multitone power ratio (MTPR) [32] of the converted DMT signal is 81 dB. Both figures are small enough for our application, so that clock-boosting is not required. C. Quantization Blocks The resolution specifications for the comparators in the first and second stage are not very demanding: offset and hysteresis smaller than 10 and 20 mV, respectively. However, the maximum comparison time is only 3 ns—a quarter of the worst-case clock period. For this reason, the latched comparator in Fig. 15 has been adopted. It includes a differential pair input transconductor [37], which attenuates the impact of common-mode interferences, a regenerative stage, and an SR latch. In this circuit, the small voltage imbalance created across the nMOS switch controlled by during the reset phase is rail-to-rail regenerated during the positive-feedback comparison phase. The latter starts when goes high, thus making the latch react before the integrator output changes at the beginning of . This strategy avoids using an extra SC stage at the comparator front-end. Differenced supply paths are used for the preamplifier and the regenerative latch in order to reduce the sensitivity to digital switching noise and supply bouncing. The 3-b A/D/A converter in the last stage has been implemented with a flash ADC and a resistive-ladder DAC, as shown in Fig. 16 [18]. The resistive-ladder is also used to generate the voltage references of the ADC. The latter has a fully differential flash architecture, where the thermometer output code is translated into a 1-of-8 code using AND gates. For improving robustness against common-mode interferences, seven differential comparators, similar to those in the first and second stage of the cascade, form the ADC front-end, each of them with two input pairs to perform the subtraction of the two differential signals being compared. Apart from this, the only difference with those in the firstand second-stage comparators is that the input transistors have been reduced in size in order to decrease the capacitive load of the fourth integrator. The DAC consists of 14 segments of 50poly resistors, the most important source of INL being resistor mismatch, which improves with device area. Thus, in order to guarantee that INL FS, each of the 50resistors is obtained by connecting larger devices in parallel. D. Auxiliary Blocks Fig. 17 shows the clock driver that generates the nonoverlapped clock phases—,—from an external clock signal. Delayed versions of the phases—,—are also generated to avoid signal-dependent clock-feedthrough. As shown in Fig. 7, the delay is incorporated only to the turn-off of the switches (falling edges of the signals) in order to increase the time slot available for sampling and integration [15]. Complementary versions of the phases are also generated to control the CMOS switches. All signals are properly driven at the output using a buffer tree that equalizes the differences in capacitive load from phase to phase. After ensuring reliable nonoverlapping time and phase delay, the worst-case effective phase eye is 6 ns, which means that approximately 85% of the clock period is left for the modulator operation. The reference voltages required for the modulator operation, namely V and V, together with the central voltage are on-chip generated by the circuit shown in Fig. 18. Its main design considerations are fast settling and that the output impedance of the and lines must be low enough to avoid dynamic distortion at the integrators [38]. In our case, 7maximum output impedance is obtained along the signal band through the combined use of an on-chip resistive amplifier and two big external capacitors. An extra external capacitor is connected between the reference voltages, valued according to the pad wire lead pin parasitics, so that the spurious components around half the sampling frequency are removed from the differential reference voltage. A second-order passive antialiasing filter is also included on-chip. Its bandwidth can be programmed to accomplish 62 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 51, NO. 1, JANUARY 2004 JoséM. de la Rosa received the “Licenciado en Física Electrínica”(electronics physics) degree and the Ph.D. degree from the University of Seville, Seville, Spain, in 1993 and 2000, respectively. Since 1994, he has been working at the Institute of Microelectronics of Seville (IMSE-CNM, CSIC). He is also with the Department of Electronics and Electromagnetism at the University of Seville, where he is an Associate Professor. His main research interests are in the field of switched-current sigma–delta analog-to-digital converters including analysis, behavioral modeling, and design automation of such circuits. In this topic, he has coauthored the book Systematic Design of CMOS Switched-Current Bandpass Sigma-Delta Modulators for Digital Communication Chips (Boston, MA: Kluwer, 2002). BelénPérez-Vérdúreceived the Liceniado en Físcia Electrónica and the Ph.D. degrees from the University of Seville, Seville, Spain, in 1979 and 1985, respectively. She has been an Associate Professor at the University of Seville since 1987. She is also with the Institute of Microelectronics of Seville (IMSE-CNM, CSIC). Her research activities are in the field of mixed-signal integrated circuit design, in particular, sigma–delta modulators, computer-aided design, and modeling of analog integrated circuits. She has published two books and more than 70 papers, including journal and conference papers. She has participated in several European ESPRIT projects and Spanish CICYT projects. Manuel Delgado-Restituto received the Ph.D. degree in physics from the University of Seville, Seville, Spain in 1996. In 1990, he joined the research staff of the Institute of Microelectronics of Seville (IMSE-CNM, CSIC). Since 1998, he has occupied a permanent position as a tenured Scientist of the Spanish Council for Scientific Research (CSIC). He has research interests in the design of analog and mixed-signal VLSI circuits for nonlinear signal processing, including vision chips, neuro-fuzzy controllers, and chaotic circuits for communications. His work in these areas has resulted in systematic design methodologies for these kinds of circuits. He is also interested in the design and modeling of integrated circuits for wireless and powerline communication systems and the design for reusability of analog and mixed-signal circuit blocks. He authored or coauthored more than 80 international scientific publications and has been involved in different national and European R&D projects. Rafael Domínguez-Castro received the “Licenciado en Física Electrínica”degree and the Ph.D. degree from the University of Seville, Seville, Spain, in 1987 and 1993, respectively. Since 1987, he has been with the Department of Electronics and Electromagnetism at the University of Seville, where he is currently an Associate Professor. He is also with the Institute of Microelectronics of Seville (IMSE-CNM, CSIC), where he is a member of a research group on Analog and Mixed-Signal VLSI. His research interests are in the design of embedded analog interfaces for mixed-signal VLSI circuits, design of CMOS imagers and CMOS focal plane array processors, and development on CAD for automation of analog design. Dr. Domínguez-Castro was a co-recipient of the 1995 Guillemin–Cauer Award of the IEEE Circuits and Systems Society and the Best Paper Award of the 1995 European Conference on Circuit Theory and Design. Fernando Medeiro received the “Licenciado en Física Electrínica”degree and the Ph.D. degree from the University of Seville, Seville, Spain, in 1990 and 1997, respectively. Since 1991, he has been with the Institute of Microelectronics of Seville (IMSE-CNM, CSIC). He is also with the Department of Electronics and Electromagnetism, University of Seville, where he is an Associate Professor. His research interests are in the field of sigma–delta converters, including modeling, behavioral simulation, and design automation. On this topic, he has participated as a Lecturer in several international courses and has coauthored the book Top-Down Design of High-Performance Sigma-Delta Modulators (Boston, MA: Kluwer, 1998). Angel Rodríguez-Vázquez (M’80–SM’95–F’96) received the Liceniado en Físcia Electrónica and the Ph.D. degrees from the University of Seville, Seville, Spain, in 1977 and 1983, respectively. He is a Professor of Electronics in the Department of Electronics and Electromagnetism, University of Seville. He is also a Member of the Research Staff of the Institute of Microelectronics of Seville (IMSE-CNM, CSIC), where he is heading a research group on Analog and Mixed-Signal VLSI. His research interests are in the design of analog interfaces for mixed-signal VLSI circuits, CMOS imagers and vision chips, neuro-fuzzy controllers, symbolic analysis of analog integrated circuits, and optimization of analog integrated circuits. Dr. Rodríguez-Vázquez served as an Associate Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I (IEEE TCAS-I) from 1993 to 1995, as a Guest Editor of the IEEE TCAS-I Special Issue on “Low-Voltage and Low-Power Analog and Mixed-Signal Circuits and Systems”(1995), as Guest Editor of the IEEE TCAS-II Special Issue on “Advances in Nonlinear Electronic Circuits”(1999), and as chair of the IEEE-CAS Analog Signal Processing Committee (1996). He was a co-recipient of the 1995 Guillemin-Cauer award of the IEEE Circuits and Systems Society and the Best Paper Award of the 1995 European Conference on Circuit Theory and Design. In 1992, he received the Young Scientist Award of the Seville Academy of Science.