Prototyping of fuzzy logic–based controllers using standard FPGA development boards

PROTOTYPING OF FUZZY LOGIC–BASED CONTROLLERS USING STANDARD FPGA DEVELOPMENT BOARDS S. Sánchez-Solano1, R. Senhadji1, A. Cab e a2, I. Ba u one1, C. J. Jiménez1, A. Ba iga1 1 Ins i u o de Mic oelec ónica de Se illa, Cen o Nacional de Mic oelec ónica, A da. Reina Me cedes s/n, E-41012-Se illa, Spain. 2 Dp o. Au omá ica y Compu ación, Facul ad de Ingenie ía Eléc ica, ISPJAE, Ciudad de la Habana, Cuba. P oc. 13 h IEEE In e na ional Wo kshop on Rapid Sys em P o o yping (RSP’2002), pp. 25-32, Da ms ad , July 1-3, 2002. © 2002 IEEE. Pe sonal use o his ma e ial is pe mi ed. Howe e , pe mission o ep in / epublish his ma e ial o ad e - ising o p omo ional pu poses o o c ea ing new collec i e wo ks o esale o edis ibu ion o se e s o lis s, o o euse any copy igh ed componen o his wo k in o he wo ks mus be ob ained om he IEEE. This ma e ial is p esen ed o ensu e imely dissemina ion o schola ly and echnical wo k. Copy igh and all igh s he ein a e e ained by au ho s o by o he copy igh holde s. All pe sons copying his in o ma ion a e expec ed o adhe e o he e ms and cons ain s in oked by each au ho ’s copy igh . In mos cases, hese wo ks may no be epos ed wi hou he explici pe - mission o he copy igh holde . P o o yping o Fuzzy Logic–Based Con olle s Using S anda d FPGA De elopmen Boa ds S. Sánchez-Solano1, R. Senhadji1, A. Cab e a2, I. Ba u one1, C. J. Jiménez1, A. Ba iga1 1 Ins i u o de Mic oelec ónica de Se illa, Cen o Nacional de Mic oelec ónica, A da. Reina Me cedes s/n, 41012-Se illa, Spain. <[email p o ec ed]> 2 Dp o. Au omá ica y Compu ación, Facul ad de Ingenie ía Eléc ica, ISPJAE, Ciudad de la Habana, Cuba. <ale[email p o ec ed]> Abs ac This pape desc ibes a design me hodology o uzzy log- ic-based con ol sys ems. The me hodology employs ha d- wa e/so wa e codesign echniques acco ding o an ‘a p io i’ pa i ion o he asks assigned o he selec ed com- ponen s. This ea u e makes i possible o ackle he con ol sys em p o o yping as one o he design s ages. In ou case, hepla o mconside ed o p o o ypinghas been a de elop- men boa d con aining a s anda d mic ocon olle and an FPGA. Expe imen al esul s om an ac ual con ol appli- ca ion alida e he e iciency o his me hodology. 1 In oduc ion The g owing complexi y o cu en elec onic sys ems oge he wi h he need o dec easing he ime- o-ma ke when launching a new p oduc ha e mo i a ed e y much heuseand de elopmen o CAD ools ha ease he desc ip- ion, e i ica ion and syn hesis o elec onic sys ems. This demand is becoming s onge as challenging applica ions aimed a in eg a ed a whole sys em on a chip (SoC) a e in- c easing. Taking in o accoun he cha ac e is ics o in eg a - ed ci cui s ab ica ion p ocesses such as cos , deli e ing ime, e c., i is e y use ul he a ailabili y o mechanisms which pe mi he apid and cheap p o o yping o he sys em unde de elopmen in o de o e i y i s global unc ionali y be o e i s possible in eg a ion. This o en means he use o gene al-pu pose pla o ms. This pape ocuses on he design me hodology o uzzy logic-based con ol sys ems. Following he abo e com- men ed ideas, one o he s eps o ou design low will be he p o o yping o he whole sys em on a de elopmen boa d ha includes a gene al-pu pose mic ocon olle and an FP- GA, hus eso ing o he use o ha dwa e/so wa e codesign echniques. The me hodology employs speci ic ools o he de elopmen o uzzy con olle s and gene ic ools o a wo old ask: he syn hesis o componen s om ha dwa e desc ip ion languages, on one side, and he p og amming o s anda d mic ocon olle s, on he o he side. 2 Fuzzy con olle s The capabili y o uzzy con olle s o desc ibe wi h sim- ple ules he linguis ically exp essed expe ience and knowl- edge o a human expe and o achie e ha wi hou he need o a ma hema ical model o he plan unde con ol, ha e mo i a ed a g ea inc ease in he numbe o con ol applica- ions using uzzy logic-based in e ence echniques [1]. A uzzy con olle employs he same inpu and ou pu a iables han i s con en ional coun e pa . Fo ins ance, he ou pu a ia ion o a PI con olle a each i e a ion is unc ion o he e o and he e o a ia ion a he p e ious i e a ion: (1) The di e ence be ween he con en ional and he uzzy app oaches is ha in he i s one, he ou pu is ob ained as a lineal combina ion o he inpu s, (2) while in he uzzy app oach, he con ol heu is ic is de ined by a ule se ha employ linguis ic a iables ep esen ed by uzzy se s (Figu e 1). This is he eason why he con ol su ace p o ided by a uzzy con olle is usually non lineal and can be modi ied locally by changing he ules ha a ec he co esponding uni e ses o discou se. In addi ion, he use o uzzy logic- based in e ence echniques allows he de elopmen o o- bus de ices able o suppo g ea e pe u ba ions han a con en ional one and o p o ide so ou pu a ia ions wi h a small numbe o ules. These ea u es make i possible o o e come he au oma iza ion o complex con ol asks ha cu en ly can be ca ied ou only by human ope a o s. O he epo ed ad an ages o uzzy con olle s a e ha hey o en educe he de elopmen cos and main enance o con ol sys ems [2]. ∆unT() FenT()∆enT(),()= ∆unT() kIenT()kP∆enT()⋅+⋅= 3 Implemen a ion o uzzy con ol sys ems Figu e 2 illus a es he gene ic s uc u e and asks pe - o med by a uzzy logic-based con olle . The a iables de- ining he plan s a us a e acqui ed by a se o senso s ha ansla e hem in o elec ical signals ep esen ed by cu en s o ol ages. The signal condi ioning inpu s age implemen s heA/Dcon e sionand ange adjus men oge he wi h se - e al p ep ocessing algo i hms equi ed o ob ain adequa e inpu signals o he in e ence engine. This engine is in cha ge o e alua ing he se o inpu s (using a uzzi ie ), cal- cula ing he new con ol ac ion acco ding o he s a egy de- ined by he se o in e ence ules, and compu ing he non- uzzy ep esen a i e alueso hecon olac ion(usingade- uzzi ie ). The signal condi ioning ou pu s age pos p o- cesses hese alues and adequa es hem o he ac ua o s connec ed o he plan . In addi ion o hese asks, e e y con- ol sys em usually includes elemen s o ini ialize he sys- em, o de ine he con ol a ge s, and o moni o he achie emen o he a ge s, as well as iming elemen s o en- su e he co ec beha io o he sys em. Excep o he A/D and D/A con e sions, all he abo e commen ed asks (including he in e ence mechanism) can be pe o med by so wa e, so ha he con ol sys em can be implemen ed wi h a p og ammable p ocesso . Many appli- ca ions o indus ial o consume p oduc s eso o his ype o implemen a ion [3]. The p oblem appea s whene e he applica ion demands uzzy con ol sys ems wi h a high in- e ence speed and/o low size and powe . Since s anda d so wa e app oaches a e no able o mee hese equi e- men s, se e al solu ions ha e been epo ed. Some o hese solu ions y o imp o e he esponse ime o he con olle by expanding, ia so wa e o ha dwa e, he ins uc ion se o an s anda d p ocesso . Taking in o accoun ha many o he ope a ions equi ed o ca y ou he uzzy in e ence limi o a g ea ex end he ope a ional speed o he uzzy con ol- le , he idea is o speed up he execu ion o ope a ions such as he maximum, minimum, o de uzzi ica ion [4]. In he so wa e app oach, he p ocesso mic op og amming is modi ied o add unc ionali y o he ins uc ion se [5]-[6], while in he ha dwa e app oach, new ci cui y is included in he p ocesso a chi ec u e [7]-[9]. When he speed, size and/o powe equi emen s a e e- s ic i e, he solu ion is o implemen he uzzy con olle 1. IF e o e(k) is posi i e AND e o a ia ion ∆e(k) is nea ze o THEN con ol a ia ion ∆u(k) is posi i e. 2. IF e o e(k) is nega i e AND e o a ia ion ∆e(k) is nea ze o THEN con ol a ia ion ∆u(k) is nega i e. 3. IF e o e(k) is nea ze o AND e o a ia ion ∆e(k) is nea ze o THEN con ol a ia ion ∆u(k) is nea ze o. (a) 0 0.5 1–0.5–1 µ nega i e ze o posi i e (b) Figu e 1: Example o ule base (a) and uzzy se s (b) used by a uzzy PI con olle . Inpu signal condi ioning Senso s Plan Ac ua o s Fuzzi ie De uzzi ie Rule base Figu e 2: Block diag am and asks o a uzzy logic-based con ol sys em. In e ence engine Sys em asks: Ini ializa ion Ta ge de ini ion Inpu p e-p ocessing Fuzzy in e ence Ou pu pos -p ocessing Moni o ing mechanisms Sys em iming Ou pu signal condi ioning wi h speci ic analog o digi al ha dwa e ha ollows an e - icien a chi ec u e [10]. Some key poin s o achie e low cos and high speed digi al uzzy con olle s a e o es ic he shapes o he uzzy se s membe ship unc ions o he in- e ence ules, o use simpli ied de uzzi ica ion me hods, and oe alua eonly hecon ibu iono heac i e ules[11]. Acco ding o hese conside a ions and hinking in chal- lenging applica ions wi h es ic i e equi emen s, he s a - egy desc ibed in his pape combines speci ic ha dwa e o implemen ing he uzzy in e ence wi h a gene al-pu pose p ocesso o ca ying ou he es o he asks by so wa e. 4 Design me hodology The design p ocess o an elec onic sys em can be g ea - ly accele a ed by wo mechanisms. One o hem is he use o a design me hodology which de ines he di e en design s ages and hei in e ela ions. The second one is he use o CAD ools which ease he designe asks a each s age. In ou case, he X uzzy en i onmen wi h i s CAD ools (x c, x sim,x lab, and x hdl) is e y help ul in he design low o uzzy logic-based con ol sys ems, as shown in Figu e 3 [12]. S a ing om he o mal desc ip ion o he sys em, his design low is aimed a he ealiza ion o uzzy sys ems on chip employing ha dwa e/so wa e codesign echniques. Be ween hese ex eme s ages, h ee o he s ages a e ca ied ou : o -line simula ion, on-line e i ica ion (whene e pos- sible), and p o o yping wi h low-cos de elopmen boa ds. 4.1 Sys em speci ica ion The ha dwa e/so wa e pa i ioning o he di e en asks o be pe o med by he con ol sys em is done acco ding o he conside a ions commen ed in Sec ion 3. This has led us o implemen he in e ence p ocess by ha dwa e while he es o he asks (such as p e- and pos -p ocessing) a e ca - ied ou by so wa e. The use o codesign echniques means ha he con ol sys em speci ica ion equi es he desc ip- ion o ha dwa e as well as so wa e componen s. The XFL language is employed o he speci ica ion o he uzzy in- e ence componen [13]. This is he language sha ed by all he ools o he X uzzy en i onmen . The C language is em- ployed o speci ying he es o he asks since i allows he au oma ic gene a ion o p og amming code ( he e a e many C compile s, assemble s and linke s o mos o gene al- pu pose p ocesso s) and i is e y easy o X uzzy o in e- g a e C code. The XFL language allows he use o de ine com o ably no only he uni e ses o discou se o he uzzy con olle a iables, hei associa ed membe ship unc ions, and he ule bases employed, bu also he se o uzzy ope a o s ha implemen he an eceden connec ion, he implica ion unc- ion, he mechanism o ule agg ega ion, and he de uzzi i- ca ion me hod. 4.2 O -line simula ion The X uzzy en i onmen has a ool named x c which pe - mi s ob aining a C desc ip ion o he uzzy in e ence engine om i s XFL speci ica ion. The code gene a ed by x c o- ge he wi h he p og amming code associa ed o he es o he con ol asks can be combined wi h a C model o he plan unde con ol o simula e he beha io o he whole closed-loop con ol sys em. This is possible wi hin he X uzzy en i onmen hanks o a ool named x sim. This ool is e y use ul o allow a p elimina y adjus men o he con- ol sys em pa ame e s. Howe e , since he model used o ep esen he plan is usually a i s -o de app oxima ion, he esul s o his simula ion could no be eliable enough o con ol sys ems o a ce ain complexi y. In hese cases, he ac ual plan o p ocess has o be analyzed o ob ain a in- e adjus men o he con ol sys em pa ame e s. One solu- ion is o include he ac ual plan in o he con ol loop whe e he con ol sys em is implemen ed by a compu e unning a C p og am. This is he objec i e o he ollowing design s age: an on-line e i ica ion. I is impo an o no ice ha C XFL C Fuzzy in e ence sys em O he aks Plan model x sim x lab x c VHDL P ocesso model compile FPGA syn hesis ool FPGA µC VHDL x hdl ha dwa e syn esis ool Sys em Speci ica ion (HW/SW Pa i ioning) O -line Simula ion On-line Ve i ica ion P o o yping Silicon Implemen a ion Figu e 3: Design low and CAD ools o uzzy con ol sys ems. C ASM his e i ica ion is possible whene e he esponse ime o he compu e mee s he plan dynamic equi emen s. 4.3 On-line e i ica ion The ool x lab included in o he X uzzy en i onmen p o- ides he needed mechanisms o communica ing he com- pu e ha uns he so wa e implemen a ion o he uzzy con olle wi h he plan unde con ol ia a da a acquisi ion boa d connec ed o he in e nal bus o he PC [14]. The ool x lab con ains d i e s o ead and w i e da a om and in he boa d, so ha he model o he plan used in he o -line e - i ica ion can be eplaced by a unc ion ha allows moni o - ing he ue plan , hus ob aining he equi ed in o ma ion o execu e he uzzy con ol (inpu channels), as well as ac u- a ing on he plan p o iding he con ol ac ion ia he ou pu channels. X lab eases he con igu a ion o he da a acquisi ion boa d (de ini ion o he inpu and ou pu add esses, assigna- ion o he analog and digi al channels, e c.), he codi ica- ion o he equi ed p ocedu es ( il e ing, linea iza ion, e c.), and he in eg a ion o hese asks wi h bo h he so - wa e implemen a ion o he con olle and he ou ines o access he ac ual plan . One o he mos ele an ad an ages o e ed by x lab is he capabili y o moni o ing he beha io o he whole sys em a eal ime, allowing he e alua ion o a g ea a ie y o ope a ion condi ions as well as he in lu- ence o he di e en con ol pa ame e s on he sys em e i- ciency. Figu e 4-a shows one window o he x lab GUI whe e he di e en componen s o he con ol p og am a e speci ied. The window whe e he sys em moni o ing is con- igu ed is shown in Figu e 4-b. Once he con ol sys em has been adjus ed con enien ly, we ha e a so wa e implemen a ion o he con ol sys em which is qui e ope a i e. This will be he s a ing poin o p o o yping he sys em on a de elopmen boa d. 4.4 P o o yping The a ailabili y o de elopmen boa ds ha include a gene al-pu pose mic ocon olle wi h an FPGA allows he implemen a ion o a whole con ol sys em by pa i ioning he di e en asks be ween hem. As commen ed in Sec ion 3, he uzzy in e ence is assigned o an speci ic con olle implemen ed on he FPGA, while he ou ines o p ocess- ing he inpu and ou pu a iables o he uzzy con olle , o- ge he wi h all he o he asks a e p og ammed in he mic ocon olle . The iming ask is implemen ed by one o he ime s a ailable in he mic ocon olle . Addi ional ci - cui y is equi ed o adap he signals p o ided by he sen- so s o he de elopmen boa d as well as o adap he ou pu signals o he boa d o hose employed by he ac ua o s. This means he inclusion o ci cui s such as signal ampli i- e s and da a con e e s. Au oma ic syn hesis ools a e una oidable i we wan o comple e his s age apidly and e icien ly. One o he mos ou s anding ea u e o X uzzy compa ed wi h o he en i on- men s is ha X uzzy includes ools ha ease he ha dwa e syn hesis o he designed uzzy con olle . One o hem, which is named x hdl [15], ansla es he XFL desc ip ion o he uzzy in e ence sys em in o a VHDL desc ip ion ha is compa ible wi h se e al ha dwa e syn hesis ools o FPGA o ASIC ealiza ions. Figu e 4: X lab windows illus a ing he ask assignmen ca ied ou in he on-line e i ica ion s age. P e- & pos -p ocessing Timing Ini ializa ion & a ge de ini ion Moni o ing On he o he side, he use o de elopmen ools and p o- g am debugge s (assemble s, compile s, simula o s, e c.) ease he p og amming o he di e en asks o be pe o med by he mic ocon olle . The a ailabili y o C compile s o he chosen mic ocon olle is a ac o o ake in o accoun since i educes g ea ly he de elopmen ime. 4.5 Silicon implemen a ion Once checked ha he p o o ype pe o mance is as de- si ed, he designe can inc ease he in eg a ion le el o he con ol sys em o achie e less a ea and powe consump ion. Thinking in an ASIC implemen a ion, he good s a ing poin is he VHDL desc ip ion o he whole sys em. In ou design low, his means o combine he VHDL o he uzzy in e ence engine wi h he VHDL desc ip ion o he selec ed mic ocon olle co e. 5 Applica ion example The abo e desc ibed me hodology has been applied in he design o a le el con olle o a dosage sys em. As shown in Figu e 5a, he dosage sys em is composed o wo independen cylind ical anks bo h wi h an elec onic al e a i s op o con ol he liquid injec ion, wi h a p essu e sen- so a i sbo om op o ideameasu eo heliquidle el,and wi h a manually-con olled al e also a i s bo om o dis- cha ge liquid in o a sha ed con aine [16]. A ol age-con- olledwa e pumpmo es heliquidup o he anks om he sha ed con aine . The p essu e senso s p o ide a cu en ou pu signal be- ween 4 and 20 mA, whe eas he elec onic al es and he wa e pump a e con olled by ol age inpu signals be ween 0 and 10 V. The con ol s a egy applied is he uzzy e sion o a PI con olle wi h an inc emen al ou pu . This means ha he uzzy con olle equi es wo inpu signals ( he e o and i s a ia ion) o each ank, and p o ides an ou pu sig- nal ha ep esen s he change o i s co esponding al e ap- e u e. The wa e pump is go e ned by he bounded sum o bo h con olle ou pu s. Due o he symme y o he wo anks, hei uzzy con- olle s a e iden ical, so ha only one o hem can be imple- men ed i he in e ence p ocesses a e execu ed sequen ially. Thissolu ionpe mi sag ea a ea educ ion wi hou inc eas- ing he esponse ime signi ican ly. The con ol sys em p o o yping was ca ied by using an XS40-005XL boa d om XESS Co po a ion [17] moun ed on a boa d ha also includes he A/D and D/A da a con e - e s oge he wi h he signal condi ioning ci cui y (Figu e 5b). The XS40-005XL boa d has an In el 8031 mic ocon- olle , a Xilinx XC-4005 FPGA, 32 K o SRAM, a p o- g ammable clock ci cui , a 7-segmen LED display, and connec o s o communica ing he boa d wi h a PC ia a pa allel po , an VGA ou pu , and a PS/2 inpu . The boa d is p o ided wi h so wa e acili ies o p og am he clock (GXSSETCLK), o download he con igu a ion o he FPGA and he p og am o he mic ocon olle (GXS- LOAD), and o es he boa d (GXSTEST). The syn hesis s age o he FPGA was ca ied ou wi h he "Xilinx Founda ion 3.1i" en i onmen . On he o he side, he VHDL desc ip ion o he uzzy con olle was ob ained om i s XFL speci ica ion wi h he aid o he x hdl ool o X uzzy.Since he uzzyin e enceengineimplemen edin he FPGA wo ks as a cop ocesso o he 8031 mic ocon olle , se e al in e ace ci cui s has o be added o he FPGA. As a esul , he 98% o he FPGA CLBs a e employed (193 de Figu e 5: Expe imen al se up: a) Dosage sys em. b) Con ol sys em implemen a ion. c) De elopmen sys em. (a) (b) (c) 196), and he maximum ope a ional equency eaches 20 MHz. A a 10 MHz equency, he uzzy in e ence cycle akes 700 ns, which is sho e han he execu ion ime o a mic ocon olle ins uc ion. The so wa e implemen a ion in he 8031 was pe o med by using se e al de elopmen ools a ailable o he MCS- 51 amily. The code downloaded o he mic ocon olle co e s he ypical asks o a con ol cycle (acquisi ion and p ep ocessing, communica ion wi h he in e ence engine, pos p ocessing and ou pu gene a ion), and includes se e al in e up se ice ou ines as well as ou ines o allow com- munica ionwi ha PC in o de o e alua e he sys em pe o - mance (Figu e 5c). The designed p o o ype has been p o ed sa is ac o y in di e en expe imen al es s, p o iding a obus con ol which ensu es a good beha io o he dosage sys em e en unde ha d changes in he ape u e o he manually con- olled al es. As an example, Figu e 6 illus a es how he liquid le els o he wo anks ollow di e en a ge posi- ions (dashed lines) wi h he ypical ipple caused by he liq- uid d opping. 6 Conclusions The use o codesign echniques acco ding o a gi en pa - i ioning o he asks assigned o he ha dwa e and so wa e componen s has been p o ed o be an e icien s a egy o designing high-speed and low-consump ion uzzy logic based con ol sys ems. Acco ding o his s a egy, a design me hodology has been desc ibed ha employs se e al ools o he X uzzy en i onmen and ha includes, as one o i s designs ages, he p o o yping o he sys em using a low cos de elopmen boa d wi h a mic ocon olle and an FPGA. The alidi y o he p ocedu e is illus a ed by i s success ul applica ion o sol e an ac ual dosage p oblem. Re e ences [1] Passino, K. M., Yu ko ich, S., Fuzzy Con ol, Addison-Wes- ley, 1998. [2] Te ano, T., Asai, K., Sugeno, M., Eds., Applied Fuzzy Sys- ems, Academic P ess, 1994. [3] Yen, J., Langa i, R., Zadeh, L. A., Eds., Indus ial Applica- ions o Fuzzy Logic and In elligen Sys ems, IEEE P ess, 1995. [4] Salapu a, V. A Fuzzy RISC P ocesso , IEEE T ansac ions on Fuzzy Sys ems, Vol. 8, N. 6, Dec. 2000. [5] Unge ing A. P, Gose , K., A chi ec u e o a 64-bi uzzy in e - ence p ocesso , FUZZIEEE’94, pp. 1776-1780, O lando, 1994. [6] Von Al ock, C. Adap ing exis ing Ha dwa e o Fuzzy Com- pu a ion, Ins i u e o Physics Publishing, 1998. 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Sánchez-Solano, S., XFL:A Language o he De ini ion o Fuzzy Sys ems, FUZZ- IEEE’97, pp. 1581-1591, Ba celona, Jul. 1997. [14] Senhadji, R., Sánchez-Solano, S., López, D.R. Ba iga, A., X lab: An On-line Ve i ica ion Tool o Fuzzy Con olle s, IPMU’2000, pp.. 44-49, Mad id, Jul. 2000. [15] Lago, E., Jiménez C.J., López D.R., Sánchez-Solano S., Ba - iga A., X hdl: A Tool o he Syn hesis o Fuzzy Logic Con- olle s, DATE’98, pp. 102-107, Pa is, Feb. 1998. [16] Cab e a, A., Senhadji, R., Sánchez-Solano, S., Ba iga, A., Jiménez, C.J., Llanes, O., De elopmen o Le el Con olle s Based on Fuzzy Logic, NF’2002, Ciudad de la Habana, Jan. 2002. [17] XS40, XSP Boa d V1.4 Use Manual, XESS Co po a ion, USA, 1999. Figu e 6: Expe imen al esul s. 0 1000 2000 3000 4000 5000 0 20 40 60 80 numbe o samples liquid le el (cm)