A first order incremental analog to digital converter based on continuous time circuits

XVII IMEKO Wo ld Cong ess Me ology in he 3 d Millennium June 22 − 27, 2003, Dub o nik, C oa ia A FIRST ORDER INCREMENTAL ANALOG TO DIGITAL CONVERTER BASED ON CONTINUOUS TIME CIRCUITS Rica do Doldan, Albe o Yu e a and Ado acion Rueda Ins i u o de Mic oelec onica de Se illa (IMSE), Se illa, Spain Abs ac - In his pape , an inc emen al Analog- o- Digi al Con e e (ADC) designed as pa o he signal- condi ioning ci cui y o issue impedance measu emen sys em is p esen ed. Con inuous- ime design echniques has been used and a modi ied implemen a ion o he con e sion algo i hm, wi h espec o i s disc e e- ime coun e pa , has been de eloped. To educe he in luence o he no-ideali ies, analog and digi al co ec ions ha e been also implemen ed. A p o o ype in 0.8µm CMOS echnology has been ab ica ed and es ed. Expe imen al esul s a e epo ed. Keywo ds Analog o Digi al Con e sion. 1. INTRODUCTION In his wo k, we p esen he design and implemen a ion o a i s o de Inc emen al Analog- o-Digi al Con e e (ADC) using he con inuous- ime app oach. In pa icula , he OTA-C echnique is applied o design he main analog signal p ocessing unc ions, such as in eg a o and adde s, as an al e na i e o Swi ched Capaci o (SC) app oach o low ol age condi ions. This wo k is pa o a p ojec aimed a es ablishing a design p ocedu e o issue impedance measu emen wi h applica ion in measu e o biological pa ame e [1]. The p oposed measu emen sys em is shown in Fig. 1. I is based on a ou -elec odes con igu a ion (ZE1 o ZE4), in which wo o hem (ZE1, ZE4) a e employed o s imula e he issue sample (SUT) o unknown impedance Zx, and he o he wo (ZE2, ZE3) ake he SUT esponse. A e ampli ica ion and p ocessing s eps, wo digi al signals a e ob ained o eal and imagina y pa s o he issue complex impedance, Zx. Bo h a e digi ally codi ied o pa allel ansmission. Inc emen al con e e s based on sigma-del a modula ion, double- amp p inciple, o mul i ib a o a e no mally used in hese applica ions [2-4], p o iding high accu acy, good linea i y, and educed o se le els. In ou case, a i s o de inc emen al con e e wi h a bi pa allel digi al ou pu has been conside ed. The pape is o ganized as ollows. The con e sion algo i hm is b ie ly desc ibed in Sec ion 2. The design o he basic building blocks o con inuous ime analog o digi al con e sion is p esen ed in Sec ion 3. Sec ion 4 shows expe imen al esul s. Finally, some conclusions a e gi en in Sec ion 5. - +V o ZE4 ZE3 ZE2 ZE1 ZxSUT VCO I+ A A/D Demodula o A/D b(I) b(R) I- Demodula o clock-phase clock-quad Zx Imagina y Zx Real Vx elec ode model issue model Fig. 1. Blocks en ol ed in he eal and imagina y impedance measu emen sys em 2. THE ANALOG TO DIGITAL ALGORITHM The ope a ion p inciple o an inc emen al ADC elies on changing ol age- esolu ion o ime- esolu ion, pe o ming he in eg a ion o he analog inpu o ob ain a bi -s eam ou pu [2]. This ou pu is easily ans o med in o a digi al wo d by basic digi al ci cui s. The block diag am o he ADC is illus a ed in Fig. 2. This inc emen al con e e wo ks as a sigma-del a modula o wi h a ese signal a he beginning o each con e sion. I s main blocks a e he in eg a o and he compa a o . O he blocks a e he inpu signal mul iplexe , he con ol block o ese and in e he in eg a o ou pu ol age, and he digi al ou pu signal p ocessing, basically a coun e . The basic algo i hm wo ks as ollows: a di e en ial signal (Vin = Vinp-Vinn) is con inuously in eg a ed. The in eg a o ou pu (Vop) is hen compa ed wi h ze o. Fo posi i e alues, a -VRe alue will be added a he in eg a o inpu , Vin; Fo nega i es, VRe will be. E e y T seconds Vop is compa ed wi h ze o, being he ou pu , Ncon, a n-bi digi al wo d p opo ional o he imes ha VRe has been added and sub ac ed a he inpu . This e e ence ep esen s he hal o con e e Full Scale, so ha he LSB is gi en by VRe / 2n-1 o a con e e o n bi s. The decision o add/sub ac depends on he compa a o ou pu . The P oceedings, XVII IMEKO Wo ld Cong ess, June 22 – 27, 2003, Dub o nik, C oa ia TC1 P oceedings, XVII IMEKO Wo ld Cong ess, June 22 – 27, 2003, Dub o nik, C oa ia TC1 P oceedings, XVII IMEKO Wo ld Cong ess, June 22 – 27, 2003, Dub o nik, C oa ia TC4 701 con e sion ime is ixed by he numbe o bi s. A disc e e- ime ealiza ion o he con e e equi es h ee basic ope a ion modes: ese , sample and posi i e con e sion. A desc ip ion o hese ollows. In he i s clock pe iod, Rese Mode, he in eg a o is au oze oed. Nex , in Sample Mode, he analog inpu signal is connec ed o he in eg a o posi i e inpu , gi ing Vop=Vin *. The Posi i e Con e sion Mode (PCM) in e al is 2nT (whe e T is he clock pe iod), du ing which he compa a o pe o ms 2n disc imina ions. Ini ially, depending on he posi i e o nega i e sign o Vin *, VRe is sub ac ed om o added o Vin *, espec i ely. Adding o sub ac ing means o pu he VRe signal in o he in eg a o posi i e o nega i e inpu e minal espec i ely, hus a oiding he need o wo ol age e e ence VRe and -VRe . Adding and sub ac ing VRe also mo es he coun e s a e up and down. Wi h Nu1 and Nd1 ep esen ing he numbe o up and down coun s, espec i ely, he in eg a o ou pu a e 2n clock pe iods will be: Vop 2n () Nd1Nu1 – () VRe Nu1Nd1 + () Vin∗ += (1) and, NN u1Nd1 –2nVin∗ VRe ------------    Vop 2n () VRe ------------------–== (2) The analog- o-digi al con e sion is hus ealized, and N ep esen s he s a e o he ou pu coun e ob ained as he di e ence be ween he up and down coun s. The accu acy o he digi al ep esen a ion o Vin * is n bi s. One ex a bi can be ob ained by de ec ing he sign o Vop(2n). Due o he high numbe o in eg a ion s eps, his ype o con e sion can be c i ical o he in eg a o inpu equi alen o se . A digi al co ec ion echnique, as p oposed in [3], can be used. In his case, wo addi ional ope a ion modes a e necessa y: in e sion and nega i e con e sion modes. A e he i s 2n-1 posi i e con e sion cycles, he signal a he in eg a o ou pu is in e ed. The in eg a o ou pu in he nex clock pe iod will be -Vop1, whe e Vop1 = V op(2n-1) is gi en by (1) using n-1 ins ead o n. This is he In e sion Mode. Du ing he ollowing 2n-1 clock cycles he Nega i e Con e sion Mode (NCM) ope a es simila ly o PCM, bu now he -Vin* inpu signal is sampled and compa ed o ze o. Up and down coun s a e decided in e sely as in PCM. A he end, he signal accumula ed a he in eg a o ou pu is, ∫ + - Cloc k V op Vinp Vinn VRe Rese and In e sion Digi al Con ol Vcomp COUNTER Vn VpSignal Inpu Mul iplexe DSP Ncon Vop 2n () V –op1 2n1 –Vin∗ –Nu2 Nd2 – () VRe + = (3) and, Vop 2n () 2nVin∗ –2NVRe += (4) whe e 2N=(Nu2-Nd1+Nu1-Nd2) is an n-bi digi al wo d. In his case, he ex a sign bi (d) will be “1” i Vop(2n+1) < 0 and “0” o he wise. The inal digi al wo d, Ncon, will be ob ained as 2N+d. Fig. 2. Concep ual schema ic o an inc emen al ADC The desc ibed ADC has he ad an age ha i s esolu ion does no depend on he in eg a o gain e o s, and u he mo e, he in eg a o non-signal dependen o se is cancelled. An impo an p ope y ha mus be p ese ed is he use o an unique VRe . The eason o his is ha misma ching be ween VRe and - VRe gene a es ou pu e o s which inc ease wi h he numbe o bi s. The same conside a ions apply o he inpu signals. 3. CONTINUOUS TIME IMPLEMENTATION In he con inuous ime e sion o he ADC, he basic idea has been o di ide each in eg a ion pe iod, T, in o wo in e als, in such a o m ha he inpu signal, Vin, and he e e ence signal, VRe , will be in eg a ed in di e en imes: he inpu in (0,T/2), and he e e ence in (T/2,T), espec i ely. This is illus a ed in Fig. 3. In his algo i hm, a compa ison by cycle is ca ied ou a T/2. Analysing he inal esul he ou pu digi al code is ob ained as, Ncon Vin∗ VLSB -------- = (5) ha ep esen s he in ege pa ope a o o his a io. This modi ied algo i hm sol es some p oblems de i ed om con inuous ime implemen a ions, in pa icula due o he in eg a o , since e o s in linea in eg a ion will be high due o he in luence o he ini e ansconduc o ou pu esis ance [6]. When he inpu signal Vin * app oach o he FS limi s, he e ec i e pe iod o in eg a ion inc eases since Vop changes i s sign only a e y ew imes. In hese si ua ions, he in eg a o ou pu esis ance will deg ade he quali y o he in eg a ion p ocess. P oceedings, XVII IMEKO Wo ld Cong ess, June 22 – 27, 2003, Dub o nik, C oa ia TC1 P oceedings, XVII IMEKO Wo ld Cong ess, June 22 – 27, 2003, Dub o nik, C oa ia TC1 P oceedings, XVII IMEKO Wo ld Cong ess, June 22 – 27, 2003, Dub o nik, C oa ia TC4 702 The speci ica ions o he a ge ed ADC a e: 12 bi s, a 50kHz clock, a ol age supply below 3V, and an inpu ange o 0.5V in bipola condi ions. The ci cui s equi ed o ha a e bo h analog and digi al. The block diag am o he analog pa is shown in Fig. 4. I includes a con olled wo-inpu in eg a o and a compa a o . The unc ionali y o each block is b ie ly explained in he ollowing. The inpu mux block is con olled by he S in digi al signal, which selec s when he in eg a o has o p ocess he ADC inpu o a ze o inpu . The INV block applies o signal in e sions. Bo h blocks a e implemen ed wi h CMOS analog swi ches, whose on- esis ance mus be op imized when hey a e in he signal pa h. The RES block discha ges he capaci o when he con e sion ends. Fo he e e ence signal in eg a ion he same OTA han o he inpu is used, whose ope a ion is now con olled by he S e digi al signal, sou cing/sinking (b o sou cing, and b o sinking, being b he compa a o ou pu signal) cu en a he in eg a ing capaci o C. The mo e challenging analog block is he OTA. I s inpu ol age ange mus be 0.5V bipola , so a linea ized a chi ec u e has o be chosen. We ha e employed he ci cui epo ed in [5] which allows o inc ease he inpu linea ange by p ope ly designing M2 and M22 ansis o s. I s schema ic including he common-mode eedback ci cui is shown in Fig. 5. In o de o gua an y he linea i y o he OTA-C in eg a o , he selec ion o he ansconduc ance alue is ealized aken in o accoun he in eg a o capaci o alue, he OTA ou pu esis ance, and he in eg a ion ime. In he p oposed algo i hm, he inpu ol age a he in eg a o will be a s ep signal om ze o o he p esen inpu sample alue. So, conside ing an ideal in eg a o as illus a ed in Fig. 6, ansien ime e olu ion o he capaci o ol age can be desc ibed as, (6) The maximum alue o Vin should be VRe , ha in eg a ed in a T/2 pe iod o ime will gi e us he maximum ou pu ange. Fo a C=15pF, we ha e chose gm=0.338S. The co esponding ansis o sizes a e in Table 1. The linea ized OTA esponse is illus a ed in Fig. 7, whe e an 1Vpp inpu ange can be app ecia ed o a gm linea i y e o below 0.9%. Fo a eal, he ime cons an gi en by Rou C mus be dimensioned o p ese e he ou pu linea i y ange. Since we ha e a T/2 = 10s, and a 7.5ms ime cons an alue has been conside ed enough o wo k always in he linea egion. This leads o a Rou = 500MΩ o a C=15pF. 0T/2 T Vop ~ Vin Vop ~ V Re Vop INV OTA INV INV S in Sin Sin Sin b I e I e Vin+ Vin- V g ound + C- Vou MUX INV V1 V’1 V2 V’2 Vo+ Vo- RES es Vg ound INV OTA S e b V e + V e - V g ound MUX INV Fig. 3. In eg a o ou pu e olu ion in he p oponed algo i hm Table 1: T ansis o sizes o he OTA T ansis o [µm/µm] T ansis o [µm/µm] M1, M11 4/20 M5,M55,M9 6/2 M2, M22 2/64 M6, M10 20/5 M3, M33 20/5 M7 4/20 M4, M44 1.5/13.8 M8 1.5/13.8 Vo gmVin C --------------- ⋅ = Vdd = 3V Vg ound M9 M8 M7 M6M33M3 M1 M2 M22 M11 M44 M55M5 M4 Ibias = 500 nA M10 Vin + Vo- Vin- Vo+ Fig. 4. ADC analog blocks Vin V o gmC Vin + - 0 i i Vo Fig. 5. Schema ic o he OTA Fig. 6. Ideal s ep esponse o he linea ized OTA-C in eg a o P oceedings, XVII IMEKO Wo ld Cong ess, June 22 – 27, 2003, Dub o nik, C oa ia TC1 P oceedings, XVII IMEKO Wo ld Cong ess, June 22 – 27, 2003, Dub o nik, C oa ia TC1 P oceedings, XVII IMEKO Wo ld Cong ess, June 22 – 27, 2003, Dub o nik, C oa ia TC4 703 -0.5 0.5 i Vin [100mV/di ] I o [100nA/di ] The gene al block desc ip ions o he digi al con ol and p ocessing pa s comp ises wo 14bi s coun e s, and a mo e speci ic con ol block ha will no be desc ibed now. The inpu o hese blocks a e: he clock (clk), an ex e nal ese ( es_ex ), he numbe o bi s o he ADC (n) ha has been pa ame ized in he ange (2,13), and inally, he bi - s eam (b) om he compa a o ou pu . The ci cui s has been implemen ed using s anda d cell om a VHDL whole unc ion desc ip ion. 4. EXPERIMENTAL RESULTS A 0.8m CMOS p o o ype has been in eg a ed and es ed. I s layou spends a silicom a ea o 2265µm x 2012µm. The e has been pe o med a s a ic es o he expe imen al cha ac e iza ion o he ADC. The ans e unc ion and DNL and INL g aphics ob ained o 12b a e shown in Figu es 10 and 11 espec i ely o n=12 bi s, o an inpu signal o absolu e alue in he ange o 500mV, wi h VRe = 500mV, and wo king wi h a powe supply o 3V. An implici ad an age o con inuous ime implemen a ions is he good equency scaling beha iou since he clock d i es he con e sion ime bu no he ADC ope a ion. This is illus a ed in Fig. 12, whe e he pe o mance o he same p o o ype es ed a 2MHz clock equency is shown. Coun e 1 Con ol Coun e 2 clk es b n clk es_ex clk es Ncon ce ud S in Sin S e Q es con 1 Vin [150mV/di ] Code [N] Fig. 7. Io e sus Vin linea ized OTA cha ac e ic ic Fig. 9. Pho og aph o he ADC DNL INL 0-1024-2048 20481024 Code lsb 0 -0.5 -1 -1.5 0.5 1 1.5 0-1024-2048 20481024 lsb 0.4 0.2 0 -0.2 0.6 0.8 1.0 1.2 1.4 -0.4 Fig. 10. Expe imen al ans e unc ion o n=12bi s and VRe = 500mV. Fig. 8. Digi al blocks in ol ed in he ADC Fig. 11. DNL and INL o n=12b, VRe =500mV and c=50kHz. P oceedings, XVII IMEKO Wo ld Cong ess, June 22 – 27, 2003, Dub o nik, C oa ia TC1 P oceedings, XVII IMEKO Wo ld Cong ess, June 22 – 27, 2003, Dub o nik, C oa ia TC1 P oceedings, XVII IMEKO Wo ld Cong ess, June 22 – 27, 2003, Dub o nik, C oa ia TC4 704 0-1024-2048 20481024 Code 0-1024-2048 20481024 Code lsb 0 -0.5 -1 -1.5 0.5 1 1.5 lsb 0 -0.5 0.5 1.0 1.5 -1 DNL INL 5. CONCLUSION In his pape , he design o a i s o de Con inuous Time Analog o Digi al Con e e has been p esen ed. The p oposed analog o digi al con e sion algo i hm conside s i s con inuous- ime implemen a ion, educing he e o s de i ed om he ini e in eg a o ou pu esis ance. A silicon p o o ype has been in eg a ed o a 12-bi esolu ion. Tes esul s show a good ag eemen wi h he speci ied pe o mance and an excellen equency scaling pe o mance. REFERENCES [1] A. Yú e a, G. Lege , E. O. Rod iguez-Villegas, J. M. Muñoz, A. Rueda, A. I o a, R. Gomez, N. Nogue a and J. Aguiló: “An In eg a ed Ci cui o Tissue Impedance Measu ed”. P oc. o IEEE EMBS. USA, May 2002. [2] J. Robe , G. C. Temes, V. Valencic, R. Dessoula y and P. De al: “A 16-bi Low-Vol age CMOS A/D Con e e ”. IEEE J. o Solid-S a e Ci ., ol SC-22, n, Ap ., pp.157- 163.1987. [3] A. Yú e a and A. Rueda:“A S2I Fi s O de Inc emen al A/D Con e e ”. P oc. o IEE Pa -G: Ci cui s, de ices and sys em, ol. 145, nº2, pp. 78-84. 1998. [4] A. Habe li, P. Malco a i, H. Bal es, and F. Malobe i: “An Inc emen al A/D Con e e o Accu a e Vec o P obe Measu emen s”. P oc. o IEEE ISCAS. pp. 541-544. 1995. [5] F. K ummenache and N. Joehl, “A 4-Mhz CMOS con inuous- ime il e wi h on-chip au oma ic uning,” IEEE Jou nal o Solid-S a e Ci cui s, ol. SC-20, pp. 114-1121, Dec. 1985. Fig. 12. DNL and INL o n=12b, VRe =500mV and c=2MHz. [6] R. Doldan, A. Yú e a and A. Rueda: “ A Con inuous-Time Inc emen al Analog o Digi al Con e e ”. P oc. o he 15 h Symposium on In eg a ed Ci cui s and Sys ems Design. pp: 62-67. Po o Aleg e, B azil. Sep. 2002.. Au ho : Rica do Doldan, Albe o Yú e a and Ado ación Rueda. Ins i u o de Mic oelec ónica de Se illa (IMSE-CNM). Ed. CICA. A . Reina Me cedes s/n. 41012. Se illa. SPAIN. Phone: +34- 955056666.Fax:+34-955056686. emails:{ doldan,yu e a, ueda}@ imse.cnm.es. P oceedings, XVII IMEKO Wo ld Cong ess, June 22 – 27, 2003, Dub o nik, C oa ia TC1 P oceedings, XVII IMEKO Wo ld Cong ess, June 22 – 27, 2003, Dub o nik, C oa ia TC1 P oceedings, XVII IMEKO Wo ld Cong ess, June 22 – 27, 2003, Dub o nik, C oa ia TC4 705