A mismatch-insensitive high-accuracy high-speed continuous-time current comparator in low voltage CMOS

A Mismatch-Insensitive High-Accuracy High-speed Continuous-Time Current Comparator in Low Voltage CMOS R. del Rio-Fevnandez, G. Liiian-Cembrano, R. Dominguez-Castro and A. RodriguezVazquez Instituto de Microelectr6nica de Sevilla, Centro Nacional de Microelectr6nica, Avda. Reina Mercedes s/n, Edif. CICA, E-4 10 12 Sevilla Tel.: +34 5 4239923, FAX: +34 5 4231832, E-mail: [email protected] Abstract This paper presents a CMOS current comparator which emp ioys nonlinear feedback to obtain highaccuracy (down to 1.5pA) and high-speed for low input currents (8ns050nA). This structure is much faster for low currents (below 10pA) than other previous nonlinear feedback comparators [ 11, [2], [3], [4]. Particularly, when compared to the fastest current comparator reported up to now [4], the new one goes more that 100 times faster for 1nA current, with smaller area occupation and similar power consumption. In addition, the new comparator is virtually insensitive to mismatch and capable to operate with supply voltages as low as 1V. 1. Introduction Analog current-mode techniques are drawing strong attention today due to their potential application in the clesign of high-speed mixed-signal processing circuit:; in low voltage standard VLSI CMOS technologies [5]. Also current-mode circuits are natural candidates for image sensory information processing where current sensing and comparison is necessary. Current comparators are basic building blocks for nonlinear current-mode signal processing and analog to digital converters. The availability of large current ranges is an appealing feature for both fields. Also, efficient small current level detection is fundamental for high accuracy and high speed applications. Low level, high speed current detection is also required in different light and radiation sensing applications: i.e. y-detectors using wide band gap semiconductors [6], or controllability and reconfigurability issues in E-beam testing of integrated circuits [7]. For instance, in the latter the need arises to detect current levels as low as 1nA in afew ps. Subthreshold CMOS current mode massive computation architectures [8] also require efficient detection of low current levels for fast discriminating function evaluation. To highlight another application, current detection is also required in IDDQ VLSI testing approaches [9]. In recent years, many current comparator circuits have been proposed [ll, [21, [31, [41, [lo], [ill, [121. A possible classification of them is to distinguish between the ones where the input current is first sensed at a low impedance node (resistive input) and them amplified using a voltage gain mechanism, and the ones where the input current is sensed at a high impedance node (capacitive input). The firsts provide high speed for high current levels but are somewhat inaccurate; the seconds obtain enlarged resolution at the cost of increasing voltage excursions at the input node and consequently decreasing the operation speed [ 121. Another possible classification is to distinguish between the structures that use autozeroing techniques to attenuate offset or to reduce propagation delays by adding clock signal generation circuitry and the ones that work on asynchronous mode. In this paper we propose an asynchronous mode current comparator that uses nonlinear feedback to combine the advantages of capacitive-input and resistive-input architectures. Because the proposed circuit is offset insensitive by construction it does not require autozero for offset attenuation. We include also a comparative study with the operation of the current comparator which is claimed the fastest among all 111 0-7803-42~#-2/97/$10.00 0 1997 IEEE those reported to now [4]. 2. Circuit behaviour Fig. 1 shows the schematic of the so-called Current Switch Comparator, whose advantages for low input currents have been demonstrated in [l2]. The operation of this circuit involves two different re,' =ions. If a positive current flows towards the input node, and assuming null initial conditions (Vin = V,= E) transistors M, and Mp are OFF, therefore the equivalent impedance at the input node is capacitive and consequently the circuit exhibits a very high resolution (only limited by the leakage currents), the input current is integrated in the parasitic input capacitor (Gin) producing a continuous increase of the input voltage. The amplifier causes Vo to decrease faster than Vi, and so that Mp turn ON draining the input current and closing a negative feedback loop around the amplifier. It obtains a virtual ground at the amplifier input, thus fixing the voltage at the input node. A similar situation occurs for negative input current where M,l becomes ON. The transient evolution is dominated by the first operation mode (the capacitive input behaviour), and if we consider a single pole model for the amplifiers with a gain-bandwidth product (GB) and linear capacitors for their input and output nodes one obtains However, due to the parasitic capacitors between input and output nodes (CM) the transient response is slowed down even for an ideal amplifier; this behaviour is similar to the slew rate phenomena in Miller operational amplifiers. In the comparator of Fig. 1 the coupling capacitor is formed by the Cgs capacitors of Fig. I Current Switch Comparator Schematic. Mn and Mp, and eventually the intrinsical coupling capacitor of the amplifier. Due to C,, input and output nodes of the comparator are coupled, so that the transient response evolution follows a linear characteristic instead a quadratic law r 2 where c = CinCo + Cin C, + C,C, Note that in (1) the output voltage is directly proportional to the amplifier GB, and hence the faster the amplifier is the faster the current comparator solves. However in (2) this dependence is vanished. The response time can be calculated from (1) and (2) by making AV, (T,) = E,, , where EOH denotes the logic noise margin. T =-- C, 'in ; (C, = 0) T =-- C, 'in According to this formula, Fig.2 shows a comparison of the response time for the current switch comparator of Fig.1 with and without the coupling capacitor. We are assuming EoH=l V, typical capacitances values of Ci,=Co=50fF and g,=1001ul/v2 for the amplifier. For low current levels, it is seen that the comparator behaviour becomes severely degraded due to the coupling capacitor, even for low values of this capac1 Om , i In loop In 10n lOOn 1p l0cl 'U% 16, Fig. 2 Comparison time response ,for the current compurutor wirh and withour coupling capacitor: 112 itor. On the other hand, for large currents (in the order of tens of PAS) smaller times response are obtained in the coupled ccrrent comparator. For these high current levels a simple inverter features fast operation speed, with no feedback needed. To impro\re transient response of the current switch comparator for low input currents, circuit strategies are required to uncouple input and output nodes of the amplifier and hence, reducing the coupling capacitance. In order to achieve faster response times simple CMOS inverters are usually used as amplifiers. To avoid the ove1,lap capacitors influence cascode transistors could be used in the amplifier output node. Also, the feedback mechanism used to obtain the nonlinear driving-point characteristic should be modified to avoid MI, and M, Cg.? influence, so that using a source follower in the feedback loop must be avoided. The new comparator schematic is shown in Fig.3. The circuit hac; two operation zones. lf a positive current flows touards the input node, and assuming that the initial conditions are: transistors Mn and Mp are OFF, so that the equivalent impedance at the input node is capacitive (i.e., very large in DC) and consequently the circuits exhibits a very high resc'lution (only limited by the leakage currents), the input current is integrated in the input capacitor (Gin) and produce a continuous increase of the input voltage. The amplifier causes V, to decrease faster than Vi, increasing Vs.y for the transistor Mn and decreasing Vsg for M,.,, so that M,, is driven into the ON state anc! a negative feedback loop is created around the amplifier. It obtains virtual ground at the amplifier input, fixing the voltage at the input node. A similar situation occurs for negative currents, where MI, becomes ON. It Fix. 3 Curren,, Steering Comparator Schematic. This structure reduces response times of the Fig. 1 comparator. An improved around two orders of magnitude is observed with the comparator in [4] if we compare the worst cases (negative input currents). We can also obtain a symbolic expression for the response time parameter by transient analysis. If we consider an input current step at t=O from a negative overdrive level -J up to a positive overdrive level +J, the response time can be written as follows: Fig.4 shows the final schematic for the new current steering comparator. As it can be seen the amplifier that appears in Fig3 has been implemented by a CMOS inverter with two cascode transistors which avoid the capacitors between input and output nodes, so that the transient evolution presents a quadratic time dependence instead of a linear depcndencc, as occurs for the comparator in [4]. The response times simulation measures of the two comparators for a range of input currents are shown in Fig.5. We have considered the worst case, Vr, -L 2/o.8 1' 6/03 I '5 -1 I 7 T "n 1' 410.8 (b) Fig. 4 (a) New Current Conipururor fiir ES.? 0.8pn CMOS fechnolofiy.. (hi Biasing Circuirn. 113 13000 ID i.e. a step input current from a positive overdrive level +J to a negative overdrive level -J. The results show that the greatest speed improvement occurs for low input currents, and for less than lop4 the new comparator remains faster than the one in [4]. The quadratic time law predicted in (2) can be observed in Fig.6. It can be seen how this approach is suitable in order to describe the main transient evolution. It contrasts with the behaviour observed in Fig.7 where the slewrate phenomena governs the temporal response. The circuit which provides the wave-form in Fig.7 is the same as in Fig.4 but using the feedback scheme that appears in Fig. 1. A possible technique to improve comparison times is to reduce the voltage excursions at the amplifier output node. This approach was applied by the authors in [4] to the circuit in Fig.1. However it presents a very high sensitivity to mistmatch effects. In order to avoid the mistmatch influence the excursions on the output voltage must be larger than the expected maximum fluctuations due to mistmatch. .. -1 0: - -2.07 b) ; .......,.. .',... 1, ,I...\ ..... I ...................... I .........,.... I .... '...,, .............................. I Fig. 6 Response of the compararor in Fig.4 .for U 50nA input pulse. ............. - - ....>......,...,..... I ..... > ....,.....,...... 1 .... , ...... I , .. I , .. : 1.0" 200.0" 400.0n 600.0n SO0 On 0. t>me (1l"l Fig. 7 Response ofthe current switch comparator in Fig. I ,fiir U 50d input pulse. Fig.8 shows a comparative study by Monte Carlo analysis of the new and [4] comparators designed in the same technology (ES2 1.5pm). It is shown how the percentage of successful comparisons for [4] decreases as input current level becomes lower. However, for the new comparator this percentage becomes 100% as soon as the input current reaches the maximum offset level (<lSpA). In order to obtain the maximum improvements the comparator has finally been designed using ES2 0.8pm technology. Fig.9 illustrates the layout for the comparator and the biasing circuitry. The main characteristics of the new comparator are : - 5V power supply. - Input Current Offset lower than 1.2pA. - Maximum resolution in the order of few PA. - Maximum delay for a 50nA step input cur- - Maximum delay for a lpA step input current rent 8ns. 2ns. A NA! Fig 8 Sensirrviries of rhe New and [4] Comparator.7. 114 J/ Fig. I1 Low voltage ampl$er Fig. 9 Luyout ofthe comparator and the biasing circuitry. - Area consumption without bounding pads - Power consumption 2.5mW. 0.005rnm2. Fig. 10 shows a comparison between schematic and extracted response times. It can be observed how the extracted response times are twice slower than schematic times due to the parasitic effects. A careful layout must be developed in order to minimize the parasitic capacitor effects. Another important feature of this new structure is its capability for working at low voltage supplies. As it can be seen in Fig.4 the biasing circuitry requires whereas the CMOS amplifier need It allows xoper operation with a power supply below 3V. If i. lower power supply is needed the biasing circuitry should be modified, in this case (7) provides the minimum V~D value (lower than 2V). This comparator c,in operate even below this limit if the I Fig. 10 Compurison Between Schcmric and Extracted Delays. amplifier in Fig1 1 is used. In this case the new limit becomes around 1V. Fig. 12 shows the response times of the comparator in Fig.4 for two different rail-to-rail voltages. It can be observed how for low input current levels the maximum speed is obtained using a 3.3V rail-to-rail voltage. It is due to lower voltage excursions at the output node of the amplifier. 3. Conclusions An analysis of the transient evolution of nonlinear feedback current comparators demonstrates that its response time degrades significantly at low currents due to the influence of a Miller coupling capacitor. This can be partially overcome by reducing the voltage excursions, the price to be paid for this is a reduction of the circuit tolerance to mismatches, specially significant at low-voltage supplies. The comparator presented in this paper uses another strategy to obtain large operation speed without degrading the comparator resolution and keeping the comparator operation virtually mismatch-insensitive, even for voltage supplies as low as 1V. h 115 4. References [l] R. Dominguez Castro, A. Rodriguez Viizquez and J.L. Huertas: “Sobre el Disefio de Comparadores de Intensidad”. DiseAo de Circuitos Integrados 91, ISBN 84-87412-61-0, pp 61-66, Universidad de Cantabria 199 1. 121 R. Dominguez-Castro, A. Rodriguez-Viizquez, F. Medeiro and J.L. Huertas: “High-Resolution CMOS Current Comparators”. 1992 European Solid-state Circuits Conf, ISBN 87-984232-0-7, pp. 242-245, Kandrup 1992. [3] H. Traff “Novel Approach to High Speed CMOS Current Comparators”. Electronics Letters, Vol.28, No.3, pp. 310-312, 1992. [4] A.T.K.Tang, C.Toumazou: “High Performance CMOS Current Comparator”. Electronics Letters, Vo1.30, No.1, pp. 5-6, Jan. 1994. [5] C. Toumazou, E J. Lidgey and D. G. Haigh: “Analogue IC Design: The Current Mode Approach”. IEE Circuits and Systems, series 2, 1990. [6] P. Olmos et al: “Computer Simulations of the Behavior of the Partial Charge Collection Model in Thick HgI2 y-detectors”. Nuclear Inst. and Methods in Physics Research, A302, pp 91-104, 1991. [7] J. Madrenas and J. Cabestany: “E-Beam Detector Devices for IC Controllability”. Microelectronics Engineering 16, pp465-472, 1992. [SI A.G. Andreou et al: “Current-Mode Subthreshold MOS Circuits for Analog VLSI Neural Systems”. IEEE Trans. on Neural Networks, Vol. 2, pp 205213, March 1991. [9] J. Rius and J. Figueras: “Proportional BIC Sensor for Current Testing”. Journal of Electronic Testing, Vol. 3, pp 387-396, Dec. 1992. [ lO]G.Palmisano. 6. Palumbo, S. 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