Very wide range tunable CMOS/bipolar current mirrors with voltage clamped input

October 20, 1998 5:14 pm 1 Very Wide Range Tunable CMOS/Bipolar Current Mirrors with Voltage Clamped Input Teresa Serrano-Gotarredona1, Bernabé Linares-Barranco1, and Andreas G. Andreou2 1 National Microelectronics Center (CNM), Ed. CICA, Av. Reina Mercedes s/n, 41012 Sevilla, SPAIN, Phone: 34-5-4239923, Fax: 34-5-4231832, E-mail: [email protected] 2 Dept. of Electrical and Computer Engineering, The Johns Hopkins University, Baltimore, Maryland, USA Abstract In low power current mode signal processing circuits it is many times required to use current mirrors to replicate and amplify/attenuate current signals, and to clamp the voltage of nodes with high parasitic capacitances so that the smallest currents do not introduce unacceptable delays. The use of tunable active-input current mirrors would meet both requirements. In conventional active input current mirrors stability compensation is required. Furthermore, once stabilized, input current cannot be made arbitrarily small. In this paper we introduce two new active-input current mirrors that clamp their input node to a given voltage. One of them does not require compensation, while the other may require under some circumstances, but for both input current may take any value. The mirrors can operate with their transistors biased in strong inversion, weak inversion or even as CMOS compatible lateral bipolar devices. If biased in weak inversion or as lateral bipolars, the current mirror gain can be tuned over a very wide range. According to the experimental measurements provided in this paper, input current may spawn beyond nine decades, and current mirror gain can be tuned over 11 decades. As an application example a sinusoidal gm-C based VCO has been fabricated whose oscillation frequency could be tuned for over 7 decades between 74mHz and 1MHz. I. Introduction When using current mode signal processing VLSI circuits it is not unusual that a very wide range of current levels have to be handled. For example, when building low power silicon retinas, light intensity is directly and (approximately) linearly transformed into current [1]-[2]. Silicon retinas can sense up to six decades of light levels, which yields also six decades of current levels at the photoreceptors output. It is impractical to permit that this current would control directly the time constant of the complete system. This would make a silicon retina be fast for high ambient light, but six orders of magnitude slower for low ambient light. This is not realistic, and a way to speed up these delays is by clamping the voltages of those nodes with high parasitic capacitances. Since current mirrors are necessary elements for current mode signal processing circuits, a very compact solution is to use current mirrors that clamp their input voltages. These current mirrors are usually referred to as active input current mirrors [3]-[4]. In the next Section the conventional active input current mirror is analyzed and it is shown why it needs compensation, why compensation depends on the mirror input current, and why this current cannot be made arbitrarily small. In Section III two new source driven active input current mirror topologies are introduced and stability is analyzed. One of the mirrors does not require compensation and the other may require under some circumstances. However, for both structures, input current can be made arbitrarily small without rendering unstable behavior. Section IV provides some intuition Submitted to IEEE Transactions on Circuits and Systems, Part I on April 24, 1998. Revised version submitted on July 31, 1998. Accepted on September 4, 1998. Final version submitted on October 20, 1998. October 20, 1998 5:14 pm 2 regarding dynamic behavior of the mirrors. Section V shows how to make the mirrors to have a continuously adjustable gain tunable over a very large range. Section VI studies loading effects. In Section VII it is shown how to extend the mirroring operations to bipolar transistors using the CMOS compatible lateral bipolar transistors, and finally in Section VII experimental measurements are provided that show the input currents spawning beyond six decades and the current mirror gains being adjusted over 11 decades. As an application example, the first mirror is used to make a constant linear input range OTA whose transconductance is tunable for over 7 decades. This OTA is then used in a sinusoidal VCO whose oscillating frequency could be tuned from to . II. Conventional Active Input Current Mirror The conventional active-input current mirror [3] is shown in Fig. 1(a). By redrawing its input stage as shown in Fig. 1(b), one recognizes a standard (uncompensated) 2-stage CMOS operational amplifier [5], connected in a unity-gain negative feedback configuration. The first stage of the opamp is the differential input amplifier of Fig. 1(a), and the second (inverting) stage consists of transistor M1 and current source . It is well known that this structure needs compensation [5], and that the compensation circuitry depends on the value of the second stage bias current . Furthermore, it results impractical to compensate when has to be varied over many decades and reaches very low values. For the differential input voltage amplifier the OTA in Fig. 2(a) can be used. OTAs are compensated by their load capacitance . An OTA connected in unity gain feedback configuration (as in Fig. 2(b)) has the small signal equivalent circuit shown in Fig. 2(c), where element models the transconductance gain of the OTA and its output conductance. Transconductance gm-C 74mHz 1MHz Iin v1 v2 Cp M1 V CLAMP V CLAMP Iin v1 v2 M1M2 CpIo (a) v2 Cp M1 Iin v1 CA V CLAMP gm1v1go1 Cpa goa v2 (s) gm v1v2 gd1 C Cp (c) (b) (d) Fig. 1: Conventional active input current mirror, (a) circuit schematic representation, (b) input stage drawn as a 2-stage opamp, (c) small signal equivalent circuit for mirror input stage, (d) compensated circuit. Iin Iin Iin Cpa gms( ) goa October 20, 1998 5:14 pm 3 is frequency dependent because of the delay introduced by the parasitic capacitances of the OTA internal nodes. This delay can be modeled as [6] (1) where is the DC transconductance gain of the OTA and models its delay. This yields the following stability condition for the circuit in Fig. 2(c) (2) Using this model for the OTA with the stability condition of eq. (2), it is possible to analyze the stability for the circuit in Fig. 1(b), whose small signal equivalent circuit is shown in Fig. 1(c). Transistor is modeled by elements , and , while the OTA is modeled by , and the node parasitic capacitance . After straight forward analysis it is easy to see that, if eq. (2) is satisfied, imposing the condition (3) guarantees stability. But this requires, at least, that which imposes a lower bound on the value of (and ) in Fig. 1(b). In practice, the circuit is usually compensated as shown in Fig. 1(d) [3], by adding a unity gain voltage buffer and a compensation capacitor . Eq. (3) would change to (4) But again, cannot be made arbitrarily small. in vvin + bias V out v Cpa bias I (a) vout Cpa vin (b) goa vout gm(s)(vin-vout) pa C (c) Fig. 2: (a) OTA structure suitable for the differential input voltage amplifier.(b) Unity gain feedback configuration, and (c) small signal equivalent circuit. gms( ) gms( ) gma 1s ωa ------–     = gma ωa Cpa gma ωa --------- > M1 gm1 go1 Cgd1 gms( ) gma 1s/ωa –( )= goa v1 Cpa Cgd1gm1gma –( ) gm1gma ωa ------------------ > gm1gma > gm1 Iin CA gm1Cgd1CA +( ) gm1gma ωa ------------------ gmaCgd1 +> gm1 October 20, 1998 5:14 pm 4 The two new active input current mirror topologies introduced in this paper do not have this problem: (and consequently, ) can be made arbitrarily small. In the next Section these mirrors are introduced and analyzed. III. Two New Active Input Current Mirrors A. First Topology The first alternative circuit to the one in Fig. 1(a) is shown in Fig. 3(a), where the OTA output drives the source of transistor instead of its gate. The OTA must be able to sink twice the maximum expected value for , which imposes an important design constraint for the OTA: in Fig. 2(a) must be, at least, twice the maximum operation current of the mirror1. The mirror input stage can be redrawn as shown in Fig. 3(b), which can be considered to be a special two stage opamp connected in unity gain feedback configuration. Note that the second stage of this opamp is a positive gain voltage amplifier, as opposed to the case of Fig. 1(b). Neglecting body effect of transistor , the absolute gain value of this second stage would be identical to that of Fig. 1(b). Also note, that the input node of this second stage is the source of transistor which is a low impedance node. This makes the circuit of Fig. 1(b) to have a single dominant pole, and consequently its behavior is qualitatively similar to a single stage opamp in unity gain feedback configuration. To analyze the stability conditions for this circuit, let us resort to its small signal equivalent circuit, shown in Fig. 3(c). Its characteristics equation is 1. Eventually, special OTAs that operate in a type of class AB mode [7] could be used to optimize power consumption. gm1 Iin M1 Iin Ibias M1 M1 V CLAMP Iin v2 M1 v1 M2 CpIo (d) gmv 1 1 v2 (s) m goa gpa Co1 gp C v1 2 v (c) V CLAMP Iin v2 M1 v1 M2 V G Io Cp (a) Iin v2 Cp M1 v1 V G V CLAMP (b) Fig. 3: First new active input current mirror topology, (a) circuit schematic representation, (b) input stage drawn as a 2-stage opamp, (c) small signal equivalent circuit. (d) Second current mirror topology. October 20, 1998 5:14 pm 5 (5) Since the OTA is assumed to be compensated, eq. (2) is satisfied, and the last term for coefficient b in eq. (5) is positive. However, b might still become negative. The following condition guarantees a positive b coefficient (6) This can be achieved by either adding an extra capacitance at node or by making the OTA to have a smaller delay (larger ) or lower . Note that the right hand side of eq. (6) is an increasing function of . Consequently, once eq. (6) is satisfied for the maximum possible (maximum ) stability is guaranteed for any smaller value of (and ). If eq. (6) cannot be satisfied, another way to achieve compensation for this topology is by adding a compensation capacitor between nodes and in Fig. 3. This yields the following characteristics equation (7) If eq. (2) is satisfied, coefficient a is positive as well as the second term of coefficient b. Consequently, stability is guaranteed if (8) If the right hand side of eq. (8) is negative, is not necessary and eq. (6) results. If the right hand side of eq. (8) is positive, then should satisfy eq. (8) for the largest value of (or ). Once this is assured, eq. (8) remains valid for any smaller value of (or ). B. Second Topology Another alternative active input current mirror is the one shown in Fig. 3(d). Note that in this case transistor is connected as a diode around the negative feedback loop of the amplifier, and acts simply as a passive device. Therefore, if the differential voltage amplifier is already compensated for unity gain feedback, the circuit should always be stable. This can be verified by performing a similar analysis to that for the first topology. C. Discussion The stability analyses for both topologies are valid whether transistors and are biased in their weak or strong inversion regions of operation. This allows the current mirrors to operate for a as2bs c+ + 0= a CpCpa = b goa gm1 +( ) Cp gm1gma ωa ------------------– go1Cpa gma ωa ---------–       += c gm1gma =        Cp gmagm1 ωagoa gm1 +( ) ------------------------------------- > v2 ωa gma gm1 gm1 Iin gm1 Iin CA v1 v2 as2bs c+ + 0= a CpCpa CACpCpa gma ωa ---------–+       += b Cpgoa gm1 +( ) go1Cpa gma ωa ---------–       gma CA gm1 ωa ---------–       + += c gm1gma =        CAgm11 ωa ------ Cp gma ---------–       Cp goa gma --------- –> CA CA gm1 Iin gm1 Iin M1 M1 M2 October 20, 1998 5:14 pm 6 very wide range of currents: from values equal to junction leakage currents up to the maximum current the OTA might be able to sink. Also, care needs to be taken to avoid that the OTA output voltage reaches its minimum (or maximum, for p-type current mirrors) value by adjusting to a safe enough level. The stability advantages for these two new topologies with respect to the conventional one of Section II, come from the fact that the differential voltage amplifier is loaded by a low impedance node, which makes the whole circuit to behave similar to a single pole (or one-dominant pole) system. Although the Topology 1 current mirror might require stability compensation, it has certain advantages over the Topology 2 one, as will be seen throughout the paper: it is faster for very low currents and it can be operated in bipolar mode by simply rebiasing constant global voltages. IV. Transient Response A. First Topology The circumstances under which the current mirror will be slowest is when input current is smallest (in the to range). In these cases transistor is operating in weak inversion and it is safe to consider the OTA acting as an instantaneous device that does not introduce any delay. If this is the case, the large signal transient response of the circuit in Fig. 3(b) can be computed by modeling the mirror input stage as shown in Fig. 4(a) but with . If and model the OTA and is the current through transistor , straight forward analysis yields the following state equation (9) where is the OTA voltage gain. If changes in a step fashion from to , the solution for eq. (9) can be written as (10) where, (11) If we define as the delay time it takes for to reach , then (12) Note that if is sufficiently large can be reasonably small, even for low values of . As increases the circuit will respond faster and the delay introduced by the OTA will start to be appreciable. In this case, the circuit shown in Fig. 4(a) with can be used to analyze its transient response. The resulting state equation does not have an analytical solution, thus in order to obtain an estimation of the delay in the current mirror one can resort to its small signal equivalent circuit, and consider makes a “little” step. Neglecting the OTA internal delay1 (characterized by VCLAMP nA pA M1 Cpa 0= gma goa IM1IS1VG1v1 –( ) /nUT { }exp= M1 Iin IM1 Cp goaAv --------------I ˙M1Cp nUT Av ----------I ˙M1 IM1 -------- + += Avgma/goa = Iin rIc Ic IM1t( ) IcIM1t( )–[ ] 1ε+ ------------------------------------------- rIc IcrIc –[ ] 1ε+ ---------------------------------et/τ1 = τ1 CpnUT AvIc ----------------- ,εIc goanUT ------------------= = td1 IM1t( ) RIc td1τ1R r --- 1r– 1R– ------------    1ε+ ln= Av τ1 Ic Ic Cpa 0≠ Iin October 20, 1998 5:14 pm 7 ) the following characteristics equation (valid for weak and strong inversion) results for the circuit drawn in Fig. 3(c), (13) The roots for this equation are given by (14) If two complex poles result and the transient has an associated time constant of the order of . If the poles are real, the dominant time constant may range from (for high values of ) to (for small values of ). Note that for very small values of ( and ) it follows that and , and the resulting time constant is , as derived previously using the large signal first order model. On the other hand, for very large (and ) values is also small and a dominant first order dynamics results with time constant . Consequently, for both very small and very large there are no complex poles and the dynamics is dominated by a single real pole. The maximum value of is reached for (assuming ), and is . Therefore, if can be satisfied, no complex poles (and no ringing) will appear for the whole input current range. If a compensation capacitor is used, the resulting equation would be 1. The effect of might be included, although the main delay introduced by the OTA is given by loaded by and other loads. ωa gma Cpa oa gpa C v1 V G1 Iin v2 Cp M1 2CLAMP -V v ma g( ) (a) oa g 1 v pa C gs C1 M1 Iin v2 Cp 2CLAMP -V v ma g( ) (b) Fig. 4: Equivalent circuits for computing transient analysis if OTA delay cannot be neglected, for (a) first new topology and for (b) second new topology. ωa s2s τ3 ----- 1 τ1τa ----------+ + 0= 1 τ3 ----- goa gm1 + Cpa ----------------------- go1 Cp --------+= 1 τ1 ----- gm1Av Cp --------------- = 1 τa ----- goa Cpa --------- =          so1 2τ3 --------– 1 1 4 τ3 2 τ1τa ---------- –±= τ3 2/τ1τa1/4> 2τ3 2τ3 τ3 2/τ1τa τ1τa/τ3 τ3 2/τ1τa Iin gm10≈ go10≈ τ3 2/τ1τa1« τaτ3 ≈ τ1 Iin gm1 τ3 2/τ1τa τ1τa/τ3Cp/gma ≈ Iin Iin τ3 2/τ1τa gm1goa = gm1/Cpa go1/Cp » AvCpa/4Cp AvCp/Cpa < CA October 20, 1998 5:14 pm 8 (15) where and with a, b and c given by eq. (7). Again, the associated dominant time constant would take a value between and . For very small and very large there is a dominant real pole of time constant that produces a first order dynamics. For very small it results , while for very large it is . The maximum value is reached for , for which two real poles result both of similar time constants around . B. Second Topology For the current mirror of Fig. 3(d) similar analyses can be done. For very small input currents, such that the OTA can be considered to respond instantaneously, the following state equation results (assuming and ) (16) Consequently, eqs. (10)-(12) would also be valid for this mirror as long as is substituted by . If the OTA might no longer be considered to respond instantaneously, or if is not negligible with respect to , an estimation of the delays can be obtained from the small signal equivalent circuit of Fig. 3(d) with . Routine analysis yields the following characteristics equation (valid for weak and strong inversion) (17) Consequently, the settling of the mirror has a dominant time constant that can range between values of the order of and . For very small and very large values (and assuming ) it follows that and a dominant first order dynamics results with effective time constant . For very small this time constant is , while for very large it is . The maximum value for is reached for . Therefore, if can be satisfied no complex poles will appear. C. Simulations Extensive Hspice transient response simulations have been performed on both topology current mirrors to confirm the previous analyses. Sizes for transistors and were set to and the internal bias current for the OTA was . An input node capacitance of was considered and input current was changed in a step fashion from to . The value s2s τ3' ------ 1 τa' ------    2 + + 0= τ3'a/b= τa'( ) 2a/c= 2τ3' τ'a 2/τ3' Iin τ'a 2/τ3' Iin τ'a 2/τ3'τ1CA/gm1 +≈ Iin τ'a 2/τ3'Cp/gma ≈ 2τ3'/τa ( ) 2 gm1goa gmaCA/Cp +≈ 1/τ3' 2 goa/CAgma/Cp +( )= Cpa 0≈ Cgs10≈ Iin IM1 Cp goa Av1+( ) ------------------------------I ˙M1 CpnUT Av1+ -----------------I ˙M1 IM1 -------- + += Av Av1+ Cgs1 Cp ωa0= s2s τ4 ----- 1 τ5 2 -----+ + 0= 1 τ4 ----- Cgs1Cp + Ce 2 -----------------------goa Cpa Cp + Ce 2 ---------------------gm1 Cgs1 Ce 2 -----------gma + += 1 τ5 2 ----- gmagm1 Ce 2 ------------------ = Ce 2CpCgs1CpCpa Cgs1Cpa + +=          2τ4 τ5 2/τ4 Iin CpCpa Cgs1 ,» 2τ4/τ5 ( ) 21« τ5 2/τ4 Iin τ1Cgs1/gm1 + Iin Cp/gma 2τ4/τ5 ( ) 2Cgs1Cpa +( ) /Cgs1Cp/Av +( )= gm1goa gmaCgs1/Cp += AvCpa Cp < M1 M2 150µm5µm× 20µA Cp1pF= Ic 2Ic October 20, 1998 5:14 pm 9 of was swept logarithmically from to . The output of the current mirror was connected to a voltage source equal to . The current through this voltage source was time-normalized to , where is the time at which has reached 63.2% of its total excursion value (assuming a first-order-like response). Fig. 5(a) shows the simulated output waveforms, where the amplitude has also been normalized with respect to , (18) In Fig. 5(b), for the trace with circles, the corresponding values for as a function of are represented for Topology 1 with . As discussed previously in Section IV.A, for very small currents the time constant is inversely proportional to current level (see eq. (11)), while for large currents the time constant tends to settle to a constant value (see discussion after eq. (14)). For between and the mirror output current step response showed ringing (presence of complex conjugate poles), while outside this range no ringing is observed (absence of complex conjugate poles). This was also predicted by the theoretical discussion after eq. (14). Eventually, ringing could be reduced or suppressed by improving the circuit phase margin by adding the compensation capacitance mentioned in Section III.A. However, may increase the delays for the complete range of input currents. The same simulations were repeated for the second topology. The resulting values of as a function of are represented in Fig. 5(b) using the trace with asterisks. Again for very small currents the time constant is inversely proportional to current and tends to settle for large currents (as predicted in Section IV.B). Presence of complex conjugate poles was observed for between and , as anticipated by the discussion after eq. (17). Note that for the lower currents range the resulting values for are about twice than those for Topology 1. This is because for Topology 2 the input node capacitance includes now also the subthreshold gate-to-bulk capacitance of transistor . For gate oxide thickness and gate area this capacitance is [8]. Therefore, in this example, the effective Fig. 5: Transient Analyses Simulation Results. (a) Time and Amplitude Normalized Transient Responses for Topology 1 Current Mirror with Unity Gain, (b) Extracted values for τn for both Topologies with Unity Gain and Sweeping the Gain. (a) (b) 10−11 10−10 10−9 10−8 10−7 10−6 10−5 10−8 10−7 10−6 10−5 10−4 Iout τ n topology 1, gain=1 topology 2, gain=1 topology 1, Iin=10 nA topology 2, Iin=10 nA Ic 10pA 10µA VCLAMP 2.5V= Iot( ) Iot/τn ( ) τn Io Ic Iot/τn ( ) Ic – Ic ------------------------------- τn Ic CA0= Ic 2nA 100nA CA CA τn Ic Ic 10nA 100nA τn Cp Cgb M1 tox 10nm= A150 5µm2 ×= Cgb 0.4Aεox/tox 1.05pF= = Cp October 20, 1998 5:14 pm 16 For the fabricated prototype VCO the capacitor value is . When using conventional CMOS OTAs for sinusoidal VCOs, their frequency tuning range is limited to little more than one decade [6]. The reason is that for tuning the VCO frequency, OTA transconductances have to be changed. If the OTA transconductance is adjusted through its differential pair bias current then the linear range of the OTA is reduced as its transconductance (and ) is lowered. If a linear range above is desired, transconductance tuning is limited to little more than one decade. The transconductance of the OTA in Fig. 9 can be tuned while maintaining its current (and linear range) constant. The two top Topology-1 PMOS current mirrors are tuned simultaneously through control voltage and are able to change the OTA transconductance for over 7 decades. Fig. 10(b) shows the experimentally obtained relationship between oscillation frequency and control voltage of the sinusoidal VCO. The minimum frequency that could be measured was , while the maximum was . Fig. 11 shows the measured sinusoidal waveforms for these two limit situations. To show the effect of OTA linear input range degradation, let us resort to Fig. 12. Classically, the OTA transconductance is tuned by changing its differential pair tail bias current . Fig. 12(a) shows the measured curves for the OTA of Fig. 9 ( ) when using current for tuning and leaving constant. Fig. 12(b) shows the curves , which are the first derivatives of those in Fig. 12(a) normalized with respect to (defined as the slopes at for Fig. 12(a)). The widest bell-shape curve corresponds to the maximum and maximum . As is decreased the bells become narrower (less input range) until the differential pair transistors are fully biased in weak inversion and the linear input range remains constant (between one or two ). In Fig. 12(a) and Fig. 12(b) the largest measured transconductance is , while the minimum is . If instead of using to tune we use then the curves shown in Fig. 12(c) and Fig. 12(d) are measured. Fig. 12(c) shows and Fig. 12(d) shows . In Fig. 12(c) and Fig. 12(d) the largest measured transconductance is , while the minimum is . Note that now the OTA input range is maintained constant. As a result, the OTA behaves almost linearly from to which means that low distortion sinusoids of peak-to-peak amplitude can be obtained with the VCO of Fig. 10 for the whole frequency range, as can be seen in Fig. 11. Fig. 11: Measured VCO outputs for minimum (73.94mHz) and maximum (1.015MHz) frequencies. Vertical scale is 50mV/div and horizontal scales are 2s/div for left trace and 200ns/div for right trace. C10pF= gm-C Iss Iss 200mV Iss VG2 VG2 fmin 73.96mHz= fmax 1.015MHz= gm ISS Iout Vin ( ) /ISS Vin V+V- –= ISS VG2 I'out Vin ( ) /gm gm Vin 0= ISS gm ISS nUT gm30.0µA/V= gm60.4pA/V= ISS gm VG2 Iout Vin ( ) /Iout max I'out Vin ( ) /gm gm30.0µA/V= gm40.0pA/V= 100mV– 100mV+ 200mV October 20, 1998 5:14 pm 17 IX. Conclusions Two new active-input current mirror structures are introduced. The novelty resides in that the active amplifier drives transistor sources instead of gates. This allows the amplifier to be connected in a negative feedback loop configuration, instead of positive. The first proposed topology might require compensation, while the second does not need it. Both topologies behave much better from a stability point of view than the conventional active input current mirror. This is because the amplifier output is connected to a low impedance node. The consequence is that the mirrors remain stable for arbitrarily small operation currents, thus allowing current ranges of many decades. Experimental measurements reveal that the currents involved can vary over 9 decades, and that the gain of these current mirrors can be continuously tuned over 11 decades while maintaining 1% linearity error in the mirroring operation. The mirrors can be used either with their transistors biased as MOS or as CMOS compatible lateral bipolar devices. Experimental results have been provided. As an application example a sinusoidal VCO has been fabricated and tested. Its frequency could be continuously tuned for over 7 decades through a single control voltage. To our knowledge this has never been achieved before for CMOS sinusoidal VCOs. −0.2 −0.15 −0.1 −0.05 0 0.05 0.1 0.15 0.2 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Vin (Volts) gm (Normalized) −0.2 −0.15 −0.1 −0.05 0 0.05 0.1 0.15 0.2 −1 −0.8 −0.6 −0.4 −0.2 0 0.2 0.4 0.6 0.8 1 Vin (Volts) Iout (Normalized) −0.2 −0.15 −0.1 −0.05 0 0.05 0.1 0.15 0.2 −1 −0.8 −0.6 −0.4 −0.2 0 0.2 0.4 0.6 0.8 1 Vin (Volts) Iout (Normalized) −0.2 −0.15 −0.1 −0.05 0 0.05 0.1 0.15 0.2 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Vin (Volts) gm (Normalized) (a) (b) (c) (d) Fig. 12: Experimentally measured dependence of OTA linear input range on transconductance tuning. For differential pair tail bias current (ISS) tuning, linear range decreases as transconductance decreases: (a) normalized OTA output current (Iout/ISS) as a function of differential input voltage, (b) normalized first derivative of previous curve. For tuning through the top Topology-1 current mirrors: (c) normalized OTA output current, (d) normalized first derivative of previous curve. gm-C October 20, 1998 5:14 pm 18 X. Acknowledgements This work was partially supported by an ONR Multidisciplinary University Research Initiative (MURI) for Automated Vision and Sensing Systems N00014-95-1-0409. XI. References [1] Carver Mead, Analog VLSI and Neural Systems, Addison-Wesley, 1989. [2] A. G. Andreou, R. C. Meitzler, K. Strohbehn, and K. A. Boahen, “Analog VLSI Neuromorphic Image Acquisition and Pre-processing Systems,” Neural Networks, vol. 8, No. 7/8, pp. 13231347, 1995. [3] D. G. Nairn and A. T. Salama, “A Ratio-Independent Algorithmic Analog-to-Digital Converter Combining Current Mode and Dynamic Techniques,” IEEE Trans. Circ. & Syst., vol. 37, No. 3, pp. 319-325, March 1990. [4] T. Serrano and B. Linares-Barranco, “The Active-Input Regulated-Cascode Current Mirror,” IEEE Trans. Circ. & Syst. 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