A CMOS 0.8- µm transistor-only 1.63-MHz switched-current bandpass ΣΔ modulator for AM signal A/D conversion

1220 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 8, AUGUST 2000 A CMOS 0.8-  m T ansis o -Only 1.63-MHz Swi ched-Cu en Bandpass 61 Modula o o AM Signal A/D Con e sion José M. de la Rosa, Belén Pé ez-Ve dú, Rocío del Río, and Angel Rod íguez-Vázquez Abs ac —This pape p esen s a CMOS 0.8- m swi ched-cu - en (SI) ou h-o de bandpass 61 modula o (BP- 61 M) IC capable o handling signals up o 1.63 MHz wi h 10.5-bi esolu- ion and 60-mW powe consump ion om a 5-V supply ol age. This modula o is in ended o di ec A/D con e sion o na ow- band signals wi hin he comme cial AM band, om 540 kHz o 1.6 MHz. I s a chi ec u e is ob ained by applying a lowpass- o- bandpass ans o ma ion ( 1 2 ) o a 1-bi second-o de low-pass 61 modula o (LP- 61 M). The design o basic building blocksisbaseduponade ailedanalysiso hein luenceo SIe o s on he modula o pe o mance, ollowed by design op imiza ion. Memo y-cell e o s ha e been iden i ied as he dominan ones. In o de o a enua e hese e o s, ully di e en ial egula ed- olded cascode memo y cells a e employed. Measu emen s show a bes SNR peak o 65 dB o signals o 10-kHz bandwid h and an in e - media e equency (IF) o 1.63 MHz. A co ec noise-shaping il- e ing is achie ed wi h a sampling equency o up o 16 MHz. Index Te ms—Analog- o-digi al con e sion, bandpass sigma– del a modula ion, swi ched-cu en ci cui s. I. INTRODUCTION THE TREND owa d he ealiza ion o comple e mixed- signal sys ems on chip has mo i a ed he explo a ion o analog design echniques compa ible wi h s anda d digi al CMOS echnologies. This is he case o swi ched-cu en (SI) ci cui s [1], which du ing he las ew yea s ha e been explo ed o he cons uc ion o di e en analog unc ions, including il e ing and analog- o-digi al con e sion (ADC) [2]–[5]. Manyo he SI ADC’s epo ed in li e a u e use low-pass modula o (LP- M) a chi ec u es o handling audio- e- quency signals. Pa icula ly, a CMOS 0.9- m p o o ype ha ea u es 13-bi e ec i e esolu ion and 300–3400 Hz signal band using a single-loop second-o de modula o has been p esen ed in [2]. The use o SI ci cui s o design cascade LP- M’s capable o handling la ge ope a ing equencies has also been explo ed in [3];howe e , he achie ed equencies a e well below he MHz ange. Repo ed SI ADC’s o signal equency in he MHz ange employ a Nyquis - ype a chi ec- u e [4]–[5]. Speci ically, he CMOS 0.8- m con e e in [4] ea u es 8 bi a 7.5 MHz wi h 350-mW powe consump ion; while ha in [5], also in CMOS 0.8- m, ea u es 7.2 bi a 20 MHz and dissipa es 82.5 mW. This pape p esen s a CMOS 0.8- mSI modula o ci cui capable o handling signals up o 1.63 MHz wi h 10.5-bi esolu ion and 60-mW powe consump ion om a Manusc ip ecei ed Decembe 7, 1999; e ised Ma ch 23, 2000. This wo k was suppo ed by he Spanish CICYT P ojec TIC 97-0580. Theau ho sa ewi h heIns i u odeMic oelec ónicade Se illa,IMSE-CNM (CSIC),41012Se illa,Spain(e-mail:[email p o ec ed];[email p o ec ed]; [email p o ec ed]; [email p o ec ed]). Publishe I em Iden i ie S 0018-9200(00)06436-2. 5-V supply ol age. This modula o is o he bandpass ype (BP- M) and has been designed o handle na owband signals wi hin he comme cial AM band, om 540 kHz o 1600 MHz. The ad an ages o BP- M’s, as compa ed o wideband Nyquis - a e con e e s, o digi izing na owband signals ha e been discussed elsewhe e [6], and a numbe o s anda d CMOS swi ched-capaci o p o o ypes ha e been epo ed [7]–[8]. The SI BP- M in his pape ea u es a bes SNR peak o 65 dB o signals o 10-kHz bandwid h and an in e media e equency (IF) o 1.63 MHz. Co ec noise-shaping il e ing is achie ed wi h a sampling equency o up o 16 MHz, hus demons a ing he possibili y o using SI BP- M’s in na owband high- equency communica ion sys ems. Ci cui design is based upon a de ailed analysis o he in luence o SI e o s, ollowed by design op imiza ion. Memo y-cell e o s ha e been iden i ied as he dominan ones. Howe e , unlike LP- M’s, S I memo y cells [9] canno be employed o a enua e hese e o s because signals a e sampled a a a e close o he signal equency; hence hey change qui e signi ican ly du ing sampling, he eby des oying he SI pe o mance. Ins ead, ully di e en ial egula ed- olded cascode memo y cells a e employed o e o a enua ion in ou ci cui s. Ano he consequence o he high- equency ope a ion is he inc eased in luence o bonding-pad pa asi ics, which in ou ci cui is handled h ough he use o ully di e en ial cu en -mode bu e s [10]. Sec ion II o he pape desc ibes he modula o a chi ec u e. Sec ion III desc ibes he design p ocess o he memo y cell and ou lines o he modula o subci cui s. Sec ion IV p esen s expe - imen al esul s. Finally, conclusions a e gi en in Sec ion V. II. MODULATOR ARCHITECTURE Fig. 1 shows he block diag am o he modula o . I is a single-loop ou h-o de BP- M wi h a 1-bi quan ize . On he one hand, his choice ende s he modula o easy o unde - s and and simple o design. On he o he hand, such a simple a chi ec u e is capable o achie ing high esolu ion oge he wi h obus s able ope a ion; ac ually, 1-bi quan iza ion and ou h-o de il e ing su ices o accomplish he speci ica ions in ended in his pape . No e ha Fig. 1 is ob ained by applying a ans o ma ion o a single-loop second-o de LP- M. Such a ans o ma ion keeps he s abili y p ope ies o he la e , and hence allows us o exploi he knowledge al eady a ailable o he low-pass modula o [11] in o de o design he bandpass one—ano he eason o choosing such an a chi ec u e. Fig. 1 includes wo esona o s, esul ing om he ans o ma iono he in eg a o sin heLP- M, woaddi ionaldelayblocks,needed o achie e he equi ed delay in he eedback loop, and h ee 0018–9200/00$10.00 © 2000 IEEE IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 8, AUGUST 2000 1221 Fig. 1. Block diag am o he modula o . scaling ac o s. The alues o he la e ha e been op imized o ob ain simila signal anges o bo h esona o s, gi ing (1) Assuming ha he quan iza ion e o is modeled as whi e ad- di i e noise [6], he -domain ou pu can be exp essed as (2) whe e and ep esen hesignal ans e unc ion and he noise ans e unc ion, espec i ely, (3) By making , whe e is he sampling e- quency, i can be seen ha has 2 ansmission ze os a , and ha he il e ing a ound his equency is ac ually o he band-s op ype. The in-band quan iza ion noise powe can be calcula ed by in eg a ing he ou pu powe spec al densi y wi hin he signal bandwid h, as ollows: (4) whe e is he powe spec al densi y o he quan iza ion noise, is he quan iza ion s ep, is he signal bandwid h, and is he o e sampling a io. F om (4), and assuming ha he modula o inpu is a sinewa e o ampli ude , he signal- o-noise a io (SNR) and he dynamic ange (DR) a e gi en by SNR DR (5) This shows ha he modula o esolu ion inc eases wi h a a a e o abou 2.5-bi /oc a e. Howe e , such an ideal ea u e can only be achie ed p o ided ha he scaling coe icien s and he esona o ans e unc ions in Fig. 1 a e ealized wi hou e o s. Modeling o hese e o s and ci cui op imiza ion a e needed o cope wi h he SNR and DR deg ada ion obse ed in ac ual SI ci cui s. III. SWITCHED-CURRENT IMPLEMENTATION Fig. 2(a) shows he block diag am o he esona o s in Fig. 1. I consis s o a eedback cascade o wo lossless disc e e in e- g a o s (LDI).1Fig. 2(b) shows a concep ual SI ealiza ion o his esona o employing second gene a ion SI memo y cells. As shown in [1], he majo e o sou ces o SI memo y cells a e h ee, namely: conduc ance e o ( ep esen ed by pa am- e e ) due o ini e inpu /ou pu conduc ances, incomple e se - linge o ( ep esen edby ), andswi chcha geinjec ione o ( ep esen ed by ). Besides, he esona o beha io becomes deg aded by he ini e conduc ances [ and in Fig. 2(b)] o he cu en mi o s employed o ealize he scaling coe i- cien s. Thei associa ed e o s a e de ined espec i ely by (6) whe e is he inpu conduc ance o he memo y cells and is he on- esis ance o he s ee ing swi ches. The abo e-men ioned e o s modi y he noise- ans e unc- ion . Thus he ze os o his unc ion a e shi ed om hei nominal posi ions—loca ed a —deg ading noise shaping and making he in-band quan iza ion noise powe inc ease. As we demons a ed in [13], he dynamic ange o a ou h-o de BP- M deg aded by SI e o s is DR (7) whe e (8) No e ha SI e o s do no a ec DR in he same way, he la ges deg ada ionbeingp oducedby .Equa ion(7)wasused o ind he maximum alue o each e o in o de o ul ill digi al AM adio ecei e speci ica ions, i.e., DR 60 dB a 2.16 MHz 6.4 MHz a 10 kHz. This yields 0.25%, 0.35%, 0.5% and 1%. Modula o building blocks we e designed o sa is y hese condi ions as de- ailed in he nex sec ion. 1This s uc u e has been chosen because i keeps he poles inside he uni ci cleuponchanges due o e o so he eedback loopgain.Howe e ,as demon- s a ed in [12] o lowpass modula o s, i may happen ha uns able esona o s esul in s able modula o s. 1222 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 8, AUGUST 2000 Fig. 2. Implemen a ion o he esona o . a) Block diag am. b) Concep ual schema ic conside ing SI e o s. A. Design o he Memo y Cell and he Resona o A second gene a ion egula ed- olded-cascode (RFC) memo y cell [14] was used o educe . This cell inc eases he inpu conduc ance h ough he inco po a ion o a local eedback in hesignalpa h, hus educingbo h and .Fig.3shows heschema ico he ullydi e en ialRFCmemo ycellincluding he common-mode eedback ci cui (CMFB) (M ). The local eedback s age is o med by ansis o s M , he memo y ansis o sa eM and hecu en sou ce ansis o sa eM . The s ee ing swi ches a e pMOS while he memo y swi ches a e nMOS wi h minimum size; he la e include dummy de ices which, in combina ion wi h ully di e en ial ci cui y, a enua e .Al hough he ea eo he app oaches o educe ,weha eno used hem o di e en easons. Tha in [15] uses ze o- ol age swi ching o a enua e he signal-dependen componen o . Howe e , i s powe dissipa ion is penalized by he ampli ie employed oc ea e he i ualg ound.Theal e na i eisusing he so-calledS Imemo ycell[9].Howe e , hiscellisno wellsui ed o BP- M’s because he inpu signal is no s a iona y du ing hesamplingphasesinceisloca eda .Hence,unlessasam- pling-and-hold (S/H) is placed a he on end o he modula o , head an ageso using heS Imemo ycella edes oyed. Because o he local eedback, he memo y cell exhibi s hi d-o de dynamics wi h a single pole a (whe e is he small-signal ansconduc ance and is he ga e–sou ce capaci ance) and a pai o complex conjuga e poles whose alues depend on he ansconduc ances and he pa asi ic capaci ances o M and he s ee ing swi ches. Two addi ional MOSFET capaci o s, , a e connec ed o he memo y ansis o ga es (see Fig. 3) o c ea e a dominan pole a . Thus, can be con olled by sizing he memo y ansis o . These ex a capaci ances also educe he common-mode componen o . The memo y cell has been designed by using he ansis o - le el op imize epo ed in [11] o a ain he speci ica ions e- qui ed o AM digi al adio ecei e s and, a he same ime, op- imize he ade-o be ween speed and dynamic ange. The e- sul ing bias cu en s a e 212.6 A, 20 A and 2.8 pF ( ealized h ough a 36- m/36- m nMOS an- sis o ). Table I summa izes he simula ed pe o mance o he memo y cell. This able also includes he memo y-cell e o s. Thei alues a e low enough o achie e he a ge ed modula o esolu ion. On he o he hand, he in-band in eg a ed he mal noise is gi en by Sinc (9) whe e is he ac iono heclockpe iod du ingwhich he noise is being sampled, Sinc is he sample-and-hold ans e unc ion, and is he equi alen noise bandwid h. Assuming ha he e e ence cu en le el o he digi al- o-analog con e e (DAC) is , he he mal dy- namic ange o he cell is DR . In ou design, 100 A, and he wo s case is ob ained o he minimum AM sampling equency, MHz, gi ing DR 86 dB, which clea ly does no limi he pe o mance o he modula o . The SI esona o is implemen ed by eplacing he memo y cells in Fig. 2(b) by Fig. 3. The scaling s ages a e ealized h ough simple cu en mi o s. No e ha he equi ed gain in e sion is s aigh o wa d because o he ully di e en ial s uc u es. Cu en s ee ing swi ches ( ealized h ough pMOS ansis o s) a e sized such ha , which bounds IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 8, AUGUST 2000 1223 Fig. 3. Schema ic o he memo y cell. TABLE I SIMULATED PERFORMANCE (HSPICE) OF THE MEMORY CELL and acco ding o AM digi al adio ecei e equi emen s. B. O he Modula o Subci cui s O he building blocks o he modula o in Fig. 1 a e he quan- ize and he DAC. The 1-bi quan ize is made up o a egene - a i e la ch [16] and a NOR lip- lop which main ains he ou pu alue in he phase in which he esona o s a e ed back. A as compa ison is ob ained wi h low inpu -cu en le els. Layou ex ac ed simula ions show 4% hys e esis—which is no p ob- lema icbecause hepowe o he in-bandnoise emains i ually unchanged o hys e esis as la ge as 10% o he ull-scale con- e e inpu [11]. The 1-bi DAC used in he modula o consis s o a cu en sou ce con olled by he compa a o ou pu [3]. A s acked-cas- code cu en mi o was chosen because i esembles he s uc- u e o he memo y cell. The di e en ial ou pu cu en , wi h alues 50 A , change he low di ec ion depending on he compa a o ou pu . In addi ion o he men ioned blocks, o he ci cui s ha e been included o p ac ical easons. On he one hand, a ully di e en- ial cu en -mode bu e has been inco po a ed a he on end o he modula o [10]. This bu e is used o isola e he on-chip ci cui y om he pa asi ic ime cons an s a he chip inpu pads, hus allowing us o ake ull ad an age o he speed capabili ies o SI ci cui s. Apa om his unc ion, his ci cui also con e s he single-ended ex e nal inpu ol age in o a ully di e en ial cu en h ough he use o an ex e nal esis ance. On he o he hand, we ha e included an in e nal clock phase gene a o ha p o ides a 4–phase clock diag am in o de o a oid ansien cu en spikes. Thus, o e lapping clock phases (and ) a e used o cu en -s ee ing swi ches and nono e lapping clock phases ( and ) a e used o memo y swi ches (see Fig. 3). IV. EXPERIMENTAL RESULTS The ou h-o de SI BP- M was ab ica ed in a CMOS 0.8- m double-me al single-poly echnology. Fig. 4 shows he mic opho og aph o he modula o chip. I occupies an ac i e a ea o 0.48 mm and consumes 60 mW om a 5-V powe supply. Fo es ing pu poses, he modula o chip has been a ached o a wo-laye PCB, which has been designed ollowing he indica ions in [17]. The inpu is applied using he HP3341A single-ended sinusoidal signal sou ce wi h an o -chip esis o ( o V/I con e sion) connec ed o he inpu pad and hen o he on-chip cu en bu e . The ou pu bi s eams we e cap u ed wi h he HP82000 da a sys em. Kaise 20)-windowed 32768-poin FFT’swe epe o medon eacho hose bi s eams using MATLAB [18]. 1224 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 8, AUGUST 2000 Fig. 4. Mic opho og aph o he modula o . Fig. 5. Measu ed modula o ou pu spec um o a sinusoidal signal o 0 6 dB inpu le el and 1.63 MHz equency (6.67 MHz sampling equency). 0 dB ep esen s 6 50  A. Fig. 5 shows he measu ed modula o ou pu spec um o a sinusoidal inpu signal o 6 dB inpu le el2and 1.63 MHz equency—maximum equency in he AM ange—( 6dB a 1.63 MHz) wi h he sampling equency being 6.67 MHz. A co ec noise shaping is ob ained. The p esence o ou -o -band spikes sugges ha he quan iza ion e o is no a whi e noise. Howe e , his beha io does no deg ade he modula o pe - o mance. To demons a e his, he ha monic dis o ion a he modula o ou pu has been measu ed a he maximum AM sam- pling equency o 6.67 MHz. The inpu signal consis ed o wo 7 dB ones a 1.62 MHz and 1.63 MHz. Fig. 6 shows he cen- al pa o he ou pu spec um. Two hi d-o de in e modula- ion p oduc s appea a bo h sides o he signals wi h ampli udes o 69.6 dB and 67 dB espec i ely, which co esponds o an o 60 dB. This esul s in an IP o 23 dB, which is low enough o digi al AM ecei e s. Fig. 7 shows se e al measu ed SNR e sus inpu le el cu es ob ained in a 10 kHz bandwid h (comme cial AM bandwid h). The measu emen s we e made wi h a single inpu one cen e ed a se e al AM equencies. No e ha , as a consequence o he la ge o e sampling, he bes SNR peak in he AM bandwid h is 65 dB o a 6.67 MHz sampling equency. 2Inpu le elisde inedas heinpu signalampli ude e e ed o heDACou pu le el, 6 I = 6 50  A (= 0 dB in Fig. 5). Fig. 6. Measu ed in e modula ion dis o ion. Fig. 7. Measu ed SNR e sus inpu le el o an inpu one wi h di e en AM IF equencies and B = 10 kHz. Table II summa izes he modula o pe o mance when clocked a 2, 4, and 6.67 MHz o he con e sion o comme cial AM signals cen e ed a 488, 976, and 1.63 MHz espec i ely. The DR is la ge han 57 dB in all he equency ange, in acco dance wi h he equi emen s o digi al AM ecei e s. The modula o also ope a es co ec ly a clock equencies abo eAM equencies.Asan illus a ion, Fig. 8 shows he mod- ula o ou pu spec um o a 6 dB a 3.8 MHz inpu one when clocked a 16 MHz. Obse e ha , as a consequence o he sampling equency inc ease, he se ling e o domina es he in-band e o powe , hus deg ading he pe o mance o he modula o . Finally, Fig. 9 compa es measu ed and p edic ed esul s. In o de o sepa a e he e ec o SI e o s, he hal -scale SNR (co - esponding o a 6 dB inpu le el signal) was ob ained o di - e en clock a es and a 50 kHz bandwid h. No e ha , o clock equencies below abou 3 MHz, he SNR inc eases wi h a a a e o abou 15 dB/oc a e, which co esponds o a dependence on as p edic ed in (7). This means ha he quan iza ion noise domina es he pe o mance o he modula o . Howe e , o clock equencies abo e 3 MHz, he SNR inc eases wi h a a a e o only 3 dB/oc a e, which e lec s a dependence on IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 8, AUGUST 2000 1225 TABLE II MEASURED PERFORMANCE OF THE MODULATOR Fig. 8. Measu ed modula o ou pu spec um o a 0 6 dB a 3.8 MHz inpu one when clocked a 16 MHz. Fig. 9. Measu ed and heo e ical Hal -Scale SNR e sus ob ained in a 50 kHz band cen e ed a = 4 . , and he e o e, whi e noise is he dominan e o sou ce. Fi- nally, o clock equenciesexceeding10MHz, hese linge o domina es and he noise powe in he signal band inc eases e y apidly, as p edic ed by heo y. Fig. 9 demons a es ha he dynamic ange o he p o o ype modula o is limi ed by ci cui noise, no by quan iza ion noise. Howe e ,asshowninSec ionIII, he mal noiseo memo ycells isbelow he measu ednoise loo . Apossibleexplana ion o he noise inc ease may be digi al swi ching noise which is coupled o sensi i e nodes ia he addi ional MOST capaci ance, , connec ed be ween he subs a e and he ga e o he memo y ansis o (see Fig. 3). V. CONCLUSIONS A cu en -mode bandpass modula o has been designed in a CMOS 0.8- m single-poly double-me al echnology. The ci cui has been ealized using swi ched-cu en ully di e - en ial egula ed- olded cascode cells. Measu emen s show DR > 57 dB wi hin a 10 kHz bandwid h o signals cen e ed on 540–1600 kHz (comme ical AM bandwid h). A co ec noise-shaping il e ing is shown o a sampling equency o up o 16 MHz, hus demons a ing he possibili y o use SI BP- M’s in na owband high equency communica ion sys ems. REFERENCES [1] C. Toumazou, J. B. Hughes, and N. C. Ba e sby, Eds., Swi ched-Cu - en s: An Analogue Technique o Digi al Technology. London, U.K.: Pe eg inus, 1993. [2] S. J. Daube and D. Vallancou , “A ansis o -only cu en -mode 61 modula o ,” IEEE J. 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