CMOS design of cellular APAPs and FPAPAPs: an overview

CMOS DESIGN OF CELLULAR APAPs and FPAPAPs: AN OVERVIEW A. RODRIGUEZ-VAZQUEZ~ Im ih io de Mic oelec dnica de Se illa-CNM-CSIC. A da. Reina Me cedes s/n 41012 Se illa (SPAIN). Tel.: 134 955056666, Fax: +34 955056686. E-mail: [email p o ec ed] CNN-based analogic isual mic op ocesso s ha e simila i ies wi h he so-called Single Ins uc ion Mul iple Da a sys ems ‘, al hough hey wo k di ec ly on analog signal ep e- sen a ions ob ained h ough embedded op ical senso s and hence do need nei he a on - end senso y plane no analog- o-digi al con e e s. The a chi ec u e o hese isual mic o- p ocesso s is illus a ed in Fig. 1 h ough wo p o o ype chips, namely: ACE4K and ACE16K ’. In bo h cases, as in o he ela ed chips *, he a chi ec u e includes a co e a ay o in e connec ed elemen a y p ocessing uni s, su ounded by a global ci cui y. This la e ci cui y is in ended o : Con ol and iming. * Add essing and bu e ing o he co e cells. Inpu lou pu . S o age o use -selec able ins uc ions (p og ams) o con ol he sequence o ope a- ions o he p ocessing co e. * S o age o use -selec able analogic p og amming pa ame e con igu a ions ( em- pla es). On he o he hand, he co e o in e connec ed p ocessing uni s embeds di e en unc- ions on a common silicon subs a e (see Fig. 2 o illus a ion pu poses), namely: - 2-D sensing. 2-D analoddigi al a ay p ocessing concu en wi h he signal sensing. - 2-D spa io- empo al p ocessing de e mined by local, ecep i e- ield-like p og am- mable in e connec ions. - 2-D memo y banks o concu en on-line.uploading and downloading o sho - e m analog and digi al da a. Se e al analogic isual mic op ocesso chips in di e en CMOS echnologies ha e been epo ed du ing he las ew yea s. Table 1 p esen s a summa y o some o he mos ele an da a o hose implemen a ions wi h a leas 20 x 20 pixels. Some columns co - espond o chips in ended o black and whi e inpu images, while o he s a e o chips which accep g ay scale inpu images. As wi h any o he analog p ocessing ci cui , igu es o me i abou pe o mance mus con empla e accu acy and a ea occupa ion in addi ion o speed and powe consump ion. Any compa ison mus e e o he numbe o ope a ions pe second and o he accu acy. The da a in he able highligh s he ollowing: - The e is a ade-o be ween a ea occupa ion (cell densi y) and accu acy, on he one hand, and speed o ope a ion and powe consump ion, on he o he . This ade-o is ypical o analog in eg a ed ci cui s ’. a. This o e iew is mos ly based on he wo k o Sewando Espejo, Ra ael Dominguez-Casm, Rica do Ca mona and Gus a o Li ih. and has been suppo ed by ESPRIT V P ojec IST-1999-19007 and by ONRNICOP G an N00014-00-10429 (POAC), and he Spanish ClCYT P ojec TIC-1999-0826. 16 Chan. Analog Da a Bus Add. Bus Con ol. 1 e 1. II 1 128 DA-AD Bank . Bus Mem. Con ol. 32b Digi al Da a Bus A chi ech es o halogic Visual Mic op ocesso Chips: (a) ACFAK 2 ,I.%) ACE16K 5 , Figu e 2. Illus a ing he embedding o di e en unc ional ea u es a he cox p ocessing a ay o isual mic op ocesso s. (a) Mic opho og aph o he ACE4K chip (le ipue), and concep ual ep esen- a ion o he dis ibu ed unc ions embedded in he co e a ay ( igh igu e); @) Layou o a p ocessing wi o he ACE16K showing he a eas occupied by he di e en unc ions ealized concu en ly by he co e my. * The e olu ion owa ds scaled-down echnologies epo s ad an ages in e ms o speed and cell densi y. Ac ually, he ACE16K chip has 128 X 128 esolu ion and is capable o ealizing sequences o 64 ins uc ions; using up o 32 di e en em- pla es (each empla e consis ing o 24 8-bi -coded analog p og amming alues) du - ing a sequence; loading and downloading ull-size g ay-scale images o and om he cache memo y, and ha ing always 8 ull-size images a ailable o usage du ing he low; wi h an in emal p ocessing ime o 160ns, and p o iding digi ally-coded ou pu images (ob ained wi h a ba e y o in emal A/D con e e s) wi h a downloading ime o 0.128ms. 510 Table I Summa y and compa ison o chip implemen a ions Tech. p 0.8 0.7 B PIX. Fo ma I1 I Weigh . Con inuous 8-b P og.e [+I1 c Ab I-s a e I-Inpu 4 LLMs Capaci o Memo y pe 5,5, Ih pe cell Speed Pho o Senso s. P og am. 8 Templ. i Memo y 15.8 GOPS 0.53 GOPS I 0.98 XPSla ea GOPSlmm2 II I 375 uWIcell -1 w Powe m, 22 I06 OPSIm2 XPSlPOW (op,J) 1.58 1010 3.5 109 22 Lines 20 Lines Bina y Bus Analog Bus Elec . U0 // 1 II I a.A=Analog, B=Bina y 0, D=DiI b.Only B/W esul s a e a ailable. c.7.7b Equi alen Accu acy. d.8b Eaui alen Accu ac . 8 0.5 48 x 48 B 2 Id2 ou Regis e s 9,9, 1 No 1 Templ. 5OnS 295 30hW (max.) 0.5 TOPS 64 GOPSlmm2 1.6 10” 48-b Bina y Bus I1 215 % 128x128 9, 1, 1, 1 7 Mul imode Senso 250pWIcell 18OpWlcell 1.2 W Chip 4W Chip 40 GOPS 0.19 TOPS GOPSlmm2 COPSlmm2 16 Lines e.I e e s o he numbe o bi s used o de me weigh pa ame e s. .A, B, and z mul iplie s. g.A and B mul iplie s a e he same. The chip uses a ime-mul iplexing scheme. h.C oss-shape neighou bood. 51 1 The capabili y o design cells wi h maximum densi y, speed and accu acy, and mini- mum a ea and powe consump ion elies basically on he exploi a ion o all unc ional ea- u es o e ed by he MOS ansis o . This is e y di e en om digi al design, in which only he swi ching capabili y o he MOS ansis o is exploi ed. The design o he en i ies which in e connec he cells (synapses) de ines one o he majo issues. In o de o do his, di e en possibili ies may be chosen a p io i. In all cases elec ical con ollabili y is p o- ided by de aul . Howe e , he di e en s a egies exhibi qui e a di e en pe o mance in he p esence o sys ema ic and andom e o sou ces, as well as a di e en incidence o he global signal ansmission e o s. Hence, ca e ul analysis and op imiza ion is needed o selec he bes app oach. Such analysis and op imiza ion a e needed o achie e he cell densi y and accu acy le els ea u ed by las gene a ion chips. The backg ound o such p ocedu es can be ound in li e a u e ’ ’. Re e ences 1. T. Roska and A. Rod iguez-Vbquez (Edi o s), Towa d he Visual Mic op ocesso . John Wiley & Sons L d., 2000. 2. G. Liiiln, P. Foldesy, S. Espejo, R. Dominguez-Cas o and A. Rod iguez-Vbquez, “A 0.5pm CMOS IO6 ansis o analog p og ammable a ay p ocesso o eal- ime image p ocessing”. P oc. o he 1999 Eu opean Solid-S a e Ci cui s Con e ence, pp. 358-361, Sep embe 1999. 3. R. Ca mona, P. Gamdo, R. Domingnez-Cas o, S. Espejo and A. Rod iguez-Vkquez, “Bio-inspi ed analog lsi design ealizes p og ammable complex spa io- empo al dynamics on a single chip”. P oc. o he 2002 Con e ence on Design and Tes in Eu ope, o appea . 4. J.C. Gealow and C.G. Sodini, “A pixel-pa allel image p ocesso using logic pi ch ma ched o dynamic memo y”. IEEE Jou nal o Solid-s a e Ci cui s, Vol. 34, pp. 83 1- 839, June 1999. 5. G. Liiiln, R. Dominguez-Cas o, S. Espejo and A. Rod iguez-Vbquez, “ACE16K An ad anced ocal-plane analog p og ammable a ay p ocesso ”. P oc. o he 2001 Eu opean Solid-S a e Ci cui s Con$, pp. 216-219, Villach (Aus ia), Sep embe 2001. 6. P. Kinge and M. S eyae , Analog VLSI In eg a ion o Massi e Pa allel P ocessing Sys ems. KIu e Academic Publishen, 1997. 7. R. Dominguez-Cas o e al., “A 0.8pn CMOS 2-D P og ammable mixed-signal ocal- plane a ay p ocesso wi h on-chip bina y imaging and ins uc ion s o age”. IEEE J. Solid-s a e Ci cui s, Vol. 32, pp. 1013-1026, 1997. 8. A. Paasio, A. Dawidziuk, K. Halonen and V. Pow, “Minimum size OSpm CMOS p og ammable 48 x 48 CNN es chip”. P oc. o he I997 Eu opean Con e ence on Ci cui Theo y and Design, pp.154-156, Budapes , Sep embe 1997. 9. A. Rod iguez-Vbquez, E. Roca, M. Delgado-Res i u o, S. Espejo and R. Dominguez- Cas o, “MOST-Based Design and Scaling o Synap ic In e connec ions in VLSI Analog A ay P ocessing Chips”. J. o VLSISignal P oc. Sys ems o Signal, Image and Video Technology, Vol. 23, pp. 239-266, Kluwe Academics No embe mecembe 1999.