Symbolic analysis tools-the state of the art

SYMBOLIC ANALYSIS TOOLS - THE STATE-OF-THE-ART Francisco V. Fern Andez and Angel Rodriguez-Vkzquez Dept. of Analog Circuit Design, Centro Nacional de Microelectrcjnica Edif. CICA, Avda. Reina Mercedes s/n, E-41012 Sevilla, SPAIN Phone: +34 5 4239923, FAX: +34 5 4231832, E-mail: [email protected] ABSTRACT This paper reviews the main last generation symbolic analyzers, comparing them in terms of functionality, pointing out also their shortcomings. The state-of-the-art in this field is also studied, pointing out directions for future research. 1. INTRODUCTION Circuit analysis is a basic milestone for efficient design of integrated circuits. Ever since powerful computers have been available, designers have developed programs to analyze circuits automatically. Today, all electrical engineering professionals and students use electrical simulators (such as HSPICE or ELDO). However, electrical simulators do not cover all the analysis tasks required for integrated circuit design. Essentially, they only serve to verzfy the performance of previously sized circuits. Among other things, designers must be able to predict the behavior of unsized circuits by tracing relationships among performance figures and design parameters. These relationships may be in the form of transfer functions, poles and zeros, root loci, parametric Bode plots, harmonic distortion coefficients, etc. Tools used to derive them automatically are called symbolic analyzers. The first generation of symbolic analyzers appeared in the late 60’s [l], where the basic analysis techniques were proposed. Most of these techniques are compiled in a recent book by P.M. Lin [2]. These tools did not spread on the designer community, partially due to their computational cost and because they did not fully fit the designer requirements. On the other hand, the lack of interest on custom analog ICs during the 70’s rendered symbolic analyzers secondary as compared to electrical simulations. This scenario changed during the 80’s with the increased economical interest on custom analog and mixed-signal ASICs. Symbolic analyzers were promptly recognized crucial tools to: provide insight and knowledge about analog circuits; support automatic behavioral modeling of analog integrated circuits; provide compiled models for automatic repetitive evaluations required for analog synthesis, among other applications [3], [4]. It resulted in the emergence of a new generation of tools during the late 80’s. Main features of this new generation have been approximation, post-processing and the extension to weakly non-linear circuit analysis. This paper summarizes some main contributions in these second generation tools, and compares the characteristics of many of them. 2. SYMBOLIC EXPRESSION APPROXIMATION Simplification in symbolic analysis is defined as the reduction of formula complexity by eliminating insignificant terms or sub-expressions, based on numerical estimates of the symbolic parameters. Simplification (or approximation) is required even for small circuits given the exponential increase of the expression length with the circuit size. Con0-7803-3073-0/96/$5 .OO ‘1996 IEEE 798 ventional simplification approaches first calculate the complete symbolic expression, and then simplifies it -- Simplification After Generation (SAG). Different versions of SAG have been implemented in modern symbolic analyzers: ISAAC [5], SSPICE [6] and ASAP [7] for expanded format expressions, and SYNAP [8] and ASAP [7] for nested format expressions. Differences arise in the control of errors and in the use of either a nominal point or a nominal interval to estimate the magnitude of the symbolic terms. Due to the necessity of generating complete expressions, SAG techniques are constrained to small and medium complexity circuits (below about 100 symbols). Larger circuits can be analyzed by using the newest approaches of simplifying during, or before to, the analysis stage. They are called Simplification Quring Generation (SDG) and Simplification Before Generation (SBG) techniques respectively. The rationale behind SDG techniques is that terms can be generated strictly in decreasing order of magnitude starting with the largest. The classical undirected tree enumeration method has demonstrated to be the most efficient to solve the underlying matroid intersection problem. This approach has been implemented with slight differences in RAINIER [9],[10] and ADAGIO [11],[12], the new tool evolved from ASAP and ISAAC. SBG can take place in the network under analysis, replacing those elements (or subcircuits), whose contribution (appropriately measured) to the network function is negligible, with a zero-admittance or zero-impedance element. These approximations are usually done when deriving network equations manually. However, except for the most trivial replacements, no automatic procedure has been reported yet. Reported approaches perform approximations directly on the network equations, either in graph [SI or matrix form [13], ~41. 3. POSTPROCESSING TOOLS These are basically intended for easier interpretation and manipulations of symbolic formulae, or to extract information from them. 3.1. Symbolic pole-zero extraction Poles and zeros are commonly used by analog designers. [ 151 introduced a technique for symbolic extraction of poles and zeros, based on heuristic approximations, similar to those performed by expert analog designers, e.g.: the root-splitting technique. This approach is also used in [16] which subsequently applies a symbolic Newton iteration to refine the polelzero locations obtained with the root-splitting technique. Consider, for example, the active feedforward compensated amplifier of Fig. 1. A symbolic extraction of the first pole/zero pair gives [ 151 : 3.4. Factorization and complexity reduction Even approximated expressions can be difficult to interpret due to the considerable size they have when calculated with enough accuracy in medium or large circuits. Factorization of common factors and cancellations of common factors in numerator and denominator are some of the needed capabilities to improve the interpretability without decreasing the accuracy. Many modern tools incorporate some primitive form of factorization. But more sophisticated mechanisms are still needed, for instance to eliminate the contribution of bias circuitry which usually affect equally numerator and denominator of most transfer functions. ? Figure 1 : Active feedforward compensated amplifier The interest of symbolic poles and zeros can be seen through this example. From (1) one can infers the value of the compensation capacitor that annuls the pole/zero mismatch and hence improves the high frequency behavior of the amplifier, Another extraction technique, reported in [ 171, extends the root splitting technique to cluster of poles or zeros which are quite apart from other clusters and calculates approximate expressions of the network function for a frequency range appropriate to the roots being calculated. 3.2. Graphical interfaces Some tools incorporate graphical interfaces for parametric representations of Bode diagrams or root locus. For illustration, Fig. 2 shows the graphical representation of the real part of poles and zeros of the voltage gain of Fig. 1 versus the value of Cpz. The value for which the pole/zero pair cancel is clearly seen. -io* -106 -104 -102 0 102 io4 io6 108 io10 Re(s) (radls) (log) Figure 2: Pole/zero location (real part) versus Cpz. 3.3. Sensitivity analysis Sensitivity analysis also plays a fundamental role in analog circuit design, specially in the calculation of the influence of component mismatches. The sensitivity of a circuit characterized by a symbolic system function H(s, x) can be obtained by simply deriving the system function with respect to the circuit parameter [ 181, [ 191, [20]. 4. AN OVERVIEW OF CURRENT TOOLS Many symbolic analyzers have evolved as members of this second generation. Exact comparison of their performance is difficult due to the lack of standard benchmarks for test circuits and platforms. Some key characteristics of main reported symbolic analyzers are compared in Table 1. A brief description of those analyzers follows. SCAPP [22] has been implemented at Iowa State University, in the framework of the development of a new methodology for symbolic analysis of large circuits. The program partitions the circuits hierarchically and symbolically analyzes each sub-circuit separately. Once the terminal blocks are analyzed, an inverse run of the partition process reconstructs the global system function. Since this analyzer uses an approach for large circuits based on hierarchical analysis, the system functions are given as a series of expressions rather than only one expression. Thus, the number of symbolic terms grows linearly, instead of exponentially, with the circuit size. SCAPP can be obtained for free via anonymous ftp at cpre 1 .ee.iastate.edu:/pub/scapp SCYMBAL and SYBILIN [23] are two simulators developed in CNET (Bagneux, France). A distinctive feature of SCYMBAL is that it was developed specifically for switchedcapacitor circuits. It allows not only continuous variables such as conductances, capacitors, etc., as symbolic parameters, but also boolean variables such as clock phases. On the other hand, SYBILIN is a continuous-time analyzer, specially conceived for the analysis of microwave circuits. These tools can be obtained from the authors on request. The price depends on the type of institution. SC [24] was developed at the University of Arizona, and conceived for classroom use, and thus developed for personal computers. It has a set of post-processing tools to ease interpretation of symbolic data: interactive numeric evaluation, numeric calculation of poles and zeros, and graphic representation. SC can be obtained from the authors with a $6 handling charge. SAPEC [25] was implemented at the University of Florence, also for PCs. One of its main characteristics is the group of applications developed around it, such as symbolic sensitivity analysis, transient analysis of electronic power circuits, calculation of testability index and fault diagnosis. SAPEC can be obtained for free from the author (e-mail: manetti@ ingfi 1 .ing.unifi.it) SSPICE [6] was developed at Michigan State University for both personal computers and mainframes. It incorporates a fast albeit not very accurate SAG technique. It is also capable of performing sensitivity analysis [19]. SSPICE is available from Instructional Media Center (Michigan State 799 University) with a cost of $5OO/copy and a license fee of $250/year. There is a limited student version for $25. SYNAP [8] was developed at ETH in Zurich (Switzerland). Together with ISAAC and ASAP, it was especially conceived for the modelling and design of analog integrated circuits and, more specifically, to be included on CAD frameworks for automatic design of analog integrated circuits. It incorporates encapsulated models for semiconductor devices and analog functional blocks, and can handle mismatches. Its newest version is capable of analyzing linear continuous-time and sample-data circuits, and also incorporates a primitive DC analysis capability. SAG techniques implemented in SYNAP use the concept of "lazy expansions", which performs approximations directly on the nested expressions. SYNAP is available from the author only to universities and non-profit research institutions. The first version of ISAAC [5] was developed in the Katholieke Universiteit Leuven. It was the first tool to incorporate the analysis of weakly nonlinear characteristics [26]. Like ASAP, SYNAP, and SSPICE it obtained simplified expressions using SAG techniques. It uses exact expressions in expanded format and eliminates those least significant terms whose accumulated sum remains small. ISAAC forms a fundamental part of the automatic design system ARIADNE [27]. ISAAC is available from the authors for a $400 handling charge. A Lucid Common Lisp license is required. Distribution to companies is done on a case by case basis. Currently it is being improved to include SDG and SBG, among other new features -- a cooperative project shared with ASAP. ASAP [28] was developed at the Centro Nacional de Microelectrhica in Sevilla (Spain). Like SSPICE, it runs on workstations and PCs. It shares with ISAAC the capability of performing groupings of elements and together with SYNAP, the explicit expression of mismatching. It calculates approximate poles and zeros symbolically. ASAP also incorporates a new SAG criteria which reduce errors by considering intervals of the symbolic parameters instead of fixed numeric values. Approximation with variation ranges has also been used to develop a reliable and precise criterion to simplify nested expressions resulting from hierarchical analysis. ASAP has been commercialized within the ELDO framework and is available through ANACAD-EES. SIFTER [ 141 and RAINIER [9] have been developed at the University of Washington at Seattle, and have mainly addressed the implementation of SBG and SDG techniques, as discussed in Section 2. RAINIER is available for free via anonymous ftp at twolf8.ee.washington.edu. 5. FUTURE DEVELOPMENTS One of the major challenges for future symbolic analyzers is increasing the complexity of circuits, while keeping the interpretability of results. A possible solution has been shown to be the application of hierarchical analysis techniques. These techniques are specially adequate for large circuits consisting of loosely coupled sub-blocks. For strongly connected circuits new SBG and SDG techniques are arising. The symbolic analysis of large networks has been the focus of intense attention in the last years, is still of interest today, and doubtless will continue to be of interest in the future. Table 1 shows that most tools are limited to the analysis of linear(ized) circuits. The first attempt to nonlinear analysis has been reported in [26] although limited to weak non-linearities. Reducing the actual symbolic analysis techniques to the study of linear or weakly nonlinear characteristics limits its practical applications. It can be assured that the possible future availability of large signal symbolic analysis techniques will suppose the full integration of these tools in automatic design and test systems, and in general, within any CAD environment. Regarding the time domain, the first attempts at time-domain symbolic simulation have been reported in [291. Together with the development of symbolic analysis techniques for non-traditional characteristics, and the new, more efficient algorithms, applications are being amplified within fields such as automatic design of analog integrated circuits. REFERENCES [ 11 P. M. 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