Nonlinear switched-current CMOS IC for random signal generation

Nonlinear switched-current CMOS IC for random signal generation M. Degaldo-Restituto, F. Medeiro, and A. RodriguezVazquez Indexing term: Switched-current circuits. Oscillators, Chaos signal generators ~~ A nonlinear switched<urrent circuit is presented that implements a chaotic algorithm for the generation of broadband, white analogue noise. The circuit has been fabricated in a double-metal, singleply 1.6~ CMOS technology and uses a novel, highly accurate CMOS circuit strategy to realise piecewise-linear characteristics in the current-mode domain. Measurements from the silicon prototype show a flat spectrum from DC to -30% of the clock frequency, for a clock frequency of 500kHz. Introduction: During the last few years, the study of chaotic behaviour displayed by nonlinear deterministic systems has attracted an extraordinary amount of research attention in many different scientific and technologic disciplines. Today, there is renewed engineering interest in the topic, based on the expectations created by advanced signal processing [l] and computation paradigms [2] that operate in the context of chaos. In particular, deterministic chaos provides excellent algorithms for designing improved electronic random signal generators for white [3] and coloured [4] analogue noise, and for random number time series [5]. It is based on the extreme sensitivity of chaotic equations to initial conditions, that render their solutions (consequently, the waveforms provided by electronic circuits that implement these equations) stochastic-like [6]. Few of the previously reported chaotic circuits are realisable in monolithic form. To the best of our knowledge, the only monolithic chaos-based noise generator reported in the literature realises a piecewise-linear (PWL) discrete-time system employing switchedcapacitor (SC) circuit techniques [3] which are very well suited to double-poly technologies. The circuit proposed in this Letter uses switched-current (SI) techniques for compatibility with standard, single-poly VLSI technologies. Measurements from a silicon prototype show faster operation than for the previously reported SC circuit [3], with much less silicon area occupation. Also, the proposed circuit is much simpler than digital noise generator structures composed of feedback shift register and lowpass filters, and provides fully aperiodic waveforms. PWL function scaled delay L I a b1557/11 Fig. 1 Analogue computer cuncepr for noi.se gtnerutiun algorithm. und nunlrnear Junction rharucreriwc a Analogue computer b Nonlinear function charactenstic Noise generation algorithm and circuit concept: Fig. la shows a block diagram of the proposed circuit, consisting of a PWL function transformation, shown in Fig. Ib, whose output is fed back to the input through a delay block with scaling parameter B. Thus, the following PWL discrete-time system is implemented Bin +A x, < 0 n=0,1,2, ... (1) Bx,-A z,>O X"C1 = { where X, denotes the value of x at the nth discrete time instance. We may consider eqn. 1 as a signal generator, providing a sequence (x.) for a given initial value x,. Parameter B determines the dynamic properties of the generated signal (also called orbit or trajectory), while parameter A acts only as a scale factor. For 1 s. B a 2, all steady-state orbits starting within interval J = [-A, A], are aperiodic and remain confined inside J; the system is in the 2190 EL ECTRO NI1 chaotic reghe. In this regime, slight differences in the initial conditions are greatly amplified in a few iterations: the system has a sensitive dependence on initial conditions [6]. Also, for B > v'(2). and with the exception of a countable set of periodic points, any arbitrarily small subioterval inside J is reached regardless of the initial point: the map is ergodic in the range B E [d(2,2)]. Actually, for B near 2, the distribution of iterates is very uniform, allowing map exploitation for improved random number and white noise generators. 4 4 Fig. 2 Scaled delay block and schematic diagram for realisation of PWL characteristic a Delay block b Schematic diagram Consider implementation of eqn. 1 in the current-mode domain, according to the concept of Fig. la. The scaled delay operation can be realised as a cascade of two track-and-hold switched-current stages, following the proposal by Hughes et al. [7]. Fig. 2a shows schematic diagrams for this block; parameter B is set by adjusting the geometry factors and bias current of the second track-and-hold stage. Fig. 2b, which consists of two current sources (realised in practice by current mirror output branches), four transistors and two digital inverters, shows a conceptual schematic diagram for the realisation of the PWL characteristics of Fig. Ib. Transistors Mcs. and Mcsp in Fig. 2b operate as a currentcontrolled-current-switch, and transistors M, and M, operate as voltage-controlled current switches. Any positive input current increases the input voltage, turning the M, device on, and since both devices in the current switch have the same gate voltage, Mcs. off. Simultaneously, the voltage at the second inverter output evolves to the high logic state, turning M, on and M, off. Thus, a current i, - A (obtained by KCL at node A',) is directed to the output node through transistor M,; the right-hand section of Fig. Ib is implemented in this manner. Similarly, negative input currents turn Mcs. and M, on, so that a current ih + A circulates through M, to the output node. Because current discrimination in the proposed circuit relies on the integration function performed at the input node, resolution is very high, and not influenced by transistor mismatches. Also, the feedback created by inverter IN, yields significant reduction of the dead zone exhibited by the driving point characteristics measured at the input node, that is proportional to (VTm + lVml)/K, where VTn and VTp are the threshold voltages for the transistors and K is the inverter DC gain. This is an appealing feature that enables reduction of interstage loading errors caused by finite equivalent MOS transistors Early voltages. CMOS prototype and experimental results: A prototype of the proposed circuit has been fabricated in a 1.6~ CMOS doublemetal single-poly n-well technology. In this prototype, the output transistor of the second track-and-hold stage is a binary-weighted transistor array, thus allowing digital control of parameter B. Also, some extra miscellaneous circuitry has been added to enable testing of the output current and the possibility to either open or close the feedback loop. Bias current I, for the delay stages was set to 50 pA with A = 20d. Slopes of the characteristic, which correspond to the B parameter in eqn. 1, were set to a value slightly less than 2, to avoid divergent orbits that may arise as a consequence of non-ideal effects, such as clock feedthrough. Total area occupation, including miscellaneous circuitry, amounts to 0.096mm'. The characteristics of Fig. 3 have been measured in the open loop configuration. Fig. 3a ranges from -20 to 20pA and shows the actual global PWL current transfer characteristics displayed by the prototype. Measured deviation from linearity in this range is less than 0.2%. Fig. 36 shows a detail of the global characteristics, ?S LETTERS 9th December 1993 Vol. 29 No. 25 -7 Authorized licensed use limited to: Universidad de Sevilla. Downloaded on March 26,2020 at 16:39:54 UTC from IEEE Xplore. Restrictions apply. Fig. 3 Measured characteristic of nonlinear block, and detail of discrimination function U Nonlinear block characteristic h Discrimination function where the input current changes from -21 to 21pA. It is intended to illustrate resolution achieved in the current discrimination which amounts to few picoamps. Fig. 4 Measured current waveform and power density spectrum a Current waveform b Power density spectrum Fig. 4 illustrates the closed loop operation of the prototype for a clock frequency of 500kHz. Fig. 4a shows the measured current waveform, and Fig. 4b its associated power density spectrum. The waveform of Fig. 4u shows that apparently coincident values of i, result in quite different values after few iterations, thereby confirming the expected unpredictable feature. Regarding Fig. 46, detailed measurements show a very flat spectrum from DC up to -30% of the clock frequency (deviation was less than 1 dB). It is useful to compare the performance of this circuit with that of the SC circuit reported previously for the same function [3]. Area occupation of the SI prototype is about one order of magnitude smaller than for the SC prototype. Also. for half the power consumption, the speed of the SI prototype is about three times greater than that obtained from the SC prototype. Ideas in the Letter are directly extensible to the design of chaotic neural circuits, because signal aggregation is easily achieved in current-mode, by simply rooting component currents to a common node. In particular, the Bernoulli circuit can be extended in this way to implement the chaotic neuron model proposed in [2], which models experimentally observed patterns of squid giant axons. Also, the circuit strategy used to implement the nonlinear function can be extended to support a systematic approach to high-accuracy function generation in the current domain. Such extensions will be reported in separate papers. 0 IEE 1993 Electronics Letters Online No: 19Y314ZY M. Degaldo-Restituto, F. Medeiro and A. Rodriguez-Vbzqucr (Centro Narional de Microelertronica-Universidad de Sevillu, Edificio CICA. (7 Tar@ s/n, 4/012-Sevilla, Spain) References 1 OPPENHEIM. A.v., WORNELL. G.W , ISABELLE. s H , and C!!DMO, K M : ‘Signal processing in the context of chaotic signals’. Proc. 1992 Int. Conf. on Acoustics, Speech and Signal Processing IV, 1992, pp. 117-120 AIHARA. K , TAKABE. T., and TOYODA, M.: ’Chaotic neural networks’, Phys. Left. A, 1990, 144, pp. 333-340 3 RODRIGUEZ-V~ZQUEZ, A., and DELGADO-RESTITUTO. M.: ‘Switched capacitor broadband noise generator for CMOS VLSI’. Electron. Lett., 1991, 27, pp. 1913-1915 4 MURCH. A.R., and BATES, R.H.T.: ‘Colored noise generation through deterministic chaos’, IE€€ Trans., 1990, CAS-37, pp. 608~-6l3 5 BERNSTEIN. G.M , and LIEBERMAN. M.A : ‘Secure random number generation using chaotic circuits’, IEEE Truns., 1990, CAS-37, pp. 1157-1 I64 I Septembrr 1993 2 6 DEVANEY. R.L.: ‘An introduction to chaotic dynamical systems’ (Benjamid Cummings, 1986) 7 HUGHES. I B., MACBETH. I.C, and PATIULLO, D.M.: ‘Switched current filters’, I€€ Proc. G, 1990, 137. (2), pp. 156162 Settling time reduction technique for high speed DACs 0. Kim. G. Kim and W. Kim Indexing 1erm.r: Digitd to unulogunur ronversion, Integrated circuits The ringing mechanism of the high impedance output node was analysed. To reduce this ringing, a new compensation circuit was developed and implemented in a standard CMOS process. This circuit can be programmed to cover a range of parameters. It is effective in minimising the settling time of a DAC. Introduction: There is an ever-increasing need for monolithic digital to analogue convertors (DACs) that have a resolution range of 8 - lobits. The segmentation architecture with current output [I] is widely used to obtain both high speed and high resolution using a standard CMOS technology. In this architecture, the output impedance needs to be high to obtain good linearity. This high output impedance coupled with the inductance of the packaging produces parasitic poles in the transfer function. These poles lead to ringing at the output node and an increase in the settling time. The ringing mechanism was analysed and a new output compensation circuit was developed. This circuit effectively eliminates the ringing at the output node. VI + +j&F{RL VO + j887/11 Fig. 1 Equivulent circuit of DAC output section ModeNing qf output pad: Fig. la shows the equivalent circuit of a DAC output section. Node i is the internal node of the device. Node o is the external node like that on the printed circuit board. R, is the output resistance of the device. C, is the equivalent capacitance associated with node i which includes the parasitic capacitance of the current switch output, metal layout and bonding pad. Lp is the parasitic inductance between node i and o [2]. It comprises the parasitic inductance of a bonding wire and the lead frame of the package. C, is the parasitic capacitance at node U, and R, is the termination resistor. The effective value of R, is 37.59 when the output node is doubly terminated with 759. Ideally, R, is m, C, and L, are 0. The step response at node o is given by where T = R,C,. From this, the worst case settling time to within 1i2 LSE of the target value is given by Yo = IRL(1 -e-+) (1) T,,,, = (n + 1)Tln2 (2) where n is the resolution of the device. If C, and L, are included, the transfer impedance Z(s) becomes (3) If R, >> R, and C, >> C,, The poles are ELECTRONICS LETTERS 9th December 1993 Vol. 29 No. 25 2191 Authorized licensed use limited to: Universidad de Sevilla. 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