A 2.5MHz 55dB Switched-Current BandPass ΣΔ Modulator for AM Signal Conversion

Abs ac - We p esen a Swi ched-Cu en (SI) ou h-o de bandpass Σ∆ mod- ula o IC p o o ype. I uses ully-di e en ial ci cui s in 0.8µm CMOS echnol- ogy o ob ain a Dynamic Range (DR) la ge han 55dB a 2.5MHz cen e equency wi h 30kHz bandwid h − in acco dance o he equi emen s o AM digi al ecei e s. The p o o ype inco po a es a single-ended o ully-di e en- ial cu en -mode bu e o es ing pu poses. The powe consump ion o he whole p o o ype (modula o plus bu e ) is 60mW om a 5V supply ol age. 1 In oduc ion P omp ed by he con enience o design mixed-signal chips using s anda d VLSI echnolo- gies, di e en au ho s ha e explo ed he applica ion o swi ched-cu en (SI) ci cui s o ana- log- o-digi al con e sion [1][4]. Mos o hei e o ha e been ocused on lowpass Σ∆ modula o s (Σ∆M) o equencies in he ange o audio [1][2]. A ew wo ks ha e also explo ed he use o SI ci cui s o la ge equencies [3][4]. Pa icula ly, [3] epo s a 4 h-o de lowpass (Σ∆M) ea u ing 7.2bi @625kHz wi h powe consump ion o 40mW in a 0.8µm CMOS echnology, while he highe equency has been ob ained using a Full-Nyquis con- e e ha ob ain [email p o ec ed] wi h 350mW, also in a 0.8µm CMOS echnology [4]. These la e ad ances show p omise o u u e applica ion o SI echniques in he a ea o communica- ions. Du ing he las ew yea s bandpass Σ∆Ms (BPΣ∆M) ha e been demons a ed as basic build- ing blocks o wi eless In e media e-F equency (IF) communica ions [5]. A numbe o CMOS p o o ypes ha e been epo ed using swi ched-capaci o (SC) ci cui s [6][7]. Howe e , e y li - le has s ill been done on he design o his kind o o e sampled modula o s using SI ci cui s [8]. This pape p esen s a SI ou h-o de BPΣ∆M IC o con e ing AM signals. This ci cui elies on he analysis o he majo sou ces o e o s which deg ade he pe o mance o SI ci - This wo k has been suppo ed by he Eu opean Union, unde ESPRIT P ojec 8795-AMFIS. A 2.5MHz 55dB Swi ched-Cu en BandPass Σ∆ Modula o o AM Signal Con e sion J.M. de la Rosa, B. Pé ez-Ve dú, F. Medei o, and A. Rod íguez-Vázquez Ins i u o de Mic oelec ónica de Se illa - CNM Edi icio CICA-CNM, A da. Reina Me cedes sn. 41012 - Se illa, Spain Tel: +34 5 4 23 99 23, Fax: +34 5 4 23 18 32 E-mail: [email p o ec ed] cui s o ob ain 9bi esolu ion up o 1.25MHz IF and 8bi a 2.5MHz wi h a maximum sampling e- quency o 10MHz, in CMOS 0.8µm echnology. I uses ully-di e en ial ci cui y ope a ing wi h 5V supply ol age and has a powe consump ion o 60mW − showing simila Powe /Speed igu es han o he s high- equency SI con e e s [3][4]. 2 Modula o A chi ec u e The modula o a chi ec u e has been ob ained by applying a z−1→−z−2 ans o ma ion o a 2nd- o de lowpass modula o . Because o his ans o ma ion, which keeps he s abili y p ope ies o he lowpass modula o , he in eg a o s become esona o s. The e a e se e al al e na i e s uc u es o ealize he esona o unc ion using SI ci cui s. The s uc u e shown in he inse o Fig.1 has been chosen because i keeps he poles in he uni ci cle upon changes due o misma ches o he esona- o ’s eedback coe icien s. Fig.1 shows he block diag am o he bandpass modula o , whe e he equi ed delay in he eedback loop has been ealized h ough wo addi ional delay blocks. Assuming as cus oma y o Σ∆ ci cui design ha he 1 bi quan ize can be modelled as an addi ional whi e noise sou ce wi h e ec i e gain o k, he ou pu is gi en as, (1) whe e X(z) is he modula o inpu signal, Y(z) is he modula o ou pu , and E(z) is he addi ional quan iza ion noise sou ce in he linea model. We see ha he ans e unc ion o he inpu is a dou- ble-delay; on he o he hand, he ans e unc ion o he quan iza ion noise has wo ansmission ze oes a s/4 whe e s is he sampling equency. This is he equi alen o he wo ze oes a DC obse ed in he lowpass p o o ype. The scaling ac o s ha e been op imized o ob ain simila dynamic ange o bo h esona o s, gi ing and . 3 Swi ched-Cu en Implemen a ion o he modula o Memo y Cell and In eg a o : The mos basic linea block is he memo y cell. We use a ully-di - e en ial second gene a ion egula ed- olded-cascode s uc u e which inc eases he inpu conduc- ance h ough he inco po a ion o a local eedback in he signal pa h, hus educing he e o due o ini e inpu conduc ance, εg [9]. Fig.2 shows he schema ic o he in eg a o including he common mode eedback ci cui (CMFB) (M16-24). I consis s o wo egula ed-ga e cascode [10] (RGC) g oups. The local eedback s age ( egula ed-cascode s age) is made up o M3-6; he memo y ansis- o s a e M1,2,1’,2’; he supply cu en mi o s a e M9-15,15’. The s ee ing swi ches a e PMOS while he memo y swi ches a e NMOS; he la e include dummy de ices o eed h ough a enua ion. Because o he eedback, he memo y cell exhibi s a hi d-o de dynamics wi h a single pole a and a pai o complex conjuga e poles whose alues depend on he ansconduc ances and he pa asi ic capaci ances o M3-6 and he s ee ing swi ches. Two ex a MOSFET connec ed o he memo y nodes (see Fig.2) a e used o c ea e a dominan pole a and, hus, o con- ol he e o due o incomple e se ling, εs, by p ope sizing o he memo y ansis o . These ex a capaci ances educe also he common-mode cha ge-injec ion e o , εq. The memo y cell has been designed using a ansis o -le el op imize [11] o a ain he speci ica- ions equi ed o AM digi al ecei e s and, a he same ime, op imize he ade-o be ween speed and dynamic ange, o 10MHz sampling equency. The esul ing bias cu en s a e: Ibias = 106.3µA, IbiasR = 120µA; on he o he hand, CH=1.4pF ( ealized h ough a 36µmx36µm ansis o ). The sim- ula ed alues o he e o s a e εg=0.06%, εq=0.3%, εs=0.3% − low enough o achie e he a ge ed modula o esolu ion. On he o he hand, he in-band in eg a ed he mal noise is -78.9 dB below he D/A e e ence cu en (50µA) − in compliance o he in ended SNR o he modula o (>8 bi ). Yz() z2–Xz() 1z2– +() 2 Ez()+= A RES2 nom ADAC2 nom ADAC1 nom –1== =A RES1 nom 12⁄= C gs12,g m 12, ⁄ C gs12,C H +()g m12, ⁄ 1-bi Quan ize and D/A: The 1-bi quan ize is made up o a egene a i e la ch [12] and an RS lip- lop ha main ains he ou pu alue du ing he acquisi ion phase -- he phase whe e he esona- o s a e eedback. Layou -ex ac ed simula ions shows 4% hys e esis −no p oblema ic because he powe o he in-band noise emains i ually unchanged o hys e esis as la ge as en pe cen o he ull-scale con e e inpu . The 1-bi D/A con e e used in he modula o consis s o a cu en sou ce con olled by he compa a o ou pu . Cu en Mode Bu e : We ha e inco po a ed a single-ended o ully-di e en ial high- equency cu en mode bu e a he on -end o he modula o . Fig. 3 shows he schema ic o his ci cui . This bu e is used o isola e he on-chip ci cui y om he pa asi ic ime cons an s a he chip inpu pads, hus allowing us o ake ull ad an age o he speed capabili ies o he cu en -mode ci cui y. The condi ion is he basic speci ica ion in he design o he bu e , which is in ended o 10MHz sampling equency. In addi ion, i s SNR mus be in compliance o he in ended SNR o he modula o (>8bi ). 4 Expe imen al Resul s Fig.4 shows he mic opho og aph o he modula o . I occupies 0.48mm2 ac i e a ea and con- sumes 60mW om a 5V powe supply. Fo es ing, he inpu is applied using he single-ended sinu- soidal signal sou ce HP3314A h ough an o -chip esis o ( o V/I con e sion) connec ed o he inpu pad and hen o he on-chip cu en bu e . The ou pu bi s eams we e cap u ed wi h he HP82000 da a acquisi ion equipmen . Hanning-windowed 32768-poin FFTs we e pe o med on each o hose bi s eams using MATLAB. Fig.5(a) shows a measu ed modula o ou pu spec um o a -9dB inpu [email p o ec ed] signal equency@10MHz sampling equency. Fig.5(b) shows a measu emen o he SNR igu e s. ela i e inpu ampli ude o a single one o 2.47MHz and an o e sampling a io o 167 (nominal alue co esponding o a signal bandwid h o 30kHz). The mea- su ed DR is la ge han 55dB(8.8bi ), which is illus a ed wi h a linea eg ession cu e ob ained p o- cessing he expe imen al SNR da a. The SNR-peak is 48dB (7.8bi ). Table 1 summa izes he modula o pe o mance o di e en sampling equencies and o e sampling a ios. I shows DR > 55dB up o 10MHz sampling equency − in acco dance o he equi emen s o AM digi al ecei e s. Summa izing, he esul s in his pape demons a e he possibili y o design high- equency SI ci - cui s wi h a ound 9bi p ecision h ough p ope con ol o he main e o s which deg ade he pe o - mance o his kind o ci cui s. Re e ences [1] N. Moeneclaey and A. Kaise , “A High-Resolu ion Cu en -Mode Sigma-Del a Modula o ”, P oceedings o he 22nd Eu opean Solid-S a ed Ci cui s Con e ence, ESSCIRC’96, pp. 260-263, Sep embe 1996. [2] M. B acey,W. Redman-Whi e, and J.B. Hughes, “A Swi ched-Cu en Σ∆ Con e e o Di ec Pho odiode In e ac- ing”, P oc. 1994 IEEE In . Symp. Ci cui s and Sys ems, pp. 287-290, May 1994. [3] N.Tan, “Fou h-O de SI del a-Sigma Modula o s o High-F equency Applica ions”, Elec on. Le .,Vol.31,pp. 333- 334, Ma ch 1995. [4] M.B acey, W.Redman-Whi e, J. Richa dson and J.B. Hughes, “A Full Nyquis 15MS/s 8-b Di e en ial Swi ched- Cu en A/D Con e e ”, IEEE Jou nal o Solid-S a e Ci cui s, Vol. 31, pp. 945-951, July 1996. [5] S.R. No swo hy, R. Sch eie , G.C. Temes, Del a-Sigma Con e e s. Theo y, Design and Simula ion. New Yo k, IEEE P ess, 1997. [6] A. Hai ape ian, “An 81-MHz IF Recei e in CMOS”, IEEE Jou nal o Solid-S a e Ci cui s, pp. 1981-1986, Dec. 1996. [7] A.K. Ong, B.A. Wooley, “A Two-Pa h Bandpass Σ∆ Modula o o Digi al IF Ex ac ion a 20MHz”, P oc. o he IEEE ISSCC’97, pp. 212-213, Feb ua y 1997. [8] J.M. de la Rosa, B. Pé ez-Ve dú, F. Medei o and A. Rod íguez-Vázquez,“CMOS Fully-Di e en ial BandPass Σ∆ Modula o Using Swi ched-Cu en Ci cui s”. Elec onics Le e s, Vol.32, pp.156-157, Feb ua y 1996. [9] C.Toumazou, J.B.Hughes, and N.C. Ba e sby, Swi ched-Cu en s: An Analogue Technique o Digi al Technology, CPADRin 1 inpu ⁄« London: Pe e Pe eg inus L d.,1993. [10] M. Goldenbe g, R. C oman, and T. S. Fiez, “Accu a e SI Fil e s Using RGC In eg a o s”, IEEE J. Solid-S a e Ci - cui s, Vol. 29, pp. 1388-1395, No embe 1994. [11] F.Medei o, B. Pé ez Ve dú, A. Rod íguez Vázquez,and J.L. Hue as, “A Ve ically-In eg a ed Tool o Au oma ed Design o Σ∆ Modula o s”. IEEE Jou nal o Solid-S a e Ci cui s, Vol. 30, pp. 762-772, July 1995. [12] M. B acey and W. Redman-Whi e, “Design Conside a ions o Cu en Domain Regene a i e Compa a o s”, P oc. o he IEE Ad anced A-D and D-A Con e sion Techniques and hei Applica ions, pp.65-70, July 1994. TABLE 1. Summa ized modula o pe o mance BW=30kHz BW=20kHz BW=15kHz BW=10kHz SNR-Peak (dB) 47 49 54 55 DR(dB) 55 58 64 64 IF F eq. (MHz) 2.47 1.23 Sampling F equency (MHz) 10 5 Fig. 5 a) Measu ed ou pu spec um o he modula o o -9 [email p o ec ed] inpu single one. b) Measu ed SNR o an inpu one o 2.47MHz@BW=30kHz@10MHz clock equency. Fig. 2 Schema ic o he In eg a o . b2 b3 b3 b1 b2 b3 b4 φ1φ1 V e b3 LR M1M2 M3M4 M5M6 M7M8 M9M10 M11 M12 M13 M15 M16 M17 M18 M19 M20 M21 M22 M23 M24 b4 CHCH b3 b1 φ2φ2 M’1M’2 M14 M’15 CHCH IbiasR 4Ibias Ibias z1– 1z 2– + ------------------ DA⁄ z1– Resona o 1 Resona o 2 Compa a o z1– 1z 2– + ------------------ DA⁄ z1– X(z) Y(z) ARES1 ARES2 ADAC1 ADAC2 z–12/– 1z 1– – ------------------ + -AFB z–12/– 1z 1– – ------------------ AF AF=1 AFB=2 Fig. 3 Cu en Mode Bu e . In eg a o 1 In eg a o 2Cu en Mode Bu e Clock In eg a o 3 In eg a o 4 1-bi D/A Compa a o & RS Flip-Flop Gene a o Fig. 4 Mic opho og aph o he Modula o . b)a) biaspbiasp iop biasp biasn ion iip iin DR>55dB Rela i e Ampli ude (dB) SNR (dB) Expe imen al Da a Linea Reg ession cu e SNR-Peak=7.8bi s -80.0 -60.0 -40.0 -20.0 0.0 -10.0 0.0 10.0 20.0 30.0 40.0 50.0 60.0 Fig. 1 Block Diag am o he Modula o . PAD Rin Iip Iin φ’2φ’2