A modular programmable CMOS analog fuzzy controller chip

A Modular Programmable CMOS Analog Fuzzy Controller Chip 0 IEEE Transactions on Circuits and Systems-II A Modular Programmable CMOS Analog Fuzzy Controller Chip Angel Rodríguez-Vázquez **, Rafael Navas *, Manuel Delgado-Restituto ** and Fernando Vidal-Verdú * *Dto. de Electrónica Universidad de Málaga Complejo Tecnológico, Campus de Teatinos, Málaga, SPAIN FAX: 34 5 2132782 Phone: 34 5 2133326 email: [email protected] **Instituto de Microelectrónica de Sevilla Centro Nacional de Microelectrónica-C.S.I.C. Edificio CICA-CNM, Avda. Reina Mercedes s/n, 41012-Sevilla, SPAIN FAX:: 34 5 4231832 Phone:: 34 5 4239923 email: [email protected].es ABSTRACT: We present a highly modular fuzzy inference analog CMOS chip architecture with on-chip digital programmability. This chip consists of the interconnection of parameterized instances of two different kind of blocks, namely label blocks and rule blocks. The architecture realizes a lattice partition of the universe of discourse, which at the hardware level means that the fuzzy labels associated to every input (realized by the label blocks) are shared among the rule blocks. This reduces the area and power consumption and is the key point for chip modularity. The proposed architecture is demonstrated through a 16-rule, two-input CMOS 1μm prototype which features an operation speed of 2.5Mflips (2.5 x 106 fuzzy inferences per second) with 8.6mW power consumption. Core area occupation of this protrotype is of only1.6mm2 including the digital control and memory circuitry used for programmability. Because of the architecture modularity the number of inputs and rules can be increased with hardly design effort. Acknowledgements: The works in this paper as been partially funded by the spanish C.I.C.Y.T under contract TIC96-1392-C02-02 (SIVA). Submitted to IEEE Trans. Circuits and Systems - II December 1997 A Modular Programmable CMOS Analog Fuzzy Controller Chip 1 IEEE Transactions on Circuits and Systems-II A Modular Programmable CMOS Analog Fuzzy Controller Chip I. INTRODUCTION Fuzzy controllers are used to map a multidimensional input signal into a scalar output , in accordance to a well-defined nonlinear relationship [1], (1) In control applications the inputs are usually called facts, the output action, and the mapping law surface response. For instance, a fuzzy controller for a washing machine must univocally set the water level (action) as a nonlinear function (surface response) of the clothes’ mass, the water impurity, and the time differential of impurity (facts) [2]. Fuzzy controllers employ the procedure of fuzzy logic inference [1] to construct the surface response. Some characteristic features of this procedure are [3][4]: • The surface response, which is a global model predicting the system behavior for any input, is obtained as a composition of local functions, each one predicting this behavior only for inputs comprised in a limited region of the input space. • These local functions represent insights on the system operation, and are described through inference rules of the type, IF AND AND ... THEN Consequent Action where are called fuzzy labels, and the consequent action assigns values to depending on the outcome of the combination of the antecedent clause statements. • The validity of the statements “IF xi is ” is continuously graded from 0 to 1; the actual grade of each statement is calculated by evaluating a nonlinear membership function which is different from zero only inside a subinterval of the whole interval. Because the statements involved in the fuzzy rules are in natural language, for instance “if the temperature is low”, this modeling technique is very well suited to capture and emulate human expertise. On the other hand, the continuous grading guarantees generalization of the local pieces of knowledge and hence, smooth surface responses. Finally, any change which affects only a limited region of the input space can be easily incorporated to the global model by just modifying the affected local functions − transparency property [3]. There are many fuzzy controller applications where the inputs and the output are analog signals [1][2]. The hardware required for these applications can be realized in two alternative ways. One employs analog circuitry only at A/D and D/A conversion interfaces, while the fuzzy processing is realized in digital domain by either general-purpose processors or dedicated ASICs [5]-[8]. The other realizes the fuzzy processing itself in the analog domain, and employs the digital circuitry for programmability and reconfigurability [9]. This paper contributes to the latter approach. Generally speaking, this approach is expected to feature larger operation speed, xx1x2…xM ,,{} T = y yfx()= x1 is A1k x2 is A2k xM is AMk Aik y Aik sik xi () xi A Modular Programmable CMOS Analog Fuzzy Controller Chip 2 IEEE Transactions on Circuits and Systems-II lower power consumption and smaller area occupation than the other [10][11]. These expectations are confirmed by the techniques presented in this paper, which fully exploit the functional capabilities of the MOS transistor (MOST) to realize the fuzzy operators with very simple circuitry. An inherent disadvantage of analog fuzzy controllers is limited precision. However, precision levels well below 10% − sufficient for many practical applications [2][9] − can be obtained by proper modeling of the errors [12], and sound circuit design techniques. Circuit blocks and design techniques for CMOS analog fuzzy controllers have been reported elsewhere [13]-[17]. Some of them have been demonstrated through actual monolithic chips, a fraction of which include programmability [15]-[17]. However, although precision is a weak point of the analog approach, most previous contributions do not consider the accuracy issue during the design phase. Whenever small transistors sizes are used − a technique inherited from digital IC design [15] − the output signal may become largely erroneous. These errors might be attenuated by post-fabrication tuning of some critical parameters, guided by learning processes [18]. Our chip overcomes this drawback by considering the accuracy issue during the design phase so that the desired performance can be anticipated inside specified error margins. Thus, our chip can be programmed in robust and transparent way. Despite the incorporation of accuracy considerations (hence, the avoidance of minimum transistors sizes) and although the demonstration prototype in this paper implements more rules than previous analog prototypes, it features much smaller values: [email protected]@16rules versus 570ns@44mW@9rules [16] and 160ns@550mW@13rules [17]. Programmability is also a quality of our proposal, which incorporates internal memory for serial digital programming of the rule consequents, and allows external analog programming of the membership functions. This is also advantageous as compared to [16], where the consequents values have to be learned using software models of the controller, and are not stored on-chip. Finally, the modular chip organization around two high level building blocks easily identified from the user and designer point of view, renders our chip architecture feasible for silicon compilation. II. CHIP ARCHITECTURE The chip realizes a type of fuzzy inference where the rule consequents are constant values, (2) These values are called singletons. As compared to the general case where the consequents include fuzzy labels [1], this type of fuzzy inference requires much less complex hardware [9], and, thus, less silicon area and less electrical power. Besides, it increases the transparency of the rules and, thus, eases the incorporation of programmability. On the other hand, different studies show that singleton fuzzy controllers are universal approximators; i.e. they are capable to approximate any surface response by properly choosing the rules and singletons [3][4]. Delay Power× IF x1 is A1k ()AND x2 is A2k ()AND…xM is AMk ()THEN yy k * =1kN≤≤ yk * A Modular Programmable CMOS Analog Fuzzy Controller Chip 3 IEEE Transactions on Circuits and Systems-II The set of membership functions constitutes the elementary nonlinearities from which the surface response of a fuzzy controller is built. Fig.1(a) shows a typical membership function shape [4] − described by three parameters: width ( ), measured as the length of the interval defined by the crossover points; center ( ), the central point of this interval; and slope ( ), the absolute value of the function slope at the crossover points. For a complete controller description, the surface response formula has to be generated from these elementary nonlinearities. Fig.1(b) illustrates the building procedure for a one-dimension, four-rules controller. Here, each rule involves only a fuzzy label, “IF THEN ”, whose validity is evaluated by using the corresponding membership function . If the actual input is at the center of the interval for the k-th membership function, then and the output is given by the value of the k-th singleton . At any point different from the centers of the membership function intervals, the output does not coincide with any of the singletons but it is interpolated by using the following formula, (3) where † 1. In this way a global response curve is built from the local data represented by the singletons, as Fig.1(b) illustrates. In the general multi-dimensional case, the surface response is interpolated from the singletons by using multi-dimensional membership functions , 1. This normalization precludes the output to take a value larger than the largest singleton at any point. sik xi () Figure 1: (a) One-dimensional membership function shape; (b) Illustrating function approximation through singleton fuzzy controllers; (c) Two-dimensional membership function. x 1 0.5 0 slope 2Δ ECE+ E- (b) (a) (c) Crossover Points 10wkx1x2 ,() x1x2 ζ– s1x() s2x() s3x() s4x() y4 *s4 y3 *s3 y1 *s1 y2 *s2 yx() 2Δ EC ζ x is Ak yy k * = skx() x Ik skx() 1= yy k * = yy 1 *s1 *x() y2 *s2 *x() y3 *s3 *x() y4 *s4 *x()+++= sk *sksk k14,= ∑ ⁄= wkx() A Modular Programmable CMOS Analog Fuzzy Controller Chip 4 IEEE Transactions on Circuits and Systems-II (4) where the function is evaluated by choosing the minimum † 2 among the values of the uni-dimensional membership functions associated to the k-th rule, (5) Fig.1(c) illustrates the build-up procedure and final shape of a two-dimensional membership function. The fuzzy controller chip architecture of Fig.2 realizes (4) for a system with inputs, fuzzy labels per input and rules. The architecture is composed of the interconnection of blocks of two different types, namely: label and rule. Each fuzzy label, say (the fuzzy label of the input), has an associated label block which evaluates the corresponding 2. This is the AND operator used in our chip. Other operators could be used as well [1]-[4]. yfx() yk *wkx() wkx() k1N,= ∑ ----------------------------- k1N,= ∑ == wkx() sik xi () wkx() min s1kx1 ()s2kx2 ()... sMk xM (),,,{}= s11 min inp min inp min inp LABEL BLOCK min output norm weighting w1w1*y1*w1* RULE BLOCK s1L min inp min inp min inp LABEL BLOCK norm weighting w2w2*y2*w2* RULE BLOCK min output norm weighting wNwN* yN*wN* RULE BLOCK x1 sM1 min inp min inp min inp LABEL BLOCK sML min inp min inp min inp LABEL BLOCK xM LM-1 LM-1 LM-1 LM-1 Σy N=LM M M x1 x2 A11 A12 A13 A21 A22 A23 A24 rule blocks label blocks A14 Figure 2: (a) Controller chip architecture; (b) Interconnection of label and rule blocks in the 1μm CMOS prototype. M A11 A1L AM1 AML (a) (b) label blocks min output M L NL M = Aij j-th i-th A Modular Programmable CMOS Analog Fuzzy Controller Chip 5 IEEE Transactions on Circuits and Systems-II membership function and generates replicas of the result. These replicas are processed in the “min inp” sub-blocks of the label blocks to make a first step towards the realization of the minimum. Each rule blocks combines inputs coming from the label blocks to: first, realize the second step of the minimum operation; second, evaluate the function ; and, third, multiply this function by its associated singleton to obtain . The final aggregation leading to (4) is performed at the output node. Fig.2(b) illustrates the interconnection of label and rule blocks for a system with two inputs and four fuzzy labels per input, as it is the case for the CMOS prototype presented in Section VI of this paper. Each box in the grid corresponds to a rule, has an associated singleton value, and is defined by two labels, one per input. Each label block is shared by four different rules. Because of this membership function sharing the architecture of Fig.2(a) can only generate lattice partitions (see Fig.3(a)); tree (Fig.3(b)) and scatter (Fig.3(c)) partitions [4] are not allowed. Generally speaking lattice partitions have the potential disadvantages of curse of dimensionality (the number of rules needed to perform a good approximation may become prohibitively large for large number of inputs) and inappropriate generalization (the partition granularity needed to approximate the function in a region of the input space may be inappropriate in other region). However, these potential disadvantages are not really significant for the type of problems which analog fuzzy controllers are intended for (medium-to-low complexity problems with low number of inputs and low number of rules). In this scenario, the architecture of Fig.2 features significant pros for hardware implementation, namely: • Area and power consumption required for the implementation of the rules antecedents is smaller than in the case of scatter and/or tree partitions. This is because the replication operation is much less areaand power-demanding than the membership function evaluation itself. • The whole architecture is highly modular and can be made to grow in very simple manner. Consequently, it is very well suited for design automation. • Programmability can be easily incorporated. Inputs to the chip are voltages for easier interfacing. On the other hand, the minimum and the normalization operations are realized in current domain because this requires much simpler circuitry that their voltage domain counterparts [19]. Thus, the inputs to the membership function circuits are voltages, while their outputs are currents. However, as already mentioned, the sij xi () LM1– M wk *x() yk *wk *x() A B C sxA xx A B C sxA3 sxA2 sxA1 (a) (b) (c) Figure 3: Examples of different types of input space partitions A Modular Programmable CMOS Analog Fuzzy Controller Chip 6 IEEE Transactions on Circuits and Systems-II label blocks do not directly deliver the membership function currents to the rule blocks; these currents are non-linearly preprocessed to produce intermediate output voltages. This simplifies the realization of the minimum operation in the rule block. Besides, transmitting these voltages (instead of the original currents) from the label to the rule blocks largely simplifies the interblock routing as these latter blocks have only one input node (instead of if currents were transmitted). III. LABEL BLOCK Each label block is driven by a component of the input voltage vector to, first, obtain a membership function current and, second, generate replicas of a voltage which is a nonlinear function of this current − a preprocessing step for the realization of the minimum operator in the rule blocks. This section describes first the membership function circuitry, then the complete minimum circuitry and, finally, outlines some major design considerations to reduce systematic errors in these circuits. III.A. Membership Function Circuitry A few alternative realizations of the pseudo-trapezoidal function shape of Fig.1(a) have been reported in literature [15][21]-[23]. One, see Fig.4(a), consists of a cascade of a linearized transconductor, to convert the input voltage into a current, and a current-mode nonlinear block to realize the pseudo-trapezoidal shape [20]; this latter block can be realized by using the techniques proposed in [15][21][22]. A drawback of this implementation is the extra area occupation and power consumption of the linearization circuitry. Also, because the transconductor cannot be linearized in the whole input range, some of this range is wasted. Fig.4(b) employs a slightly different strategy [23]. It uses two quasi-linear transconductance amplifiers to, at a first step, obtain monotone increasing and decreasing, respectively, currents around the crossover points; then, at a second step, these currents are first clipped and then aggregated in current domain. This strategy shares the drawbacks associated to linearization. However, as compared to Fig.4(a), it has the advantage that the centers and widths of the membership functions are controlled through voltages applied to high-input impedance nodes, which requires a simpler control circuitry and yields smaller loading errors in the application of the control signal. M xi sij xi () LM1– VGij + − gm Figure 4: Concepts for the realization of a transconductance membership function by current shaping: (a) Global shapping in current-mode [20]; (b) Partial shapping in current-mode [23] sij xi () front-end transconductor current-mode shaping + − + − xi EijEij+ gm gm sij xi () current-mode (a) (b) clipping and aggregation EijC xi A Modular Programmable CMOS Analog Fuzzy Controller Chip 7 IEEE Transactions on Circuits and Systems-II The membership function circuit used in our chip (see the shaded region at the left in Fig.5) approximates the shape of Fig.1(a) by using the nonlinear DC characteristics of a CMOS differential pair. This strategy is based on the work by Fattaruso and Meyer on CMOS function approximation [24], and was proposed for analog fuzzy design in [25]. Analysis of this circuit assuming equal differential pairs and using the square-law MOS transistor characteristics [26] obtains, (6) where is the large signal transconductance factor of the transistors in the differential pairs†3 and we assume that the membership function width is large enough to allow the output current reaching the logic unit value ( ) at the center. This membership function circuit shares the advantages of Fig.4(b) regarding control of the centers and widths through voltages applied to high-input impedance terminals, (7) 3. This equation shows the simplest case where the positive and negative input transistors are equal. VS−VS+ IQIQ xi sij sij+IB 2IQ+IB VCP2 MN2B MN2T maximum input cell membership function circuit complement circuitry VDP sij+IB Figure 5: The Label Block. −IQ IQ Eij-Eij+ left amplifier right amplifier Eij+ EijVGij 1VGij rVGij LM1– VD−VD+ MN1ij+ MN1ijMP1 MP2S MP2S MP2S MP2C MP2C MNQC VQ MNQ VS VCNQ IBQ MBQ MBCP2B VCP2 IBCP2 MBCP2T sij 0xiEij- –() IQ βN1 --------–<, IQ2βN1IQxiEij- –()1βN1 2IQ -------- xiEij- –() 2 –+ IQ βN1 --------–xiEij- –() IQ βN1 --------<<, 2IQotherwise, IQ2βN1IQxiEij+ –()1βN1 2IQ -------- xiEij- –() 2 –– IQ βN1 --------–xiEij+ –() IQ βN1 --------<<, 0xiEij+ –() IQ βN1 -------->, ⎩ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎨ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎧ = βN1 IQ 2Δij Eij+Eij- –=2EijC Eij+Eij- += A Modular Programmable CMOS Analog Fuzzy Controller Chip 8 IEEE Transactions on Circuits and Systems-II On the other hand, the slope at the crossover points is controlled by the large signal transconductance of the MOS transistor4, (8) The main advantage of this membership function circuit is that it does not require any linearization circuitry − why to linearize if the whole behavior is nonlinear?. Thus, it features minimum area occupation and power consumption, and full usage of the transconductor input dynamic range. On the other hand, it has been shown that the shape in (6) can actually realize the universal approximation feature, even when parasitics (systematic as well as random) are taken into account [18]. Considerations about the main non-idealities that influence the membership function circuitry, and the design strategies adopted to reduce their influence, are presented in subsequent sections. However, because they are influenced by the preprocessing circuitry used for the minimum operation, we will describe this circuitry first. III.B. Minimum Circuitry As mentioned in Section II, the minimum operation is realized in three steps: two in the label blocks and other in the rule block. However, for clarity, these three steps are described as a whole in this section. The whole operation of the minimum circuit is to select-and-propagate the minimum among a set of input currents . However, for convenience, we do not directly select the minimum among the input currents, but the maximum among their fuzzy complements, (9) where the current level corresponds to the logic “1”. This is based on the De Morgan’s law [39], (10) and takes advantage of the larger simplicity of the current-mode maximum circuitry [27]. Fig.6(a) shows conceptual circuits to evaluate the fuzzy complements by KCL, for positive (entering to) and negative (leaving from) currents. Regarding the maximum circuit itself, several alternatives appear which have to be evaluated bearing in mind the following major architectural features: • Neither constraints nor penalties should be imposed to the number of inputs since it coincides with the number of controller inputs. 4. Using the bias current to control the slope is not convenient because the bias current set the logical value “1”. ζij ζij 2IQβN1 = M sik xi () sik xi () 2IQsik xi ()–≡ 2IQ wkx() min s1kx1 ()s2kx2 ()... sMk xM (),,,{}max s1kx1 ()s2kx2 ()... sMk xM (),,,{}== A Modular Programmable CMOS Analog Fuzzy Controller Chip 15 IEEE Transactions on Circuits and Systems-II ers, while the normalization can be realized through a collective computation circuit with only two transistors per input; the chosen approach results, hence, in simpler circuits. Second, because the transmission path for the numerator and the denominator of (4) are not the same in Fig.7(b) this approach is more sensitive to mismatching. Third, the transient response of Fig.7(b) is largely-dependent on the signal level. Fourth, there is no simple way to compensate for the errors in the divider - the only way is using very accurate dividers. Fig.8 shows the schematics of the rule block where four different operations are realized: first, the current is generated as explained in Section III.B; second, this current is complemented and shifted to obtain ; third, a collective computation is carried out by all the rule blocks (they share the global nodes ANOR and BNOR) to realize the normalization operation; fourth, the resulting current is weighted by a digitally-controlled current mirror to obtain the shifted version of the k-th rule output current. IV.A. Normalization Circuitry Fig.9 shows the CMOS normalizer circuit used in our chip − based on a translinear BJT cirwkIB + wks wkIOS += MNSS ISS MNA ANOR BNOR VCN3 VG dk0dk1dk, P-1 yk VCNS minimum circuit output stage singleton weighting circuit normalization circuit unit cell VCP3 20S21S2P1– S wkIB + MN3S MN3C IC 2IQIB IOS ++= IC IG Figure 8: Rule Block MN4bk MN4tk MNSC MP3S MP3C wks wkIOS += wks *wk *IOS * += MN5S MN5C S Figure 9: Normalization circuit schematics Iss MNA ANOR BNOR MN4b1 MN4t1 wks wkIOS += wks *wk *IOS * += MN4bN MN4tN MN4bk MN4tk A Modular Programmable CMOS Analog Fuzzy Controller Chip 16 IEEE Transactions on Circuits and Systems-II cuit by Gilbert [34]. As a difference to the normalizers used in [9] [28], Fig.9 does not involve any feedback loop and, hence, features much faster dynamic response. Note that Fig.9 can be split into cells, one per each input-output pair, plus a little common circuitry consisting of the transistor NNA and the current source . Fig.8 exploits this modularity by incorporating one of these cells at each rule block. Assuming that the transistors operate in strong inversion, where the BJT translinear principle does not hold, the circuit is found to realize the following nonlinear transformation, (23) where the function is, (24) and, (25) The offset current is added to improve the dynamic behavior. Note from Fig.8 that it is related to the bias currents in the rule antecedent by . Thus, it can be introduced by just increasing the current without additional area cost, although it will be preserved in figures and equations to gain clarity. The circuit in Fig.9 exhibits the following features: a) the sum of all output currents is constant and equal to ; b) for each input, the input-output transformation is a soft monotonic one, i.e, the higher an input current, the higher the corresponding output current. Thus, the relative strengths of the different rule antecedents are preserved at the outputs − as required for defuzzification [1]-[4]. Hence, although this circuit does not realize the ideal normalization operation, it keeps the essential features needed for defuzzification; non-linearity is not problematic because the whole controller chip is highly nonlinear. Actually, system-level analysis shows that, despite this non-linearity, the normalization-plus-weighting defuzzification approach features smaller deviations from the linear interpolation than the ideal weightingplus-division structure [27]. IV.B. Design Considerations in the Normalization Circuit A first consideration refers to the input range of the normalization circuit when embedded into Fig.8. Consider first the common-mode range, where all input currents are equal. If they increase, transistors MN4bk evolve towards the ohmic region; on the other hand, if they decrease, N ISS wks *βN4t βN4b -----------wks 1ηws () wks --------------- + 2 = ηws () ηws () wks k ∑ N -------------------1 NI SS ´ wks k ∑ – ⎝⎠ ⎜⎟ ⎛⎞ wks k ∑ ⎝⎠ ⎜⎟ ⎛⎞ 2 -------------------------------------- +1– ⎝⎠ ⎜⎟ ⎜⎟ ⎜⎟ ⎜⎟ ⎜⎟ ⎜⎟ ⎛⎞ =ISS ´ βN4b βN4t -----------ISS = wk *wks *IOS * –= IOS *wks *IOS ()= IOS IOS IC 2IQIB ––= IC ISS A Modular Programmable CMOS Analog Fuzzy Controller Chip 17 IEEE Transactions on Circuits and Systems-II the transistors used in the current source evolve towards the ohmic region. Thus, the common-mode input range is given by, (26) where is the compliance limit for the current source and we have assumed that the threshold voltages of top (MN4tk) and bottom (MN4bk) transistors are approximately equal, because their sources are at similar voltage. The bottom limit in (26) is valid whenever , otherwise the real condition limit is zero. The wide range cascode current mirror enclosed in Fig.8 allows us to obtain a good common mode range (given by ) as well as good precision. Consider now the differential range; if one input current changes while the others are kept constants, the top transistor for the changing current will eventually drive all the current , and the other top transistors will be cut-off. The differential range is given by, (27) where we have considered that the set of fuzzy rules is consistent [39], i.e., when an input is maximum the remaining are zero. There are three main sources of systematic errors in Fig.8: the finite impedance of , the DC voltage mismatching among output nodes of the circuit core (shaded in Fig.9), and the DC voltage mismatching between input and output nodes of the output PMOS mirrors. The adopted cascode realization of makes the first negligible. On the other hand, because the top transistors are connected to low-impedance nodes, the second error is largely attenuated by the transconductances of the PMOSTs used at these nodes. Concerning the third error source, it can be minimized by inserting cascode transistors, as Fig.8 shows. The error is then given by, (28) which is minimized by proper choice of . Again, a particular signal value has to be selected to guide the choice of . Because most output branches drive a current value , such current level defines a good choice. Thus, is obtained from (28) for and , and it is generated in similar as already explained for Fig.6(f). With regard to the dynamic response, analysis recommends to scale the width of MNA as well as the value of proportionally to the number of normalizer inputs, i.e. rules in the controller, ISS VBnormΩVT0N –ISS NβN4t --------------+ 1 βN4b -----------N βNA ----------+ ---------------------------------------------------------------- 2 IOS –wk VDD VT0P –VT0N –ISS NβN4b ---------------– 1 βN4b -----------N βNA ----------+ --------------------------------------------------------------------------- 2 IOS –≤≤ VBnormΩ ISS VBnormΩVT0N ISS NβN4t ()⁄–≥ VBnormΩISS βNSS ⁄ISS βNSC ⁄+= ISS 0wkβN4b IOS βN4b -----------Iss βN4t ----------+ ⎝⎠ ⎜⎟ ⎛⎞ 2 IOS –≤≤ ISS ISS εwks * () 1 VAP3S --------------wks *VDD 2VT0P –wks * βP3S ----------–wks * βP3C -----------– VCP3 – ⎝⎠ ⎜⎟ ⎛⎞ = VCP3 VCP3 IOS * VCP3 ε0= wks *IOS * = ISS A Modular Programmable CMOS Analog Fuzzy Controller Chip 18 IEEE Transactions on Circuits and Systems-II in order to preserve the dynamic response as the complexity increases. IV.C. Singleton Weighting and Output Layer Fig.8 employs a digitally-controlled current-mirror (represented at the conceptual level in Fig.10(a)) to implement a programmable singleton value . As compared to analog-programmed current mirrors [38][40], the digital approach is preferred because it is more robust and accurate, compatible with standard memory circuits and directly controllable through conventional computers. Regarding the mirror circuitry itself, and because the normalization circuit output stage does not impose major range limitations, a stacked (self-biased) cascode structure is used to minimize errors due to DC mismatching. On the other hand, parallel-connected unit transistors are used to realize the binary weighting and, thus, reduce systematic errors caused by the lack of symmetry. The bias current depicted with dashed lines in Fig.10(a) is added to reduce speed degradations due to the increase of the parasitic capacitance for large singleton values. After singleton weighting the rule block outputs are wired up to the output node where a current is added to remove the offset and, thus, obtain (4). V. Global Considerations V.A. Dependence on Temperature All the building blocks except the membership function circuit have temperature independent transfer functions. The temperature dependence of the latter is caused by the large signal transconductance β in (6). However, because of the differential pair symmetry, the location and width defined in (7) are not affected by temperature changes. Electrical values of the logical zero and one are neither affected, provided the current reference is temperature-independent, because these values are associated to, respectively, logical states of the transistors in the differential pairs. The only parameter which is affected by temperature changes is the membership function slope, see (8). From a global point of view, this means that the slope of the generated function between interpolation points changes with temperature, as Fig.11 illustrates for a controller with four rules. Thus, the interpolation smoothness changes with temperature, but the yk * yk *IOS * 1N, ∑ – Figure 10: (a) Singleton weighting concept; (b) controller output node. KCL y1y1 *w1 *IOS * +()= wk *IOS * +1:yk *yk *wk *IOS * +() IOFF yk *IOFF ykyk *wk *IOS * +()= yNyN *wN *IOS * +()= yy k *wk * 1N, ∑ = yk *IOS * 1N, ∑ (a) (b) Min A Modular Programmable CMOS Analog Fuzzy Controller Chip 19 IEEE Transactions on Circuits and Systems-II interpolation points are not affected if membership functions are wide enough to saturate in the whole temperature range. V.B. Power Estimation Let us consider a controller with inputs, rules and fuzzy labels whose maximum singleton value in the associated rule base is . The maximum static power consumption is calculated as, (29) where and the currents , and are defined in Figs. 5, 6 and 8. V.C. Mismatching Errors Random variations of the transistor parameters , and can be modelled as normal distributions whose mean values are the nominal parameter values. For close and small enough transistors the variances depend mostly on the device area [12], (30) where and are the transistor channel width and length, and , and are technology-dependent. Based on , we can obtain expressions for the errors in the fuzzy controller blocks. The detailed explanation of these errors is beyond the scope of this paper; thus, only those resulting in important design equations will be outlined. Consider the membership function circuit first. Analysis shows that the most significant error corresponds to the case where the rule output is maximum [27]. The variance of the complement of the membership function current (its mean value is ) is given by, Figure 11: Illustrating dependence on temperature. M N LN 1M⁄ = ykmax * Pw M N IUIB +()×L2IUIB +()×+[]×NI CIG +()×2ISS ++{}VDD VloadISSykmax * += IU 2IQ = IB IG IC VT0 β γ σ2VT0 ()AVT0 22⁄ WL ----------------- =σ2γ() Aγ 22⁄ WL ------------- =σ2β() β2 -------------- Aβ 22⁄ WL ------------- = W L AVT0 2 Aγ 2 Aβ 2 IB A Modular Programmable CMOS Analog Fuzzy Controller Chip 20 IEEE Transactions on Circuits and Systems-II (31) where we assume that the PMOSTs MP1 and MP2S are equal, and cascode transistors mismatching is not computed because their influence is negligible as compared to signal transistors. This expression includes the errors due to the NMOS transistors (parameters and ) of the current mirror used to provide in Fig.5 †6. The error at the rule output is calculated by adding the error caused by the minimum circuit to the previous one. The variance for the worst case (only one antecedent active in the rule and non sharing of the membership function circuits) is, (32) and the corresponding mean value is . The bracketed terms correspond to the maximum circuit; the others to the complement and membership function circuits. The mismatch is smaller for any other case, although the expression of the variance is difficult to obtain because of correlations between variables. Parameters and in (32) correspond to the large signal transconductance value and the zero bias threshold voltage respectively, of the non-cascode output PMOS transistor in a current mirror that provides in Fig.5. The errors due to the normalization circuit are characterized by the following approximate variance expression, (33) where the mean value of is given by (23), 6. This mirror was omitted there in behalf of clarity and because its design is not critical for other performance parameters. σ2sij () 4IQ 2σ2βNQ () βNQ 2 ---------------------16βNQIQσ2VT0NQ ()+8IQ 2σ2βP () βP 2 ------------------4βP σ2VT0P 2IQ ----------------------------- + ⎝⎠ ⎜⎟ ⎛⎞ ++= IB 2σ2βNB () βNB 2 -------------------- 4βNBIBσ2VT0NB ()2IB 2σ2βP () βP 2 ------------------4βP σ2VT0P IB ----------------------------- + ⎝⎠ ⎜⎟ ⎛⎞ ++ + βNB VT0NB IB σ2wks ()2IB 2σ2βN3S () βN3S 2 ---------------------- 4βN3Sσ2VT0N3S IB -------------------------------------- + ⎝⎠ ⎜⎟ ⎛⎞ IC 2σ2βPC () βPC 2 --------------------4βPCICσ2VT0PC ()σ 2sij ()++ += ICIB – βPC VT0PC IC σ2wks * ()4βN4twks *1Γ–() 2σ2VT0N4b ()σ 2γN4b ()VANOR φB +φB –() 2 +[]+≈ 4βN4twks *1Γ–() 2σ2VT0N4t ()σ 2γN4t ()VBNOR φB +φB –() 2 +[]++ wks * () 21Γ–() 2σ2βN4t () βN4t 2 ---------------------βN4t βN4b ----------- ++wks *wks 1Γ–() 2σ2βN4b () βN4b 2 ----------------------+ 2wks * () 2σ2βP3S () βP3S 2 --------------------- 4βP3Sσ2VT0P3S wks * ------------------------------------ + ⎝⎠ ⎜⎟ ⎛⎞ N1– N -------------βN4t βN4b -----------ISS ´ Nwks ------------ ⎝⎠ ⎜⎟ ⎛⎞ 2 σ2wks ()++ wks * A Modular Programmable CMOS Analog Fuzzy Controller Chip 21 IEEE Transactions on Circuits and Systems-II (34) and is given by (32) for a maximum rule antecedent output current. The approximation used to calculate (33) consists of neglecting the mismatching in those normalizer inputs others than the k-th. These terms contribute only around 3% of the variance for the 16 rules CMOS prototype in this paper, and their contribution decreases as the rule count increases. This highlights an interesting feature of Fig.9 which is not shared by other approaches to the normalization operation; namely, the mismatching errors of the different rules are nearly independent. Thus, they are not mixed in the output node and manifest as offsets (easy to correct) at the points were the rule outputs are maximum (the most significant to design purposes). The global error at the rule block output includes also the influence of the weighting circuit, (35) where σ2(w*ks) is given by (33), and βin and VT0in refers to the non-cascode input transistor in the weighting circuit (see Fig.10(a)). The first term at the right in (35) corresponds to the error transmitted by the weighting circuit from previous stages, while the second term corresponds to the error introduced by itself. Note that the latter decreases when the singleton value grows. While residual systematic errors may be filtered out by the normalizer [27], the only way to attenuate the random errors is solving the design equations (30)-(35) to obtain proper transistor sizes, which is more conveniently performed with the help of an iterative optimizer. Γwks * wks * k1N,= ∑ ---------------------------- = σ2wks () σ2yk () yk * () 2σ2wks * ()yk 2σ2βin () βin 2 ------------------ 4βinykσ2VT0in ()+1 1 yk∗ ------- + ⎝⎠ ⎛⎞ += A Modular Programmable CMOS Analog Fuzzy Controller Chip 22 IEEE Transactions on Circuits and Systems-II VI. Experimental Results Fig.12(a) shows the microphotograph of a chip that performs the processing tasks involved in (4) and Fig.2(a). It is a lattice controller with two inputs and four labels per input (see Fig.2(b)). Thus, eight label blocks, four per chip input, are needed, as well as sixteen rule blocks. The label blocks outputs are connected to inputs of rule blocks through a “ring bus”. Bias circuitry, as well as one diode connected transistor and one current mirror, which complete the normalization circuit in Fig.9, are implemented in the “biasing box”. Table 1 shows the most relevant transistor sizes in this chip. Digital values to program the output current mirror and hence the singleton values are stored in a “shift register” which is the chip internal memory element and is serially programmed through two pads. Apart from digital programmability of the singleton values, width and location of membership functions are also analogically programmable by setting the voltages and (see (7) and Fig.5). Figs. 13(a) and (b) show two output surfaces generated by the chip. The bias signals are , , , , , and , while the voltages are fixed to obtain a uniform lattice partition of the input space. The circuit was loaded with a constant voltage source of 2.5V and a current source to remove the offset introduced in the normalization circuit. Singletons are set to decimal values 1 and 15 in Fig.13(a), which highlights the locality of the fuzzy basis functions, while Fig.13(b) illustrates an exemplary surface obtained with different singleton values. Finally, Fig.13(c) depicts a set of sections from Fig.13(b) which show the output when it reaches their local maximum values, thus the singleton values. Table 1:Transistor sizes (W/L) in μm/μm in the prototype chip MN1ij-MN1ij+MP1 MP2S MP2C MN2B MN2T MNQ MNQC MN3S MN3C MN4bkMN4tkMP3S MP3C MN5S MN5C 40/10 40/10 50/5 50/5 50/2 20/10 20/10 10/10 10/1 20/10 20/1 30/5 50/5 50/5 50/1 20/10 20/5 bias. flip-flop rule block label block ring bus biasing box shift register Figure 12: (a) Chip microphotograph; (b) internal architecture. (a) (b) Eij+ EijVDD 5V= VSS 0V= IQ7,5μA= IB10μA= IG0,5μA= IC35μA= ISS 37μA= Eij A Modular Programmable CMOS Analog Fuzzy Controller Chip 23 IEEE Transactions on Circuits and Systems-II Maximum circuit delay is 471ns (90% of the full scale output current) for a step input, while power consumption is 8.6mW and resolution is around 6.5%. The latter was obtained through Monte Carlo simulations (30 iterations) which take into account parameter mismatching among transistors, with 3σ ( ) as error figure. Finally, input voltage range is over 3.25V and the area of the chip without pads is 1.6mm2. It is possible to achieve faster designs by introducing bias currents at input and output branches of the current mirror that replicates membership function output, and in the output mirror that implements singleton weighting. It is also possible to achieve a higher precision by inserting the chip in a learning loop with a computer and using the hardware-compatible learning algorithms presented in [18]. Table 2 compares the performance of this prototype to that of previous analog monolithic controllers. It features much smaller values than these previous circuits, and similar programmability levels than the controller in [16]. However, in this latter controller the consequents values have to be learned using software models, the programming signals are 12 3 41 2 3 4 y, μamps x1, volts x2 , volts 12 3 41 2 3 44.5 y, μamps x1, volts x2 , volts 0 50 100 150 0 100 8 6 4 2 10 8 6 4 6 4 2 1 12 10 8 6 x2=4V x2=2.4V x2=1.6V x2=3.2V Figure 13: (a) and (b) Controller output for two different sets of singleton values: (c) and sections from (b) at maximum local points. (a) (b) (c) 50 1.5σ± Delay Power× A Modular Programmable CMOS Analog Fuzzy Controller Chip 24 IEEE Transactions on Circuits and Systems-II analog (more difficult interface) and are not stored on-chip. VII. References [1] J.M. Mendel, “Fuzzy Logic Systems for Engineering: A Tutorial”. Proceedings of the IEEE, Vol. 83, pp. 345377, March 1995. [2] H. Takagi, “Applications of Neural Networks and Fuzzy Logic to Consumer Products”. pp. 8-12 in Fuzzy Logic Technologies and Applications, New-York: IEEE Press 1994. [3] M. Brown and C. Harris, Neuro-Fuzzy Adaptive Modeling and Control. Englewood Cliffs: Prentice Hall 1994. [4] J.S.R. Jang and C.T. Sun, “Neuro-Fuzzy Modeling and Control”. Proceedings of the IEEE, Vol. 83, pp. 378406, March 1995. [5] H. Watanabe, W. D. Dettloff, and K. E. Yount, “A VLSI Fuzzy Logic Controller with Reconfigurable, Cascadable Architecture”. IEEE J. Solid-State Circuits, Vol. 25, pp. 376-382, 1990. [6] K. Nakamura , N. Sakashita, Y. Nitta, K. Shimomura and T.Tokuda, “Fuzzy Inference and Fuzzy Inference Processor”. IEEE Micro, Vol. 13, pp. 37-48, October. 1993. [7] H. Eichfeld, M. Klimke, M. Menke, J. Nolles and T. Künemund, “A General-Purpose Fuzzy Inference Processor”, IEEE Micro, Vol. 15, pp. 12-17, June 1995. [8] A. Costa, A. de Gloria, P. Faraboschi, A. Pagni and G. Rizzotto, “Hardware Solutions for Fuzzy Control”. Proceedings of the IEEE, Vol. 83, pp. 422-434, March 1995. [9] T. Yamakawa, “A Fuzzy Inference Engine in Nonlinear Analog Mode and Its Application to a Fuzzy Logic Control”. IEEE Trans. on Neural Networks, Vol. 4, pp. 496-522, May 1993. [10] E.A. Vittoz, “The Future of Analog in the VLSI Environment”. Proceedings of the 1990 IEEE Int. Symp. on Circuits and Systems, pp. 1372-1375, 1990. [11] K.A. Nishimura, Optimum Partitioning of Analog and Digital Circuitry in Mixed-Signal Circuits for Signal Processing. Ph Dissertation, U.C. Berkeley, 1993. [12] M.J.M. Pelgrom, A.C.J. Duinmaijer, and A.P.G. Welbers, “Matching Properties of MOS Transistors”. IEEE Journal of Solid-State Circuits, Vol. 24, pp. 1433-1440, October 1989. [13] J.W.Fattaruso, S.S. Mahant-Shetti, and J.B. Barton, “A Fuzzy Logic Inference Processor”. IEEE Journal of Solid-State Circuits, Vol. 29, pp. 397-402, April 1994. [14] J. L. Huertas, S. Sánchez-Solano, I. Baturone, and A. Barriga, “Integrated Circuit Implementation of Fuzzy Controllers”. IEEE Journal of Solid-State Circuits, Vol. 31, pp. 1051-1058, July 1996. [15] L. Lemaitre, M. J. Patyra, and D. Mlynek, “Analysis and Design of CMOS Fuzzy Logic Controller in Current Mode”. IEEE Journal of Solid-State Circuits, Vol. 29, pp. 317-322, March 1994. [16] N.Manaresi, R. Rovatti, E. Franchi, R. Guerrieri, and G. Baccarani, “A Silicon Compiler of Analog Fuzzy Table 2:CMOS Analog Implementations of Fuzzy Controllers CMOS Manaresi [16] Guo [17] Proposed Complexity 9rules@2input @2output 13rules@3input @1output 16rules@2input@1output Technology 0.7μm CMOS 2.4μm CMOS 1 μm CMOS Power Consumption 44mW@5V 550mW@10V 8.6mW@5V Input to Output Delay 570 ns 160 ns 471 ns Precision No data No data 6.5% (3σ) Interface (inputs@outputs) voltages@ voltages voltages@ voltages voltages@ currents Programmability high low high Area 1.9 mm216.2 mm21.6 mm2