Extremely low-voltage low-power differential difference current conveyor using multiple-input bulk-driven technique

Extremely low-voltage low-power differential difference current conveyor using multiple-input bulk-driven technique KUMNGERN, M.; KHATEB, F.; KULEJ, T. AEU - International Journal of Electronics and Communications 2020, vol. 123, August 2020, pp. 1−11 ISSN: 1434-8411 DOI: https://doi.org/10.1016/j.aeue.2020.153310 Accepted manuscript © 2020. This manuscript version is made available under the CC-BY-NC-ND 4.0 license http://creativecommons.org/licenses/by-nc-nd/4.0/ dspace.vutbr.cz Extremely low-voltage low-power differential difference current conveyor using multiple-input bulk-driven technique Montree Kumngern1, Fabian Khateb2,3, Tomasz Kulej4 1 Department of Telecommunications Engineering, Faculty of Engineering, King Mongkut’s Institute of Technology Ladkrabang, Bangkok 10520, Thailand 2 Department of Microelectronics, Brno University of Technology, Technická 10, Brno, Czech Republic 3 Faculty of Biomedical Engineering, Czech Technical University in Prague, nám. Sítná 3105, Kladno, Czech Republic 4 Department of Electrical Engineering, Czestochowa University of Technology, 42-201 Czestochowa, Poland [email protected], [email protected], [email protected] Abstract In this paper, a new differential difference current conveyor (DDCC) with ultra-low voltage and low-power capability is presented. The DDCC is designed by using a non-tailed differential pair with multiple-input bulk-driven MOS transistor technique to obtain a rail-torail input common-mode swing and extremely low supply voltage. The MOS transistors biased in the sub-threshold region have been used to achieve extremely low power consumption. The performance of the proposed DDCC is evaluated by simulation results using SPICE program and MOS transistors parameters provided by a standard n-well 0.18 µm CMOS process from TSMC. A rail-to-rail input common-mode range was shown and a high accuracy was expressed. The bandwidth was 2.2 kHz and the total harmonic distortion was 1 % for an input signal with amplitude of 240 mVp-p, obtained at supply voltage of 0.3 V and power dissipation of 28.6 nW. The proposed DDCC has been used to realize a sixth-order low-pass filter for application to electrocardiogram (ECG) applications. Keywords: Differential difference current conveyor; subthreshold technique; bulk-driven technique; multiple-input bulk-driven technique; low voltage and low power; high-order filter; analog circuit 1. Introduction The second generation current conveyor (CCII) is a basic building block which can find many applications in analog signal processing applications such as continuous-time filters, signal generators, nonlinear circuits, electrical elements (resistance, inductance, memristance) simulators/emulators circuits and data converters [1]-[7]. In comparison to operational amplifier (op-amp)-based circuits, CCII-based circuits offer several advantages: simple circuit structure, alleviating the need for both floating passive components and matched resistors, wide frequency bandwidth, versatile and high accuracy in realizing the intended characteristics, large dynamic range and low supply voltage requirement [8]. A number of CCIIs is available in open literature [9]-[19]. The early structure of CCII is a conventional CCII which offers three terminals, namely y-, xand z-terminals [9]. The unity voltage gain can be obtained between yand x-terminals while the unity current gain can be obtained between xand z-terminals. However, a single CCII may be limited for some applications: obtaining differential voltage or current input signals requirements, positive and negative for feedback connections and alleviating the need for floating resistors, etc. Therefore, there are several structures of CCIIs which have been developed to increase the performance of conventional CCII: differential difference current conveyor (DDCC) [10], differential voltage current conveyor (DVCC) [11], dual X second generation current conveyor (DX-CCII) [12], extra X second generation current conveyor (EX-CCII) [13], differential second generation current conveyor (DCCII) [14], fully differential second-generation current conveyor (FDCCII) [15]. These structures improved the performance of conventional CCII, which has one y-terminal, one x-terminal and one z-terminal, by adding y-terminal and/or x-terminal to obtain adding/subtracting voltage and current differencing capability. This work focuses on the DDCC which provides the advantages of conventional CCII and arithmetic operation capability of differential difference amplifier (DDA) [16] into single device. Thus, the conventional DDCC has three y-terminals, one x-terminal and one z-terminal, where adding and subtracting voltage can be obtained through two plus-type y-terminals and one minustype y-terminal. The DDCC with both plus-type and minus-type y-terminals is convenient for realizing positive and negative feedback applications such as negative feedback for filters and positive feedback for oscillators. There are DDCC based analogue circuits that have been reported in literature in recent years, for example, see [17]–[21]. Unfortunately, these circuits do not provide ultra-low voltage and ultra-low power operation. At present, the analogue circuits operating with ultra-low supply voltage and ultra-low power consumption are of grown interest, due to the fact that these circuits can be applied in portable electronics and biomedical devices [22]. The analogue signal processing circuits such as continuous-time filters [23]–[25], amplifiers [26]-[27], precision rectifiers [28]–[29], are usually required for applications. There are many active devices operating with ultra-low supply voltage and ultra-low power consumption available in open literature such as operational transconductance amplifiers (OTAs) [30]–[32], current conveyors [33]–[34], DDA [35] etc. Focusing on DDCC operated with ultra-low supply voltage and ultra-low power consumption, this device has been already introduced using different MOS techniques [36]– [41]. Several DDCCs based on bulk-driven (BD) MOS technique [36], [37], quasi-floating gate (QFG) [36], BD QFG MOS technique [36], [38], multiple-input bulk-driven (MIBD) QFG MOS technique [39], [40], multiple-input bulk-driven (MIBD) [40], have been proposed. If consider the supply voltage and power consumption, the circuits in [36], [37] use 0.6 V (±0.3) of supply voltage and consume about 18.5 µW of power, the circuit in [38] uses a 1 V of supply voltage and consumes 37 µW of power, the circuit in [39] uses a 0.5 V of supply voltage and consumes 1.7 µW and the circuits in [40] uses a 0.4 V of supply voltage and consumes 0.14 µW of power. It should be noted in [36]–[40] that the supply voltage and power consumption, respectively, of DDCCs are scaled down from 1 V to 0.4 V and 37 µW to 0.14 µW. Until now, DDCC operating with 0.3 V supply voltage and consuming 38 nW of power is introduced [41]. The input stage of DDCCs in [36]–[40] is realized based on differential structure which needs a tail current. A tail current is usually implemented by a MOS transistor, which increases the minimum supply voltage by at least 𝑉𝐷𝑆(𝑠𝑎𝑡). Thus, the lowest supply voltage of these DDCCs [36]–[40] is around 0.4 V [40]. Unlike the DDCCs in [36]–[40], the DDCC in [41] is based on a non-tailed differential amplifier, and is able to operate from supply voltage as low as 0.3 V, which cannot be achieved for a DDCC with a tail current differential amplifier. The circuit in [41] can operate with extremely low supply voltage, but shows relatively poor accuracy of the voltage/current gains, which is the result of its simple structure and low open-loop voltage gain of the y-x amplifier. This also results in relatively low value of the resistance Rx, seen from its x terminal. In order to overcome the above issues, a high performance DDCC which can operate with ultra-low supply voltage and ultra-low power consumption has been proposed in this paper. The proposed DDCC can operate from supply voltage as low as 0.3-V, which is possible thanks to the use of non-tailed differential pair in its input stage. The multiple-input bulk-driven technique is also used to reduce a number of MOS differential pairs. The DDCC shows ultra-low supply voltage and ultra-low power consumption using three techniques, namely, subthreshold biasing, dynamic threshold MOS and bulk-driven MOS techniques. The bulk-driven technique is used in the input stage and thanks to this a rail-to-rail input commonmode range can be obtained. The performance of the proposed DDCC was evaluated by simulation, using SPICE and transistors parameters for a standard n-well 0.18 µm CMOS process from TSMC. Simulations showed the bandwidth of 2.2 kHz and the total harmonic distortion of 1 % for an input signal with amplitude of 240 mVp-p, obtained at supply voltage of 0.3 V and power dissipation of 28.6 nW. The proposed DDCC has been used to realize a sixth-order low-pass filter for electrocardiogram (ECG) applications. 2. Proposed ultra-low voltage MIBD DDCC In this work the multiple-input bulk-driven (MIBD) MOS transistor (MOST) technique, [40] was applied. The symbol and implementation of the MIBD MOS are shown in Figs. 1(a) and Fig. 1(b) respectively. The MIBD MOST is a multiple-input device which is realized using parallel connections of capacitors CBi and resistors RLi, where i = 1, 2, …, N, while its gate terminal is properly biased with DC voltage Vb. Assuming that an n-well CMOS process was applied in the design , only the p-channel MOS transistors can be controlled in such a way. The resistor RL should possess high resistance value which can be implemented using two transistors ML operating in cut-off region as shown in Fig. 1(b). The small-signal model of the MIBD MOST that has been used for AC small-signal analysis is shown in Fig. 1(c). The gmb is the bulk transconductance, ro is the output resistance, the capacitances CBS, CBD, CBSUB are respectively the parasitic capacitances bulk-source, bulk-drain and bulk-substrate. The capacitance CMi is the parasitic capacitance between gate and drain of the transistor MLi, the resistance RMi is the output resistance of the transistor MLi while the capacitance CBi is the input capacitance. GVin1 S D VinN BVb (a) CB1 S D B Vin1 VinN CBN GVb RL1 RLN ML ML (b) CBS VinN CBD RMN CMN CBN Vin1 CM1 CB1 RM1 B CBSUB Sub D ro gmbVBS S (c) Fig. 1. MIBD PMOST [40]: (a) symbol of MIBD, (b) MIBD implementation, (c) small-signal model. From Fig. 1(c), assuming 1/CBi << RLi, CMi << CBi the input transconductances (𝑔𝑚𝑖) of MIBD MOST can be given [40] by 𝒈𝒎𝒊=𝑪𝑩𝒊 𝑪𝑻𝑶𝑻𝒈𝒎𝒃 (1) where 𝑪𝑻𝑶𝑻 is the total capacitance looking into input port which can be given by 𝑪𝑻𝑶𝑻=𝑪𝑩𝑺+𝑪𝑩𝑫+𝑪𝑩𝑺𝑼𝑩+∑𝑪𝑴𝒊+ 𝑵 𝒊=𝟏 ∑𝑪𝑩𝒊 𝑵 𝒊=𝟏 (2) The voltage at bulk terminal 𝑽𝑩 can be given by 𝑽𝑩≈∑𝑪𝑩𝒊 𝑪𝑻𝑶𝑻𝑽𝒊𝒏,𝒊 𝑵 𝒊=𝟏 (3) The relation between the inputs-referred noise powers of the MIBD MOST 𝒗𝒏,𝒊 𝟐      compared to the BD MOST 𝒗𝒏,𝑩 𝟐      can be expressed by 𝒗𝒏,𝒊 𝟐      =(𝑪𝑻𝑶𝑻 𝑪𝑩,𝒊)𝟐𝒗𝒏,𝑩 𝟐      (4) where 𝑪𝑻𝑶𝑻 is the total capacitance looking into the input port. It can be concluded from (4) that the input-referred noise of the MIBD MOST is increased by 𝑪𝑻𝑶𝑻 𝑪𝑩,𝒊 ⁄, but the maximum input signal range is also increased with the same ratio, hence the dynamic range (DR) is not affected by this ratio. Fig. 2 shows the circuit symbol of DDCC and its port relations can be expressed by ( 𝑰𝒚𝟏 𝑰𝒚𝟐 𝑰𝒚𝟑 𝑽𝒙 𝑰𝒛 ) = ( 𝟎 𝟎 𝟎 𝜷𝟏 𝟎 𝟎 𝟎 𝟎 −𝜷𝟐 𝟎 𝟎 𝟎 𝟎 𝜷𝟑 𝟎 𝟎 𝟎 𝟎 𝟎 𝜶 𝟎 𝟎 𝟎 𝟎 𝟎 ) ( 𝑽𝒚𝟏 𝑽𝒚𝟐 𝑽𝒚𝟑 𝑰𝒙 𝑽𝒛 ) (5) where 𝛽1=1−𝜀1𝑣, 𝛽2=1−𝜀2𝑣, 𝛽3=1−𝜀3𝑣 represent the voltage gain between xterminal and y1-, y2-, y3-terminals, respectively, 𝛼=1−𝜀𝑖 represents the current gain between z-terminal and x-terminal, whereas 𝜀1𝑣, 𝜀2𝑣, 𝜀3𝑣 (|𝜀1𝑣|, |𝜀2𝑣|, |𝜀3𝑣|≪1 and |𝜀𝑖|≪1) represent respectively voltage and current tracking errors. For ideal case, 𝛽1= 𝛽2= 𝛽3= 𝛼 =1. DDCC y1 z Vy1 Vz Iz x Vx Ix y3 Vy3 y2 Vy2 Iy2 Iy3 Iy1 Fig. 2. Electrical symbol of DDCC. VSS VDD M1y2y3 y3 M5M6 VB M9M10 M13 M11 M16 VB IB MB VB VSS zx y2 M2M4M3 M7 M12 M8 M14 M17 M18 y1 M15 Fig. 3. Proposed 0.3 V MIBD DDCC. The proposed internal structure of the DDCC is shown in Fig. 3. The transistors, M1M6, of the circuit form a non-tailed bulk-driven differential amplifier [42] which is realized using the MIBD MOST technique to obtain multiple-input differential amplifier and to reduce a number of MOS transistor pairs. This non-tailed architecture provides a good CMRR [32], [35], [42], which can improve the accuracy of DDCC when it is connected in a negative feedback unity-gain configuration. The non-tailed differential amplifier provides an ultra-low supply voltage of the circuit because the voltage across tail current source is absent [35]. The cross-coupled transistors M7 and M8 are added to form a positive feedback and provide some increment for the DC gain and gain bandwidth product (GBW) performance of differential amplifier. These transistors will generate negative conductance, i.e. -gm7 and -gm8, for decreasing the total conductance at the drain terminals of M9 and M10. The diode-connected transistors M9 and M10 are used for the load of differential amplifier which decreasing the total conductance by -gm7 and -gm8 and consequently to improving the DC gain and GBW of differential amplifier [35]. The transistors M11-M14 are used to mirror the output currents of differential amplifier and converted current signals into a single voltage at the drain terminals of M13 and M14. The output stage consists of transistors M15-M18 when transistors M15 and M16 work as output amplifier operating in class-AB, loaded with the current source using transistors M17 and M18. The high current driving capability can be obtained by increasing the quiescent drain currents of M17 and M18. To obtain a unity-gain voltage follower, the output terminal (drain of transistor M15) is connected to the input bulk terminals of transistors M2 and M3 thus forming a negative feedback loop. The unity-gain current follower can be obtained using complementary transistors M16 and M18 to mirror the current from x-terminal to z-terminal. The minimum supply voltage 𝑽𝑫𝑫min(𝐢𝐧) of the input stage is given by 𝑽𝑫𝑫𝐦𝐢𝐧(𝐢𝐧)=𝐦𝐚𝐱(𝑽𝑮𝑺,𝑴𝒊+𝑽𝑫𝑺(𝒔𝒂𝒕),𝑴𝒋) (6) where 𝑖 = 2, 4, 9, 10 and 𝑗 = 1, 3, 5, 6. Letting 𝑉𝐷𝑆(sat) = 𝑉𝐷𝑆(𝑠𝑎𝑡),𝑀15−𝑀18, the minimum supply voltage 𝑉𝐷𝐷min(out) of the output stage is approximately 𝑉𝐷𝐷min(out) = 2𝑉𝐷𝑆(sat). Assume that circuit is biased in sub-threshold region and letting |𝑉𝐺𝑆|,𝑀2−𝑀4 = 𝑉𝐺𝑆,𝑀9−𝑀10 = 𝑉𝐷𝑆(sat), the 𝑽𝑫𝑫min of both input and output stages is 2𝑉𝐷𝑆(sat) which is approximately equal to 6 to 8 𝑈𝑇 [35], where 𝑈𝑇 is about 26 mV at room temperature. Assuming perfect symmetry of the first stage (M1 – M14), the voltage transfer ratios 𝛽1, 𝛽2, 𝛽3, can be expressed by: 𝜷𝒊=𝑽𝒙 𝑽𝒚𝒊 =𝑨𝒐𝒊 𝟏+𝑨𝒐𝒊 (7) where 𝐴𝑜𝑖 (𝑖 = 1…3) is the open-loop voltage gain of the internal differential difference amplifier (M1-M15 and M17) from 𝑖 -th input, that is given by: 𝑨𝒐𝒊=𝒈𝒎𝒊 𝒈𝒅𝒔𝟏𝟑+𝒈𝒅𝒔𝟏𝟒∙𝒈𝒎𝟏𝟓 𝒈𝒅𝒔𝟏𝟒+𝒈𝒅𝒔𝟏𝟓 (8) where, 𝑔𝑑𝑠𝑖 and 𝑔𝑚𝑖 are respectively the output conductance and the gate transconductance of Mi respectively (𝑖 = 1…N). The transconductance gmi represents the transconductance of the first stage from i-th input, which can be approximated as: 𝒈𝒎𝒊≅𝟐𝒈𝒎𝒃𝟏,𝟑 𝒈𝒎𝟏𝟐,𝟏𝟒/𝒈𝒎𝟗,𝟏𝟎 (𝟏−𝒎)+𝒈∑/𝒈𝒎𝟗,𝟏𝟎∙(𝑪𝑩𝒊 𝑪𝑻𝑶𝑻) (9) where gmbi denotes the bulk transconductance of Mi, m=gm7,8/gm9,10, g= gds1,3 +gds7,8 +gds9,10. The current transfer ratio α of the overall DDCC can be expressed as: 𝜶=𝒈𝒎𝟏𝟔 𝒈𝒎𝟏𝟓 (10) The open-loop bandwidth of the internal differential-difference amplifier mentioned above is limited mainly by the three parasitic poles associated with internal nodes of this circuit. The first pole is associated with the drain node of M9 (M10): 𝒑𝟏=−𝒈𝒎𝟗,𝟏𝟎[(𝟏−𝒎)+𝒈∑/𝒈𝒎𝟗,𝟏𝟎] 𝑪∑𝟏 ∙(𝑪𝑩𝒊 𝑪𝑻𝑶𝑻) (11) where C1 is the total capacitance associated with this node. The second pole is associated with the output of the first gain stage (drain terminal of M13): 𝒑𝟐=−(𝟏+ 𝒈𝒎𝟏𝟓 𝒈𝒅𝒔𝟏𝟓+𝒈𝒅𝒔𝟏𝟕)𝑪𝒈𝒅𝟏𝟓+𝑪∑𝟐 (12) where C2 is the total capacitance associated with this node, except Cgd15. The third pole is associated with the x terminal of the DDCC: 𝒑𝟑=−𝒈𝒎𝟏𝟓 𝑪𝒙 (13) where Cx is the total capacitance associated with the x terminal. Assuming that the DDCC is properly frequency compensated, the poles p1 and p3 should be located well above the 3-dB frequency of the y-x follower. In such a case, the 3-dB frequency of the voltage gain of this follower is approximately equal to the GBW product of the internal differential-difference amplifier mentioned earlier and can be approximated as: 𝒇𝟑𝒅𝑩=𝒈𝒎𝒊 𝑪𝒈𝒅𝟏𝟓 (14) The 3-dB frequency of the x-z current follower is also limited by the above mentioned effects, and for y and z terminals shorted to ground for AC signals can be approximated by (14) as well. The i-th input referred thermal noise of the proposed DDCC can be approximated by: 𝑣𝑛2    =1 2∙8𝑘𝑇 3(𝑔𝑚𝑏1,3 2)[𝑔𝑚1,3+(𝑔𝑚2,4+𝑔𝑚5,6)(𝑔𝑚1,3 𝑔𝑚2,4)2+𝑔𝑚7,8+𝑔𝑚9,10+(1− 𝑚)2(𝑔𝑚9,10 𝑔𝑚12,14)2(𝑔𝑚12,14+𝑔𝑚11,13)](𝐶𝑇𝑂𝑇 𝐶𝐵,𝑖)2 (15) It is worth noting, that the optimum noise performance is obtained when all transistors M1-M4 are identical [42]. The input resistance seen from the x-terminal can be approximated as: 𝑹𝒙≈𝒓𝒅𝒔𝟏𝟒‖𝒓𝒅𝒔𝟏𝟓 𝑨𝒐𝒊 (16) where it is assumed that Aoi is identical for every i=1..3. Finally, the output resistance of the DDCC seen from the z-terminal is given by: DDCC y1z x y3 y2 R1 R2 DDCC y1z x y3 y2 C1 R2 C2 DDCC y1z x y3 y2 R3 R4 DDCC y1z x y3 y2 C3 R4 C4 DDCC y1z x y3 y2 R5 R6 DDCC y1z x y3 y2 C5 R6 C6 VoutVout+ Vin+ VinFig. 9. Sixth-order Butterworth low-pass filter. The sixth-order maximally flat low-pass filter was designed by cascading three second-order low-pass filters, which are arranged as follows: stage 1, frequency scaling factor (FSF) = 1, Q = 0.518: stage 2, FSD = 1, Q = 0.707: stage 3, FSF = 1, Q = 1.932. Therefore, the normalized transfer function of sixth-order Butterworth low-pass filter is: 𝑉𝑜𝑢𝑡(𝑠) 𝑉𝑖𝑛(𝑠) =( 1 𝑠2+1.93𝑠+1)( 1 𝑠2+1.414𝑠+1)( 1 𝑠2+0.518𝑠+1) (19) The proposed sixth-order Butterworth low-pass filter was designed with the cut-off frequency 𝑓𝑜 of 100 Hz. The first stage, second stage and the third stage were designed with the cut-off frequencies of 70 Hz, 100 Hz and 148 Hz, respectively. The value of capacitances C1 and C2 of each stage will be equalled and the value of resistances R1 and R2 of each stage will be used to adjust the value of quality factor. Thus the filter in Fig. 9 was designed as follows: 𝐶1 = 𝐶2 = 300 pF, 𝑅1 = 5.8 M, 𝑅2 = 3 M, 𝐶3 = 𝐶4 = 220 pF, 𝑅3 = 5.8 M, 𝑅4 = 2.5 M, 𝐶5 = 𝐶6 = 220 pF, 𝑅5 = 1.8 M, 𝑅6 = 14 M. In practice, these high values of resistances and large values of capacitance can be implemented off-chip. The high values of resistances were used because the high linearity and wide input range of filter can be obtained. 1.0 10 100 1.0k 10k -180 -160 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency, Hz Gain, dB Proposed Theoretical Fig. 10. Simulated frequency response of the sixth-order Butterworth low-pass filter. 1.0 10 100 1.0k 10k -180 -160 -140 -120 -100 -80 -60 -40 -20 0 20 Frequency, Hz Gain, dB Theoretical Temp.=0-75°C 10 100 300 -10.0 -7.5 -5.0 -2.5 0 Frequency, Hz Gain, dB Zooming Fig. 11. Simulated frequency response of the sixth-order Butterworth low-pass filter for different temperature. Fig. 10 shows the simulated frequency responses of the proposed sixth-order Butterworth low-pass filter. The cut-off frequency of the filter was 99 Hz and the DC voltage gain was -2.4 dB while the filter consumed 172 nW of power. The simulated frequency response was also compared with theoretical curve. Fig. 11 shows the variations of the frequency response for temperature varied from 0 to 75 °C. The simulation result shows that the DC voltage gain varied between -2.12 dB and -4.34 dB, whereas the variations of the cutoff frequency of the filter were negligible. Fig. 12 shows the simulated transient response of the filter when the 10 Hz sinusoidal input voltage signal with the amplitude of 240 mV (peak-to-peak) was applied. This result can be shown the operation of input voltage swing of 240 mV (peak-to-peak) with the total harmonic distortion (THD) of 1.09 %. To test the linearity of the proposed filter, a single tone test and two-tone test have been investigated. Fig. 13 shows the results of the single tone test of the proposed filter when the input frequency of 10 Hz was supplied whereas amplitude of input sinusoidal voltage was varied. The THD was 1.09 % when the amplitude of input voltage was increased to 240 mV (peak-to-peak). The two-tone test has been investigated by applying two input frequencies of 50 Hz and 60 Hz into the circuit and the amplitude of input sinusoidal voltages was varied. The simulated 3rd inter-modulation distortion (IMD) was shown in Fig. 14. It can be found that amplitude of the output signal for a 2% 3rd IMD was 50 mV while the amplitude of the input signal was 140 mV (peak-to-peak). 050 100 150 200 250 300 350 400 450 500 -160 -120 -80 -40 0 40 80 120 160 Time, ms Voltage, mV Vin Vout Fig. 12. Simulated transient response with input voltage swing. Fig. 13. THD variation versus amplitude of the input sinusoidal voltage at 10 Hz . 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 050 100 150 200 250 300 THD, % Vin (peak-to-peak), mV Fig. 14 . The third-order IMD versus the input voltage. In case of noise testing, the proposed sixth-order Butterworth low-pass filter was simulated to evaluate the integrated input reference noise for the bandwidth of 100 Hz. From our simulation, it can be found that an input-referred noise voltage was 338 µVrms whereas an outputreferred noise voltage was 238 µVrms. If a single-tone test has been used to define the dynamic range (DR), at THD of 1.09 % (Vin = 84.8 mVrms), the DR was 48 dB. The proposed sixth-order low-pass filter has been compared with previous works [23], [24], [43]-[45] as shown in Table II. It can be shown that the proposed DDCC can be applied to biomedical systems because the circuit can operate with ultra-low supply voltage and ultralow power consumption. In order to evaluate and compare the performance of the filters in Table II, the following standard Figure of Merit (FoM) [46] was used 𝐹𝑜𝑀= 𝑃×𝑉𝐷𝐷 𝑁×𝑓𝑐×𝐷𝑅 (20) 0.0 0.5 1.0 1.5 2.0 2.5 25 50 75 100 125 150 3rd IMD, % Vin (peak-to-peak), mV Table II. Comparison of the proposed filter to some previous sixth-order low-pass filters. This work 2000 [43] 2014 [44] 2019 [23] 2019 [24] 2019 [45] Technology [m] 0.18 0.8 0.35 0.13 0.18 20 Supply voltage [V] 0.3 ±1.5 0.5 0.25 1 10 Topology CMOS CMOS CMOS CMOS CMOS a-IGZO TFT Number of active 6-DDCC 8-OTA 50-MOS 5-FDDTA, 1OTA 6-OTA 3-DDA Number of passive 9-R & 6-C 6-C 6-C 5-C 5-C 15-C, 24-MSW† Filter order 6th LP (Butterworth) 6th LP (Butterworth) 6th LP (Bessel) 5th LP (Butterworth) 5th LP (Butterworth) 6th LP (Butterworth) Architecture Fully diff. Single-ended Single-ended Fully diff. Fully diff. Fully diff. Bandwidth [Hz] 99 2.4 2.4 100 250 272 Noise [Vrms] 339 <50 0.43E-12 A* 4.7 134 - DC gain [dB] -2.5 -10 0 ~ -6 -7 -0.65 Power consumption [W] 172E-9 10E-6 7.21E-9 603E-9 41E-9 0.537E-3 Dynamic range [dB] 48@1%THD [email protected]%THD 51.1@4%THD 57 61.2 - FOM 1.76E-12 3.47E-8 4.9E-12 5.29E-12 5.47E-13 - Note: * current-mode filter, † MSW = MOS switch, a-IGZO TFT = amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistor (TFT) DDA = differential difference amplifier, R = resistor, C = capacitor FDDTA = fully differential difference transconductance amplifier, OTA = operational transconductance amplifier 5. Conclusion This paper presents a new differential difference current conveyor (DDCC) with ultra-low voltage and low-power capability for application to biomedical systems. The DDCC is designed by using a non-tailed differential pair with multiple-input bulk-driven MOS transistor technique to obtain a rail-to-rail input common-mode range and extremely low supply voltage. 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