Design of a High Power Amplifier for Earth-Moon-Earth Communications
Abstract
Radio comunicações usando a Lua como repetidor de modo a permitir ligações de longa dis-tância sem linha direta de vista (line of sight) contornando a curvatura da terra são já realizadasdesde meados do século passado. Desde os inícios desta tecnologia, sempre foi necessário con-tornar forte atenuação de espaço livre do sinal devido à enorme distância que a Lua se localiza.Um dos métodos predominantes para tornar possível este tipo de comunicações é a transmissãode sinais de alta potência, que nos primórdios do Moonbouncing estava na ordem dos milhares deWatts, atualmente, com modulações mais complexas e recetores mais avançados é possível serfeita com apenas centenas de Watts, como demonstrado na secção de link budget do documento,continuando um desafio para entusiastas do Radio Amadorismo.Esta dissertação aborda essencialmente o processo de desenvolvimento de um amplificador depotência capaz de produzir 200 W à frequencia de 2.4 GHz com a melhor eficiência e linearidadepossiveis. Para conseguir concretizar o objetivo imposto, uma revisão do estado de arte na áreade desenvolvimento de amplificadores de radio frequência mostrou ser essencial estabelecendometodologias de trabalho e métricas para a análise desse mesmo trabalho. Foi ainda possível de-terminar que classe AB, classe F ou F inverso seriam as tipologias mais indicadas permitindo altaspotências sem sacrificar demasiado a eficiência em aplicações em que a linearidade do dispositivonão é critica.Posto isto, o plano de trabalhos seguiu a forma canónica de desenvolvimento de amplificadoresde potencia deste tipo de classes, tendo por base o circuito exemplo presente na datasheet dodispositivo ativo escolhido.Em todo o processo de desenvolvimento foi usado o software Advanced Design System 2021que tornou possível as várias análises do circuito do amplificador aliado à ferramenta de simulaçãoMomentum da Keysight Technologies que permitiu obtenção de modelos comportamentais maisfiáveis nas várias etapas de desenvolvimento evitando surpresas do ponto de vista de performanceapós a implementação prática do amplificador.Diferentes pontos de funcionamento, biasing networks e matching networks foram experimen-tadas de modo a obter um design estável capaz de cumprir o requisito mínimo de potência o maiseficiente possível, sendo na simulação eletromagnética final obtido o requisito mínimo de potênciacomPAE=51.6%.Durante o processo de desenvolvimento foi essencial uma atitude de compromisso entre aeficiência potência estabilidade e linearidade do amplificador, sendo cada uma das etapas essencialpara estabelecer o equilíbrio entre cada um desses fatores.
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FACULDADE DE ENGENHARIA DA UNIVERSIDADE DO PORTO Design of a High Power Amplifier for Earth-Moon-Earth Communications Pedro Manuel Moreira Teixeira FINAL VERSION Mestrado Integrado em Engenharia Electrotécnica e de Computadores Supervisor: Hugo Miguel Guedes Pereira dos Santos Co-supervisor: Sérgio Reis Cunha July 27, 2021
Design of a High Power Amplifier for Earth-Moon-Earth Communications Pedro Manuel Moreira Teixeira Mestrado Integrado em Engenharia Electrotécnica e de Computadores July 27, 2021
Resumo Comunicações rádio usando a Lua como repetidor de modo a permitir ligações de longa distância sem linha direta de vista (line of sight), contornando a curvatura da terra são já realizadas desde meados do século passado. Desde os inícios desta tecnologia, sempre foi necessário contornar a forte atenuação de espaço livre do sinal devido à enorme distância que a Lua se localiza e ao seu baixo albedo. Um dos métodos predominantes para tornar possível este tipo de comunicações é a transmissão de sinais de alta potência, que nos primórdios do Moonbouncing estava na ordem dos milhares de Watts, atualmente, com modulações mais complexas e recetores mais avançados é possível ser feita com apenas centenas de Watts, como demonstrado na secção de link budget do documento, continuando um desafio para entusiastas de Radioamadorismo. Esta dissertação aborda essencialmente o processo de desenvolvimento de um amplificador de potência capaz de produzir 200 W à frequencia de 2.4 GHz com a melhor eficiência e linearidade possíveis. Para conseguir concretizar o objetivo imposto, uma revisão do estado de arte na área de desenvolvimento de amplificadores de rádio frequência mostrou ser essencial, estabelecendo metodologias de trabalho e métricas para a análise desse mesmo tema. Foi ainda possível determinar que classe AB, classe F ou F inverso seriam as tipologias mais indicadas, permitindo altas potências sem sacrificar demasiado a eficiência em aplicações em que a linearidade do dispositivo não é crítica. Posto isto, o plano de trabalhos seguiu a forma canónica de desenvolvimento de amplificadores de potência deste tipo de classes, tendo por base o circuito exemplo presente na datasheet do dispositivo ativo escolhido. Em todo o processo de desenvolvimento foi usado o software Advanced Design System 2021 que tornou possível as várias análises do circuito do amplificador, aliado à ferramenta de simulação Momentum, ambas da Keysight Technologies, que permitiu a obtenção de modelos comportamentais mais fiáveis nas várias etapas de desenvolvimento, evitando surpresas do ponto de vista de performance após a implementação prática do amplificador. Diferentes pontos de funcionamento, biasing networks e matching networks foram experimentadas de modo a se obter um design estável capaz de cumprir o requisito mínimo de potência o mais eficiente possível, sendo na simulação eletromagnética final obtido o requisito mínimo de potência com PAE =51.6%. Na implementação prática o melhor resultado medido foi de 50.9 dBm de potência de saída com 45% de eficiência do PA à frequência de 2.35 GHz. Durante o processo de desenvolvimento foi essencial uma atitude de compromisso entre a eficiência, potência, estabilidade e linearidade do amplificador, sendo cada uma das etapas essencial para estabelecer o equilíbrio entre cada um desses fatores. i
Abstract Radio communications using the Moon reflection to overcome the Earth’s curvature in long distance communication have been in practice for more than 70 years. Since the beginning, a large signal attenuation due to the enormous distance the signal has to travel and the low albedo of the Moon, is a great challenge to beat. Usually to make this type of communication possible a great transmission power is required, made possible by the use of high power RF amplifiers. Initially, thousands of watts were required, but with the advances in modulation techniques and better reception systems, the transmitter power requirements go as low as hundreds of watts, as shown in the link budget section of this document, remaining, however, relevant problems to tackle amongst the Amateur Radio community. This thesis documents the development process of a Power amplifier capable of giving 200 W of power at 2.4 GHz with the best efficiency possible. To fulfill these goals, a revision on the state of the art of power amplifiers was made, establishing metrics and methodologies to use during the development. Furthermore, it was determined that a class AB, Class F or inverse class F would be the most interesting topologies, since they allow high power outputs without sacrificing the efficiency in application where the linearity is not critical. With this is mind, the workflow followed the standard development in this type of classes, using the circuit example present in the transistor’s datasheet as a starting point. During all process, the Advanced Design System 2021 software was the tool used, aided by the Momentum simulation system, also by Keysight, allowing the generation of more realistic models of the circuit’s behavior, thus, avoiding performance deviations at the implementation stage of the real device when compared to the results of the simulated model. Different bias points, bias networks and matching network configurations were tried in order to obtain a stable design capable of fulfilling the requirements. In the simulation of the last design the output power was Pout =53.25 dBm and with a power added efficiency of PAE =51.6% at 2.4 GHz. The best measured result for the PA were frequency shifted, with a Pout of 50.9 dBm and a PAE of 45% at 2.35 GHz. Throughout the whole process a compromise mentality between efficiency, power, stability and linearity of the amplifier was essential, balancing the different factors into the best performing circuit of the given application. ii
Acknowledgements While trying to remember everyone, I will start by giving a special thanks to my supervisor Hugo Santos that answered all my questions during the realization of this thesis and the necessary guiding directions to do so. A thanks to my co-supervisor Sérgio Cunha that was always a helping hand, especially in the last minute tests. The welcoming help from the Bexus team elements also needs to be recognized, specially from Tiago Martins and Bernardo Moreira. A thank you to all the people from which I keep good memories during my specialization years, particularly, Sérgio Gonçalves and Tiago Cunha. A special space in the acknowledgements should also be saved for my family, that always provided the support I needed during the elaboration of this thesis, as well as during the full 5 years of this degree. A thank you to all my "academic friends", all the 16 of you, for providing unforgettable stories during and after class, that made the university experience mean a lot more. Last but not the least important, I would like to thank my girlfriend Vitória for all the support provided, specially in the difficult days where things did not went according to plan, acting as my safe shelter. Pedro Teixeira iii
“Don’t believe everything you read on the internet just because there is a quote with a picture next to it” Abraham Lincoln iv
Contents Resumo i Abstract ii 1 Introduction 1 1.1 Context ....................................... 2 1.2 Motivation...................................... 2 1.3 Objectives...................................... 2 1.4 Structure....................................... 3 2 Literature review 4 2.1 LinkBudget .................................... 4 2.1.1 Antennatheory............................... 4 2.1.2 Friis transmission formula . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.3 Radarequation ............................... 7 2.1.4 Otherlosses................................. 8 2.1.5 Noisetheory ................................ 8 2.1.6 Synthetic aperture radar . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1.7 EMEmodulations ............................. 11 2.2 ActiveRFdeviceshistory.............................. 12 2.3 RFfundamentals .................................. 15 2.3.1 Two-Port Network Parameters . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.2 ImpedanceMatching............................ 17 2.4 Power Amplifier characterization . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.4.1 LoadPull.................................. 21 2.4.2 LoadlineTheory .............................. 21 2.4.3 Transistor operating point . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.4.4 Stability................................... 24 2.5 PowerAmplifiermetrics .............................. 27 2.5.1 AmplifierGain ............................... 27 2.5.2 Efficiency.................................. 28 2.5.3 Linearity .................................. 29 2.5.4 Gaincompression.............................. 30 2.5.5 Intermodulation Distortion . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.5.6 IP2andIP3 ................................ 32 2.6 Classes ....................................... 33 2.6.1 ClassABABandC ............................ 35 2.6.2 ClassD................................... 37 v
CONTENTS vi 2.6.3 ClassE ................................... 37 2.6.4 Class F and F-1 ............................... 38 2.7 Efficiencytechniques................................ 39 2.7.1 EnvelopeTracking ............................. 39 2.7.2 Envelope Elimination and Restoration . . . . . . . . . . . . . . . . . . . 40 2.7.3 LoadModulation.............................. 40 2.8 Power Amplifier Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.8.1 Push-Pull.................................. 41 2.8.2 MultistagePA................................ 41 2.9 State of the art high power amplifiers . . . . . . . . . . . . . . . . . . . . . . . . 43 2.10Proposedsolution.................................. 44 2.10.1 Link Budget Realization . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.10.2 Amplifiersolution ............................. 48 3 PA design steps and simulations 50 3.1 Activedevice .................................... 51 3.1.1 Active device selection . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.1.2 Active device interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.2 Layout generation and simulation . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.3 Operationpoint ................................... 54 3.4 Surroundingnetworks................................ 56 3.4.1 PowerDivider ............................... 56 3.4.2 Biasnetwork ................................ 59 3.5 Stability....................................... 61 3.5.1 Schematic simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.5.2 Layoutsimulations............................. 62 3.6 LoadPull ...................................... 65 3.7 MatchingNetworks................................. 69 3.7.1 Output matching network . . . . . . . . . . . . . . . . . . . . . . . . . 69 3.7.2 Input matching network . . . . . . . . . . . . . . . . . . . . . . . . . . 69 3.7.3 Finalmatching ............................... 70 3.8 Results........................................ 71 3.9 Monte Carlo Simulation and yield analysis . . . . . . . . . . . . . . . . . . . . . 72 3.10AM-PMdistortion ................................. 75 3.11Boardgeneration .................................. 75 4 PA practical validation 78 4.1 Implementation difficulties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 4.2 DCcharacterization................................. 80 4.3 Small signal measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 4.4 Large signal measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 5 Conclusions 94 5.1 Objectives accomplishment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 5.2 Difficultiesencountered............................... 94 5.3 Futurework..................................... 95 5.4 FinalRemarks.................................... 96 Bibliography 97
List of Figures 1.1 Earth Moon Earth link illustration at 2.4 GHz (adapted from [2])......... 1 2.1 Cascaded amplifier configuration [4,Chapter10] ................. 10 2.2 Power output to frequency [4,Chapter11]..................... 13 2.3 Different technology’s performance . . . . . . . . . . . . . . . . . . . . . . . . 15 2.4 Power amplifier simplistic model (image adapted from [18]) ........... 15 2.5 Two-Port power gains configuration, with S meaning source and L meaning Load [19,Chapter2] ................................... 16 2.6 S parameters for two-port networks. [20,ch3] .................. 17 2.7 Generic L-matching network sections (images adapted from [20, Chapter 5]) . . 19 2.8 Smith chart mapping from the Z plane [20, Chapter 5] . . . . . . . . . . . . . . 20 2.9 Adding components using ZY Smith chart. [20, Chapter 5] . . . . . . . . . . . . 21 2.10 Class A configuration [26,Chapter2] ....................... 22 2.11 Class A linear power amplifier with high and low resistance load [26, ch 2] . . . 22 2.12 Load–pull contours corresponding to a class B PA with output power (PStep =1 dB and PMax=55 dBm ) and efficiency (ηStep =5 and ηMax =78.5% ) [27] . . . . 23 2.13 I-V curve, defined as "soccer pitch" in [28]..................... 24 2.14 Two port network configuration [29,Chapter3].................. 25 2.15 Smith Chart with stable and unstable regions (left to right) in the ΓSplane [29, Chapter3]...................................... 26 2.16 1-db compression point representation[20,Chapter1]............... 31 2.17 Frequency spectrum of third-order non-linearity system with two-tone sinusoidal inputs [19,Chapter1]................................ 32 2.18 Intermodulation Distortion (IMD), IP2, IP3, and gain compression [19, Chapter 1] 32 2.19 Load lines and bias points for linear amplifiers [20, Chapter 1] . . . . . . . . . . 33 2.20 Class A, B, and C. typical configuration [20, Chapter 1] . . . . . . . . . . . . . . 34 2.21 AB amplifier excursion [20,Chapter1] ...................... 36 2.22AtoCclasscomparison .............................. 37 2.23 Class E simplified configuration [20,Chapter1].................. 38 2.24 Class E simplified configuration [20,Chapter1].................. 38 2.25 Envelope tracking behavior of DC voltage [33] .................. 39 2.26 Envelope tracking implementation [24,Chapter9] ................ 39 2.27 Envelope Elimination and Restoration implementation [31, Chapter 9] . . . . . . 40 2.28 Block diagram of the Doherty PA [24,Chapter9] ................. 40 2.29 Typical push–pull configuration [19,Chapter1].................. 42 2.30 RF performance of 500W AlGaN/GaN Vds=65V, Idsq=2.0A, Freq=1.5GHz [35] . 43 2.31 Interstage match for driver-PA [26,Chapter13] .................. 43 2.32 Approximation of the obtained SAR image . . . . . . . . . . . . . . . . . . . . 47 vii
Introduction 2 1.1 Context Although the usage of the moon to overcome the Earth’s curvature between two points is less and less relevant accounting the number of man-made satellites in orbit, the challenge continues to be very popular amongst the amateur radio community. With this in mind, the Faculdade de Engenharia da Universidade do Porto (FEUP)’s Núcleo de Radio Amador (Amateur Radio Organization) (NRA) is also trying to make EME communications with the available resources. The difficulty of using the moon as a repeater is clear once we analyze the simplified link of Figure 1.1. The emitted signal is highly attenuated due to the enormous distance from the Earth to the Moon and the low Moon albedo (6 to 7%). 1.2 Motivation To solve the high attenuation problem, several approaches can be taken: • Highly directive antennas; • Powerful transmitting amplifiers; • Very Low noise amplifiers; • Highly complex signal; • Narrow band signal. Given the fact that the most directive antenna available is only a 3 meter dish, and that, ideally, the projected system must be capable of both capturing radar images and performing Morse or voice point to point communication, efforts must be made to transmit high power, have a good reception system, and implement complex signals, that are associated with considerable processing gains. The purpose of this thesis makes part of the NRA to-do list, which includes the amplification task, i.e, design of a transmission amplifier chain with transmission power in the order of hundreds of watts, allowing the link to be possible. 1.3 Objectives Given the motivation, the objectives of this thesis are the following: 1. Design, simulation, manufacturing, and testing of a high power amplifier (greater or equal than 200 W) capable of operating in S or L band. 2. Design, simulation, manufacturing, and testing of a driver amplifier that is able to increase the power of a 20 dBm input all the way up to the required input power of the high power amplifier.
1.4 Structure 3 The success of this thesis is measured essentially by these objectives, where the first is seen as the minimum requirement. However, given the motivation of this thesis, the author considers the implementation of the amplifier chain in a moon bouncing application as a personal objective, proving the usefulness of the developed product. 1.4 Structure This document’s structure is divided by chapters, each one with its one purpose. In Chapter 1, it is explained the context, goals and motivation for this dissertation. In Chapter 2 there is a presentation of the state of the art. Firstly, a brief description of link budget theory and RF circuits fundamentals is provided, which will facilitate the characterization of the problem task. After that, the types, architectures and techniques associated with power amplifiers are presented and lastly, an evaluation of the link budget to clarify the definition of the problem. To close out the section, a solution to solve the problem is proposed. In chapter 3 the design of the amplifier is exposed where the several design steps where followed, with multiple design iterations until a circuit that fulfilled the minimal requirements was encountered, all this in simulation environment. Chapter 4 details the practical implementation of the developed design and its results, while comparing them to the simulations and other reference materials. In the last chapter (chapter 5) several conclusions are pointed out, as well as the future work to be done and possible improvements to the final product. A list of the reference material used throughout this thesis can be found at the end of the document.
Chapter 2 Literature review 2.1 Link Budget In this subsection, a brief explanation about the link budget related matters for an EME configuration will be presented. Initially, it is provided an explanation of antenna topics, followed by propagation loss concepts, radar theory, other losses and noise theory. 2.1.1 Antenna theory Antennas can be viewed as a converter of RF guided waves into a plane wave propagating in free space. This device is known to be bidirectional by nature so, it also has the capability to capture free space waves into guided waves [4, Chapter 14]. Without entering in details on Maxwell’s equations, Pozar shows that in the far-field of the antenna, the distance at which the ideal planar phase front of a plane wave, the direction of the energy flux, the radiated power, Prad, to the surrounding space can be written as Prad =Z2π φ=0Zπ θ=0 ¯ Savg ·ˆrr2sinθdθdφ=Z2π φ=0Zπ θ=0 U(θ,φ)sinθdθdφ(2.1) where ¯ Savg is the time-average Poynting vector, calculated from the Magnetic and Electric fields. And where U(θ,φ)is the radiation intensity in a given direction that is being integrated over a unit sphere. 2.1.1.1 Radiation Pattern [5] states that the radiation pattern is defined as "a mathematical function or a graphical representation of the radiation properties of the antenna as a function of space coordinates. In most cases, the radiation pattern is determined in the far-field region and is represented as a function of the directional coordinates. Radiation properties include power flux density, radiation intensity, field strength, directivity, phase or polarization". This way, the radiation pattern can be plotted 4
2.1 Link Budget 5 from the pattern functions, Fθ(θ,φ)and Fφ(θ,φ), that are present in the definition of the electric field and magnetic fields [4, Chapter 14]. 2.1.1.2 Directivity Directivity is defined "as the ratio of the radiation intensity in a given direction from the antenna to the radiation intensity averaged over all directions. The average radiation intensity is equal to the total power radiated by the antenna divided by 4π. If the direction is not specified, the direction of maximum radiation intensity is implied" [5]. Considering Umax as the maximum radiation intensity and Uavg as the overall average radiation intensity, we get equation (2.2). It can also be expressed in order of the radiated power, which is the integration of the radiation intensity of all space. D=Umax Uavg =4πUmax Prad =4πUmax Rπ θ=0R2π φ=0U(θ,φ)sinθdθdφ(2.2) 2.1.1.3 Radiation efficiency Radiation efficiency of an antenna is defined by "the ratio of the desired output power to the supplied input power" [4, Chapter 14]. ηrad =Prad Pin =Pin −Ploss Pin =1−Ploss Pin (2.3) With Prad as the power radiated by the antenna, Pin the power supplied to the input of the antenna, and Ploss, the power lost in the antenna. 2.1.1.4 Aperture efficiency Aperture efficiency, ηap, of an antenna is defined as "the ratio of the maximum effective area Aem of the antenna to its physical area Ap", where the maximum effective area is the maximum of the power delivered to the load divided by the power density of incident wave, from the reception point of view [5]. ηap =Ae Aph (2.4) Generically, the effective area (aperture), Aeis defined by [5] as “the ratio of the available power at the terminals of a receiving antenna to the power flux density of a plane wave incident on the antenna from that direction, the wave being polarization-matched to the antenna. If the direction is not specified, the direction of maximum radiation intensity is implied". Ae=Pr Sr (2.5)
Literature review 6 It is also shown that the maximum effective aperture of any antenna is related to its maximum directivity [5, Chapter 2]. Aem =ηrad λ2 4πDmax (2.6) 2.1.1.5 Gain and realized Gain Gain of an antenna is defined as “the ratio of the intensity, in a given direction, to the radiation intensity that would be obtained if the power accepted by the antenna were radiated isotropically. The radiation intensity corresponding to the isotropically radiated power is equal to the power accepted (input) by the antenna divided by 4π" [5]. This is typically referred as the relative gain because it is defined with respect to a reference, usually an isotropic antenna. G(θ,φ) = 4πU(θ,φ) Pin(lossless isotropic source )(2.7a) G(θ,φ) = ηrad 4πU(θ,φ) Prad =ηradD(θ,φ)(2.7b) Gmax =ηradDmax (2.7c) Taking equation (2.3) and (2.2) one can obtain (2.7a). When the direction is not stated, the power gain is usually taken in the direction of maximum radiation (2.7b). In [5] it is also defined another gain, the realized gain, Gre, that takes into account the reflection/mismatch losses (due to the connection of the antenna element to the transmission line that connects to it). Gre =G(1−|Γ|2)(2.8) In a perfect match to the transmission line, Γ=0, as it will be shown in the RF fundamentals section. In the mentioned case, the realized gain corresponds to the relative gain. Combining (2.7c), (2.6) and (2.6), one can also write the gain in terms of the physical area of the antenna Aphy. G=ηapηrad 4πAph λ2(2.9) 2.1.1.6 Equivalent isotropic radiated power EIRP is the power input that a lossless isotropic antenna would require to obtain the same maximum power density in the far-field of the antenna under test. Results from the product of the power input come in Watts (W), with the isotropic antenna gain. EIRP =P tGt(2.10) EIRP can be expressed in Watts, dB relative to one Watt (dBW) or relative to one milliwatt (dBm). For more details about this antenna subsection, consider that the literature used was [3–5] .
2.1 Link Budget 7 2.1.2 Friis transmission formula In a common configuration, the transmitter and the receiver are separated by a given distance Rwith Transmitter (TX) radiating according to its radiation pattern. If one assumes that the RF devices are pointed in their maximum directivity direction, and considering that an eventual misalignment is later compensated via a loss term, it can be said that the average power that reaches the receiver is the Equivalent Isotropic Radiated Power (EIRP) divided by spherical cap area at that distance. Another interpretation is the power density of an isotropic antenna at a distance R, times the gain relative to said isotropic antenna. [6], [4, Chapter 14] Savg =GtP t 4πR2W/m2(2.11) Taking in mind the definition of the effective aperture area, the power in the receiver can easily be given as Pr=AeSavg =GtP tAe 4πR2=GtGrλ2 (4πR)2P tW (2.12) From (2.12) one can derive the free space losses that express the attenuation effect of the power spreading across the space [4, Chapter 14] LFSL =4πR λ2 (2.13) 2.1.3 Radar equation When point-to-point communications are made possible by an intermediate passive reflector, it is fundamental to study the Radio Detection and Ranging (RADAR) equation. For this subject, refer to [3,4] for more information. The fundamental concept to be presented is the Radar Cross Section (RCS), which is defined as "the ratio of the scattered power in a given direction relative to the incident power density", and expressed in square meters. σ=Ps St m2(2.14) Taking equation (2.14) and considering that the transmitter power density at the reflector is just like in expression (2.11), the radar equation results in equation (2.15) Pr=P tG2λ2σ (4π)3R4(2.15) A useful rearrange of equation (2.15) can express the maximum distance an object can be positioned to make the link possible, expressing the maximum range, Rmax, of the system. Rmax =P tG2σλ2 (4π)3Pmin 1/4 (2.16)
Literature review 8 2.1.4 Other losses EME communication systems have losses associated with them that need to be taken into account [3]. One can notice losses regarding the antenna, related with the conductor and dielectric material. Losses regarding the network that connects the system to the antenna can be ohmic/dissipative or mismatch related [5]. Another loss can come from the fact that the antenna will most likely not be perfectly pointed in its maximum direction, suffering depointig loss, since the gain decreases as one moves away from the point of maximum. A last concern is that the received wave when crossing the ionosphere suffers from depolarization, meaning that some power will be transferred to the perpendicular polarization causing a degradation of the antenna’s gain, since the cross-polarization gain is usually inferior to the copolarization gain [5]. For more information about other losses associated with EME systems refer to [7, Chapther 3] and [3]. 2.1.5 Noise theory To understand the sensibility of a receiver, it is important to mention that it is essentially a competition with receiver noise signal. In a noiseless receiver, the minimum energy would be theoretically infinite [8]. The following analysis on noise theory was inspired in [4, Chapter 10]. 2.1.5.1 Noise temperature A given device can have various types of noise associated: thermal noise, resulting from the charges vibrating within the device, shot noise, flicker noise, plasma noise, and quantum noise. Typically, a RF system is dominated by what can be globally evaluated as white noise. A good modelling of a random noise source is the thermal noise of a resistor Rat a temperature T, with a measure of noise in a given bandwidth B, given by (2.17), where k=1.380×10−23 J/K is the Boltzmann constant. No =kT B (2.17) In a passive device, the equivalent noise temperature can then be calculated by (2.18a), which represents the temperature a resistor would have to be to produce the same noise power. Te=No kB (2.18a) Te=No GkB (2.18b) For an active device, one can isolate the noise from the device itself, creating a configuration where we have the noise source resistance followed by an ideal amplifier with gain G, thus the output
2.1 Link Budget 9 noise is the noise in (2.17) times the device gain. This way, its temperature has an extra Gterm in the denominator. 2.1.5.2 Noise figure Noise figure is another way to characterize a component. It is a measure of the degradation in the Signal to Noise Ratio (SNR) between the input and output of the component. F=Si/Ni So/No =1+Te T0≥1 (2.19) It can also be written as a relation of the device equivalent temperature and the input temperature, T0. The equivalent noise temperature Te, can also be solved in terms of F T0. In a noiseless network, F=1(0 dB), giving Te=0. Te= (F−1)T0(2.20) 2.1.5.3 Lossy medium The particular case of a signal across a lossy medium is of interest to study. The output power of said medium will be given by the sum of the output power, assuming a clean gain/attenuation, plus the thermal noise of the medium itself. This way, one can express No=kT B =GkT B +GNadded (2.21) And since the gain of said medium is less than one, G=1/L<1, the noise added is Nadded =1−G GkTB = (L−1)kTB . (2.22) With this in mind, one can say the output noise temperature is given by Tout =LTin +(1−L)T0.(2.23) An antenna is a particular case of a lossy device, so its temperature can be written as TA=Tb L+(L−1) LTp=ηradTb+(1−ηrad)Tp(2.24) where Tbis the brightness temperature, resulting of an integration of all the noise sources an antenna can see, and Tpis the physical temperature. Tb=R2π φ=0Rπ θ=0TB(θ,φ)D(θ,φ)sinθdθdφ R2π φ=0Rπ θ=0D(θ,φ)sinθdθdφ(2.25)
Literature review 10 2.1.5.4 Amplifier chain Considering two amplifiers in the configuration of figure 2.1, one can simplify it to a single Figure 2.1: Cascaded amplifier configuration [4, Chapter 10] amplifier, by summing Nowith amplified N1to get the new No, No=G2N1+G2kTe2B=G1G2kBT0+Te1+1 G1 Te2=G1G2kB(Tcas +T0)(2.26) where Tcas is the noise temperature of the cascade system, expressed as Tcas =Te1+1 G1 Te2(2.27) This analysis can be extrapolated to more stages getting the following noise figure, where one can easily identify that the first amplification level is the more critical, noise wise. Fcas =F1+F2−1 G1 +F3−1 G1G2 +··· (2.28) Tcas =Te1+Te2 G1 +Te3 G1G2 +··· (2.29) 2.1.6 Synthetic aperture radar A short overview of Synthetic Aperture Radar (SAR) will be given here, with special attention to range and azimuth resolution and compression gains. 2.1.6.1 SAR operation SAR is a variation of conventional RADAR that uses the motion of the radar antenna over a target region to achieve better spatial resolution than conventional beam-scanning radars. It does it by combining measurements of different positions with specific algorithms that enhance the data per target [9, Chapter 2]. 2.1.6.2 Fundamental variables In a SAR configuration several pulses of a given duration Tp, are transmitted with a pulse repetition frequency PRF, resorting to an antenna with area Aand side La. The received echoes are collected to be processed during an integration time, Ti[10, Chapter 1].
2.1 Link Budget 11 2.1.6.3 Azimuth resolution and Range resolution It is shown in [10, Chapter 4] that the maximum distinction in the direction of movement of the SAR antenna is given by δaz =La 2(2.30) In the same chapter, it is also shown that the range resolution in the direction perpendicular to the direction of the antenna, is given by δR=c 2B(2.31) being Bthe bandwidth of the signal, and cthe speed of light. 2.1.6.4 Processing Gain To better understand SAR processing gain related matter, please refer to [10, Chapter 7] where this section was inspired. The collected data is then processed by a series of algorithms that improve the Signal to Noise Ratio by combining the different echoes of the same location. This processing gain, Gproc, is a combination of the pulse compression gain, Gpulse , and the azimuth compression gain, Gazimuth . Gproc =Gpulse +Gazimuth (2.32) The pulse compression gain is given by the product of the signal length in time, Tp,, by its bandwidth B. Gpulse =TpB(2.33) The azimuth compression gain, Gazimuth is given by the Pulse Repetition Frequency (PRF) multiplied by the Radar Integration Time, Ti Gazimuth =TiPRF (2.34) 2.1.7 EME modulations EME signals are always weak, so modulations need to be chosen in order to get the best out of it. As stated in [11] On-Off Keying (OOK), Morse code is an excellent general purpose communication mode that performs well in weak signal conditions. Some operating procedures for Continuous Wave (CW) consist on repeating the message so that fragments of the message can be reassembled. In the late twentieth century, digital modulations were popularized. In these modulations there is redundancy, that is sent along with the message. That redundancy associated with Error Correcting Codes (ECCs) was proven to be way more efficient than the simple repetition used in Morse.
Literature review 18 infinitesimal contributions of pieces with length δz, one can extract the travelling wave solutions of the line that tell us the voltage and current at any point of the line in terms of the incident (+) and returning (-) voltages and currents, with γbeing given by expression (2.41) V(z) = V+ 0e−γε +V− 0e+γz(2.40a) I(z) = I+ 0e−π+I− 0e+γx(2.40b) γ=α+jβ=p(R+jωL)(G+jωC)(2.41) One can also express the characteristic impedance, Z0, as presented in equation (2.42). Z0=R+jωL γ=sR+jωL G+jωC(2.42) In [20, Chapter 5] it is also shown a fundamental concept of RF circuits. A transmission line with characteristic impedance Z0, terminated with a load ZL, presents a relation of the incident and reflected wave in terms of both impedances, being that relation the reflection coefficient of the load ΓL(in this case). V− 0 V+ 0 =ZL−Z0 ZL+Z0=ΓL(2.43) The power delivered to the load can then be calculated with the reflection coefficient (2.44), that in a perfectly adapted load is one, resulting in a maximum of the delivered power of (2.45), which is the same as one half of the voltage times current at a given time. Pavg =1 2V+ 0 2 Z01−|ΓL|2(2.44) Pmax =1 2V+ 0 2 Z0 =1 2VdcIdc (2.45) At last, a fundamental result is how the input impedance of a line with length lwith a given impedance and a load impedance is calculated. Zin (z) = Z0ZL+Z0tanh(γl) Z0+ZLtanh(γl)(2.46) From this expression, many others can be derived exploring limit cases, for example, using open or short circuit loads, or using multiples of quarter, half, and eighth wavelength lengths. In [19, Chapter 8], various techniques that resort to distributed elements are shown, being one example commensurate lines, lines with length λ/8, resulting in an inductive behavior when short circuited, and a capacitive behavior when the load is open.
2.3 RF fundamentals 19 Another particular case is when quarter wave length lines are used, if one considers a lossless line, γ=β=2π/λ, resulting in βl=π/2. Zin =lim βl→π/2Z0 ZL+iZ0tan(βl) Z0+iZLtan(βl)=Z0 iZ0 iZL =Z2 0 ZL (2.47) The typical process to adapt a load is, firstly, to separate the load by a transmission line with a given length so that the input impedance of load plus line is purely real, and then a quarter wave length line with a specific impedance Z0is chosen so that the input impedance of the whole system is the required [24, Chapter 5]. 2.3.2.2 Impedance Matching Network To match different impedances, the most common method is the use of L-matching networks that, depending on the needed adaptation, can take eight configurations. These eight configurations take capacitances and inductors that can be both in series and parallel. The inductive and capacitive elements can be implemented via short circuit or open circuit transmission lines or lumped elements. Figure 2.7: Generic L-matching network sections (images adapted from [20, Chapter 5]) 2.3.2.3 Biasing circuits and networks To impose the operation point of a PA, one needs to impose two voltages, the gate and drain voltages, maintaining them stable for the device operation to be the projected one. The simplest biasing for a power MOSFET device is to use the potentiometer-type voltage divider for the gate bias, with a choke inductor in the drain circuit. To reduce the current across the resistor divider, it is common to use a diode [19, Chapter 1]. When a bipolar device is used, another problem rises, related to its thermal shift of the threshold voltage, that is much more notorious than with MOSFET. In the junction case, temperature compensation circuits must be used. To ensure that the bias points are kept stable, the bias network should allow the Direct Current (DC) to pass to the gate and drain off the transistor, while preventing RF signals from leaking through it, presenting a high impedance at the fundamental frequency. In [25] the RF choke was made possible by two radial stubs that ensure a short circuit at fundamental and second harmonic frequencies, followed by a quarter-wavelength line added to create an open circuit at the fundamental and, therefore, a short circuit at second harmonic. DC
Literature review 20 block capacitors were also used before the input and output, making sure that only RF signal crosses. 2.3.2.4 Smith Chart Before continuing with further subjects like stability and load pull, an explanation on what is the Smith chart concept and its usefulness must be made. The Smith Chart is a graphical method proposed by Phillip Hagar Smith. It provides a graphic of displaying impedances and all related parameters using the reflection coefficient. For the Smith Chart to be used, normalized impedances must be applied [20, Chapter 5]. zL=ZL Z0 =RL+jXL Z0 (2.48) Remembering the reflection coefficient formula (2.43), where ΓLis an imaginary number that can be written as follows ΓL=|ΓL|e6ΓL=ΓLr +jΓLi (2.49) Equation (2.43) can be rewritten in terms of ZL ZL=Z0 1+ΓL 1−ΓL (2.50a) zL=rL+jxL=ZL Z0 =1+ΓL 1−ΓL (2.50b) As shown, one can represent the load in terms of the reflection coefficient. In [20, Chapter 5] it is referred that one can map the imaginary plane, Z, into a Γplane, as suggested in 2.8 with centers rL 1+rL,0for the real part, and 1,1 xLfor the imaginary part. Some of the properties that can be Figure 2.8: Smith chart mapping from the Z plane [20, Chapter 5] spotted in figure 2.8 and are worth noticing are that r-circles, centered in the real part of Γ, become progressively smaller as r increases from 0 to ∞, all passing (Γr=1,Γi=0)point. The centers of all x-circles lie on the Γr=1 line, those for x>0 (inductive reactance) lie above the Γr-axis, and those for x<0 (capacitive reactance) lie below the Γr-axis, becoming
2.4 Power Amplifier characterization 21 progressively smaller as ΓxL increases from 0 to ∞, ending at the (Γr=1,Γi=0)point for an open circuit and being the Γraxis when x=0. An analogous analysis can be made for admitances, obtaining a mirrored version of 2.8. Combining both can be a useful way to study circuits with series and parallel elements, as one can simply start from a given point in the chart and move/rotate according to the circles as suggested in 2.9. Figure 2.9: Adding components using ZY Smith chart. [20, Chapter 5] 2.4 Power Amplifier characterization 2.4.1 Load Pull As explained in section 2.3.2, to get the most of the active device, a matching network must be built in order to match both the source and the load. However, in the past it was particular difficult to predict the exact value of the power match impedance at RF, and microwave frequencies and was regarded as something which could only be measured experimentally [26, Chapter 2]. Two mechanical tuners would be connected to the input and output of the Device Under Test (DUT), varying the source and load impedance while measuring the network parameters, this way giving a practical measurement of the device’s behavior. Nowadays, this technique, associated with CAD tools, remains a great way to measure devices, providing accurate and extensive load pull data that can be used to design the amplifier itself, or to confirm the nonlinear data that might be provided by the manufacturer [19, Chapter 3]. To understand how load pull works, one must first understand Loadline theory. 2.4.2 Loadline Theory Considering a highly idealized model of the transistor represented on figure 2.10b, and assuming that the device is operating over the ideal model presented in 2.10a, in a way that it has a linear
Literature review 22 response in all input signal swing, i.e., a class A amplifier. If the load is matched for maximum power (2.45), one can calculate the optimal resistance for maximum delivered power with: Ropt =Vdc Imax 2 =Vdc Idc (2.51) Assuming a factor p, such that the obtained power PRF is equal to POPT /p, one can get two (a) Ideal strongly nonlinear device model. (b) Linear power amplifier Figure 2.10: Class A configuration [26, Chapter 2] results for the possible solutions that give the said power. Maximizing the voltage and minimizing current when the resistance is high, RHI, and the other way around when the resistance is low, RLO, as presented in figure 2.11. Figure 2.11: Class A linear power amplifier with high and low resistance load [26, ch 2] The same rationale can be used taking into account a load with a generic impedance with both imaginary and real parts, being that a phase difference will be introduced between voltage and current. The rest of the ellipsoid like shape will have RLO ±XMin the extremities, being XMthe maximum reactance for the defined pfactor [26, Chapter 2].
2.4 Power Amplifier characterization 23 This way, several ellipsoids can be drawn centered at the optimum load with a "radius" depending on the pfactor, being that the further away from the optimal point the less power is delivered to the load. The measured curves tend to be more oval compared to the proposed ideal model once they are measured in a real device with a behavior that is not the same as the model in figure 2.10a. In the previous analysis, it was assumed a class A amplifier, the canonical configuration for PA, known for its low efficiency, as will be presented in section 2.6. If one wants to analyze the efficiency contours in the Smith Chart, just like in the maximum power case, the efficiency evolution with respect to load must be evaluated. [27] reviews Cripps’ efficiency load–pull contours. From the DC power consumption, (2.52), one can derive the drain efficiency dividing the output power by (2.52), obtaining (2.53). Pdc =VDDI0=1 πVDDImax =2 πVDD VDD −Vk |ZL|(2.52) η=π 4 RL |ZL| VDD −VK VDD =π 8 RLIMax VDD (2.53) The same reasoning can be made to draw the efficiency contours that can be plotted in the same Smith Chart as the maximum power ones. Figure 2.12: Load–pull contours corresponding to a class B PA with output power (PStep =1 dB and PMax=55 dBm ) and efficiency (ηStep =5 and ηMax =78.5% ) [27] Analyzing 2.12, one can see that the optimal point in terms of efficiency usually differs from the output power one, so a compromise must be made depending on the application. In this thesis, this analysis is very useful since a high power good efficiency PA is the objective.
Literature review 24 2.4.3 Transistor operating point The fundamental behavior of a transistor based amplifier can be characterized by two main factors regarding the input voltage, output current relation. Firstly, the behavior of the device itself can be characterized by its I-V curve. One can identify the middle rectangular zone where signal clipping, compression and other nonlinear distortions do not occur, at least compared to what happens outside this region, as stated by [28]. In the graphic 2.13 one can see the knee voltage (Vk), the breakdown voltage (VBR) that Figure 2.13: I-V curve, defined as "soccer pitch" in [28] limits the "pitch". The horizontal axis corresponds to the gate-to-source pinch off voltage (Vpo) and the maximum current (Imax) can also be identified in the m1 marker. The spacing of the I-V curves for different values of Vgs is related to what is called the transconductance (gm≈∆lds/∆Vgs), the intrinsic gain of the device. In 2.13 it is also shown in the grey and blue doted line possible operation points for the transistor, which along with load matching, define the class of the amplifier. The gray line is related to class A amplifiers and the blue line to class B amplifiers. More on this will be presented in section 2.6. 2.4.4 Stability The tendency of an amplifier to oscillate must be a key aspect to take into account when designing an amplifier. In RF amplifiers, residual oscillations are pretty common due to transistor feedback, meaning that the load isolation can be imperfect, and due to path delays that can create situations of instability. This way, a minor signal could keep being amplified until it reaches a power that cannot be dissipated, potentially damaging the system [29, Chapter 3]. As mentioned by Gonzalez, to have an oscillation in a two-port network one must have a negative resistance port, which can be defined in terms of the reflection coefficient magnitude of
2.4 Power Amplifier characterization 25 the input and output of the network. Therefore, the unstable case is obtained when |ΓIN |>1 or |ΓOUT |>1, results that can be easily spotted in the Smith Chart. Figure 2.14: Two port network configuration [29, Chapter 3 ] If one remembers how to calculate ΓIN and ΓOUT , it is easily identified a dependence of the input and output reflection coefficient on the load and source matching networks, respectively. This way, two situations might occur: either the system is unconditionally stable, meaning that |ΓIN|<1 and |ΓOUT |<1 for |ΓS|<1 and |ΓL|<1; or the system is conditionally stable, meaning that |ΓIN|<1 and |ΓOUT |<1 is only verified for some passive source and load impedances. ΓIN =S11 +S12S21ΓL 1−S22ΓL (2.54) ΓOUT =S22 +S12S21ΓS 1−S11ΓS (2.55) 2.4.4.1 Stability circles Taking equation (2.54) and (2.55), applying the conditions |ΓIN |=1 and |ΓOUT |=1 and rearranging some terms, one can obtain stability boundaries, stated as circles [4, Chapter 12] |ΓL−CL|=rL |ΓS−CS|=rS (2.56) where CLand CSare the center and the rLand rSradius of the circles are calculated by the following expressions, where |∆|=|S11S22 −S12S21|. CL=(S22−∆S∗ 11)∗ |S22|2−|∆|2rL= S12S21 |S22|2−|∆|2 CS=(S11−∆S∗ 22)∗ |S11|2−|∆|2rS= S12S21 |S11|2−|∆|2 (2.57) These circles are obtained as a limit condition, so after they are drawn, one should identify which side of the boundary is stable, both for the ΓIN and ΓOUT . Taking in mind that when Zs=Z0, meaning ΓS=0, ΓOUT can be evaluated at the center of the Smith Chart. So the equation (2.55) can be calculated as simply as |ΓOUT |=|S22|. This way, to determine if the center of the ΓOUT chart is stable, one only checks if |S22|<1, being unstable if otherwise.
Literature review 26 The same rationale can be made for ΓIN with ΓS=0 and evaluating |S11|. An example of the ΓScircles can be seen in figure 2.15. . Figure 2.15: Smith Chart with stable and unstable regions (left to right) in the ΓSplane [29, Chapter 3] Other important aspects to be taken into account relating stability are that, to have an unconditionally stable system, the stability zone must cover the entire Smith Chart. In other words, ||Cs|−rs|>1 for |S22|<1 (2.58) and ||CL|−rL|>1 for |S11|<1 (2.59) being evident that, to have an unconditionally stable system, one must have |S11|<1 and |S22|<1, because the termination ΓL=0 or ΓS=0 will produce |ΓIN|>1 or |Γour |>1. 2.4.4.2 Stability tests Taking into consideration what was just said in the previous section, formal methods have been proposed to calculate the potential stability of an amplifier. K−δtest shows that a device will be unconditionally stable if Rollet’s condition (2.60) is met, having in mind that |∆|= |S11S22 −S12S21|as defined before, should be less than one. K=1−|S11|2−|S22|2+|∆|2 2|S12S21|>1 (2.60) An alternative also mentioned in [4, Chapter 12] involving a single parameter is the µtest, that tells that an amplifier is stable if (2.61) is met. µ=1−|S11|2 S22 −∆S∗ 11+|S12S21|>1 (2.61)
2.5 Power Amplifier metrics 27 Both tests are necessary and sufficient to prove unconditional stability, but the µtest has the advantage of measuring said device stability by how much larger than one the µvalue is, allowing comparisons between different devices to be made. Important to notice that if the test fails, circle analysis must be made. Stability depends on the frequency being analyzed, since the matching network has a frequency dependent impedance and new tests must be made if the analysis frequency is changed. 2.4.4.3 Maximum stable gain In a perfectly isolated amplifier, with S12 =0, to obtain maximum gain, one must have conjugate matching networks, Γin =Γ∗ Sand Γout =Γ∗ L. In this case, one is set to obtain the maximum possible gain, also known as matched gain, in an unconditionally stable device. GTmax =|S21| |S12|K−pK2−1(2.62) A more relaxed definition is the maximum stable gain, applicable to every device, not needing to be unconditionally stable [4, Chapter 12]. Gmsg =|S21| |S12|(2.63) 2.5 Power Amplifier metrics In order to measure the performance of an amplifier, one must review how those metrics are defined and what exactly do they measure. 2.5.1 Amplifier Gain Remembering the configuration of figure 2.1, one can deduce several expressions relating the the power transference along the system, in terms of the scattering parameters and the reflection coefficients at the interfaces [29, Chapter 3]. Transducer Power Gain (GT), the most used definition depending on both load and source impedance, ZLand ZS, relates the gain from source to load. A special case is when the load isolation scattering parameter is negligible. Thus, S12 is taken as zero representing the unilateral transducer power gain. GT=PL PAVs =power delivered to the load power available from the source (2.64)
Literature review 34 Figure 2.20: Class A, B, and C. typical configuration [20, Chapter 1] The calculation of these coefficients goes as follows Io=1 TZT/2 −T/2 iD(t)dt Ian =2 TZT/2 −T/2 iD(t)cos(kωot)dt Ibn =2 TZT/2 −T/2 iD(t)sin(kωot)dt (2.86) so considering the iD=IDC +Imcos(θ), one can, in a class A amplifier, get a I0=IDC,Ia1=Im with remain coefficients of a and b being zero [20, Chapter 1 ]. One can then calculate the class A DC power, Pdc, and the output power of the fundamental Pout , assuming that the drain to source voltage can be neglected, compared to the DC voltage. Pout =1 2Re[V1I∗ 1] = 1 2VdcIm(2.87) Pdc =V0I0=VdcIdc (2.88) The same rationale can be made having in mind the conduction angle, reaching more generic expressions by dividing Pout by Pdc, getting (2.84) resulting in 50% for the class A configuration. In [31, Chapter 2] it is also mentioned that DC and fundamental powers depend on the conduction angle. Pout =1 2Vdc Imax 2π 2θ−sin(2θ) 1−cosθ(2.89) Pdc =Vdc Imax π sinθ−θcosθ 1−cosθ(2.90) Another detailed approach to get the same result is stated in [19, Chapter 1 1], the known picewiselinear approximation. Writing the output current as a function of the input voltage i(t) = f[v(t)] (2.91)
2.6 Classes 35 Assuming a signal excursion like (2.85) that goes past the pinch off point Vp, one can write i=(0vin ≤V gmvin −Vpvin ≥Vp (2.92) Taking the conduction angle as θaccording to cosθ=−Vbias −Vp Vin , one can get that (2.92) can be rewritten as i(ωt) = (Iq+Imcosωt−θ≤ωt<θ 0θ≤ωt<2π−θ(2.93) Calculating the (2.86), they can be rewritten in terms of the output current amplitude Im. In=Imγn(θ)for n=1···nwhere Im=gmVin (2.94) γ0(θ) = 1 π(sinθ−θcosθ) γ1(θ) = 1 π(θ−sinθcosθ) γn(θ) = 1 πhsin(n−1)θ n(n−1)−sin(n+1)θ n(n+1)i (2.95) being that the γcoefficients can be solved in terms of the conduction angle, one can derive again the efficiency formula as (2.96), where ξ=Vm Vcc . η=P P0 =1 2 Im Iq Vm Vcc =1 2 Im Iq ξ(2.96) 2.6.1 Class A B AB and C As already detailed before, the distinction between these three classes is the selection of the operating point. The bias point in the class A mode of operation is selected at the center of the I–V curve between the saturation voltage and the maximum operational transistor voltage, giving a DC current between 0 and the maximum allowable current. With a 2πconduction angle and a constant quiescent current, even when no current is being applied, the maximum efficiency is only 50% [20, Chapter 1 ]. For class B, the biasing point is such that the transistor is turned on only one-half of the cycle θ=π. One can calculate its efficiency by (2.96) or (2.84), giving η=π/4=78.53%. Since half of the signal is cut, harmonic generation occurs. When compared to a class A amplifier, class B requires twice the amount of the voltage swing at the gate of the transistor, i.e., reducing the gain to half. Another important aspect is that the transistor only imposes the shape of the voltage and current waveforms while on. When it is off, it is the external passive circuitry that determines the shape of current and voltage, and their overlap, meaning that the external passive circuitry will be a main factor to impose a device’s efficiency [31, Chapter 2].
Literature review 36 Class AB does a compromise between efficiency and linearity, having better efficiency but worst linearity and gain compared to class A, and the opposite compared to B. Such occurs because the conduction angle stays between πand 2π. Figure 2.21: AB amplifier excursion [20, Chapter 1] Sliding the operating point Nin 2.21, one gets the behavior of A, B or AB. Moving this point horizontally, one gets different values of β. This angle is directly related to the equivalent load resistance RL, where V=Vmis the modulation voltage. tanβ=I V(1−cosθ)=1 γ1RL (2.97) The load resistance at the fundamental frequency can be further calculated by the ratio of output voltage and current [19, Chapter 1], that has an equivalent form in [31, Chapter 2]. RL(θ) = Vm γ1(θ)Im (2.98a) RL=VDD I1 =2πVDD Imax 1−cos(θ/2) θ−sin(θ)(2.98b) Class C, as indicated in figure 2.19, has a bias point below the pinch-off level so that it conducts less than 50% of the time, resulting in a higher efficiency, but lower linearity and lower gain. An overview of the normalized behavior of these classes can be seen in figure 2.22a, where it is evident that the most adequate choices for this thesis purpose are Classes B and AB, where the output power is larger with a decent efficiency 2.22a. The linearity gets worse once we reduce the angle of conduction, noticeable by the increase in the number and power of the harmonics 2.22b. Another graphical result presented in [31, Chapter 2], is that the optimal load resistor has a minor
2.6 Classes 37 decrease from A to B and then an exponential growth from B to C, a consequence of the (2.98b) equation. (a) A to C performance curves [31, Chapter 2] (b) Fourier analysis of the drain current [31, Chapter 2] Figure 2.22: A to C class comparison 2.6.2 Class D Class D amplifiers can operate in two modes, either in Voltage Mode (VM), a configuration that uses a series resonator, or Current Mode (CM), a configuration that uses a parallel resonator circuit. A typical VM configuration is implemented with two complementary transistors, PMOS and NMOS for example, being that each transistor will conduct half the time, actively switching on and off [20] so they can, in theory, obtain 100% efficiency. However, because of the parasitic capacitances on the switches, this implementation is tricky to do at higher frequencies. The efficiency also gets degraded due to power dissipation in the switches. In [20] is also shown that Class S is a variation of the class D, where all the signal amplification is made digitally with a modulator and a demodulator before and after the active element. 2.6.3 Class E Continuing the rationale, one can theoretically get 100% efficiency by using switching. To overcome the parasitic inconvenience, one can use the aforementioned parasitic in the tuning network resulting in 2.23, with a single transistor that acts as a switch S, RF choke, a parallelconnected capacitance Cp, a resonator circuit L–C, and a load RL. The resonator circuit and Cp make sure that the sinusoidal output continues when the switch is off. This simple topology is compatible with high frequency operation obtaining high efficiency, that can be justified by the fact that no overlap of transistor current and voltage curves is present, the efficiency of this idealized case is 100% with relatively low gain [32].
Literature review 38 Figure 2.23: Class E simplified configuration [20, Chapter 1] Figure 2.24: Class E simplified configuration [20, Chapter 1] 2.6.4 Class F and F-1 The principle of class F is the same as class E, to minimize the overlap region between voltage and current, reducing the transistor power dissipation. The goal is accomplished by the multiresonant load network in the class F amplifier, that helps to control the harmonic contents of the drain voltage and current. In this configuration all, even harmonics, are short circuited. Conversely, an open circuit is presented to all odd harmonics, while allowing power flow to the load only for the fundamental. This operation results in a voltage that is shaped towards a square wave, and a drain current that is shaped towards a half-sine wave in a phase opposition [20, Chapter 1]. This conceptually simple topology suffers from what class E solved. Once again, the parasistics complicate the design and reduce the efficiency [32]. It is important to notice that the inverse Class F is also a common topology. This time, the resonant behavior towards odd and even harmonics is reversed, compared to Class F. This results in a voltage square wave and half sinusoidal current. The short circuit and open circuit are commonly obtained with quarter wavelength lines, as a RF choke in the class F and in series with the load in the inverse class F, both of which can rise problems of implementation once these lines do not present their ideal behavior [32].
2.7 Efficiency techniques 39 2.7 Efficiency techniques To obtain a PA with good efficiency, one must choose an adequate class, however the solution is not that simple. Power amplifiers only give maximum efficiency at a single power level, usually around the maximum rated power of the device. As the input gets lower the efficiency also drops fast, increasing the heat dissipation [26, Chapter 10]. To solve this problem, two approaches can be made, either the DC supply changes with the demand of the input signal or the load is the one that changes. To control Vdc, a sensing mechanism must exist for the amplifier to know when to shift. Effectively, the load line stays with the same slope, because the load is supposed to be the same, and it slides horizontally towards minor values if needed. 2.7.1 Envelope Tracking Envelope tracking can be easily understood analyzing figure 2.25. When non-constant envelope signals are used, the amplitude variations must be preserved, since these effectively contain the information. As shown in the image, when the input signal gets low so does the DC power, this way the ratio between the DC power and the amplified signal stays more or less the same, independently of the signal envelope. Figure 2.25: Envelope tracking behavior of DC voltage [33] To implement the configuration presented above, one must include, besides the envelope tracker, a time delay Td, to make the DC/DC converter react in time. Figure 2.26: Envelope tracking implementation [24, Chapter 9]
Literature review 40 2.7.2 Envelope Elimination and Restoration Analyzing the name of the technique and 2.27 the way the technique works comes naturally. Firstly, the input modulated RF signal is split. One branch goes into an envelope detector, extracting the envelope, and the other branch goes through a limiter, creating a phase modulated signal. Those two signal feed a switching amplifier, Class D to F, with high efficiency, obtaining the amplified signal [24, Chapter 9]. Figure 2.27: Envelope Elimination and Restoration implementation [31, Chapter 9] 2.7.3 Load Modulation Solutions to implement load modulation have already some history. The Doherty amplifier was first proposed in 1936 [34], and remains a popular solution to the Load modulation technique. Figure 2.28: Block diagram of the Doherty PA [24, Chapter 9] The Doherty architecture is composed by two amplifiers: the carrier/main and the peaking/auxiliary, connected by a quarter-wavelength transmission line.
2.8 Power Amplifier Architecture 41 The principle of operation is impedance modulation. The load impedance of a current source can be modified by applying a current from another current source. In [26, Chapter 10] is shown that the effective output impedance of one device can be modified by the driving signals phase and magnitude, according to (2.99). Z1=RL1+I2 I1(2.99) The main amplifier, typically class AB or B, is active at low input signal amplitudes, and reaches the compression point when larger signals are presented. At this point, the auxiliary PA, typically a Class C, turns on, injecting current into the inverting network and causing the impedance seen by the carrier to decrease. With this, the load line slope of the main amplifier increases, keeping near saturation for higher input power levels, increasing its efficiency for a larger range of output power. 2.8 Power Amplifier Architecture Previously on this thesis, the term PA was mainly referred as a single stage based amplifier with a single transistor. However, any practical implementation is made possible with multiple transistor configuration. Some of these configurations are the push-pull power combining, and multistage amplification, that will be discussed now, that can increase the overall output power of the system [26, Chapter 13]. 2.8.1 Push-Pull Push pull configuration, a type of power combining, is commonly used in situations where low distortion, high efficiency and high output power are required, being mostly used in frequencies up to the GHz mark [18, Chapter 13]. The signal to be amplified is first split into two identical signals 180° out of phase. This splitting can done using an input coupling transformer, as shown in 2.29. The split signals are then fed to each transistor, being that each one of them is active half the time. The balanced circuit created by the two identical transistors and the phase deviation create a virtual ground that helps with stability and gain [19, Chapter 1]. This concept can be applied from Class A to Class C, being used to cancel out even harmonics reducing distortion [24]. In [26, Chapter 13] is also referred the balanced amplifier configuration, that uses a 90° phase difference, that has the same principle as push pull but with the advantage of improving interstage matching, being a good solution for narrowband applications. 2.8.2 Multistage PA A general approach to achieve high gain systems, is to divide the amplification process into steps. The signal before getting to the last output stage where the output power meets the requirements, goes first to stages that "prepare" the mentioned signal to be amplified. As shown in
Literature review 42 Figure 2.29: Typical push–pull configuration [19, Chapter 1] 2.30, where a Class E amplifier was developed, the output power gain relative to the input power remains more or less constant. Such thing does not happen with the efficiency that is optimal at greater values. This conclusion can be generalized and has particular importance when no efficiency techniques are used. This way it is common for a High power PA to have multiple stages, namely, driver or predriver, and driver followed by an output stage thus, dividing the problem into smaller problems and optimizing efficiency. The linearity of the driver is usually correlated with the linearity of the desired product. When nonlinear amplifiers are acceptable, and the PA stage is a saturated design, one could use a non linear driver stage. However, since the driver has a low impact on the overall efficiency when there is a PA stage with over 10 dB power, this driver chain can be implemented using linear design and improving the overall gain up to 40 dB [26, Chapter 13]. One important thing to notice is that active device adaptation and DC isolation blocking capacitors just like in 2.31 still need to be present. The design of the interstage match between a driver and PA stage can be just as challenging as the matching of the load itself, being sometimes neglected.
2.9 State of the art high power amplifiers 43 Figure 2.30: RF performance of 500W AlGaN/GaN Vds=65V, Idsq=2.0A, Freq=1.5GHz [35] Figure 2.31: Interstage match for driver-PA [26, Chapter 13] 2.9 State of the art high power amplifiers To understand the state of the art regarding high power amplifiers some research was done, obtaining the following values where CW stands for continuous wave operation. As one can see, Frequency [GHz] Output Power [W] PAE [%] Mode Reference 2,3 150 54 Pulsed [36] 2,8 100 58 Pulsed [37] 1,5 500 49 Pulsed [35] 1,3 1000 501Pulsed [38] 2,6 95 72 Pulsed [39] L-Band 360 65 Pulsed [40] 1,575 300 44 CW [41] Table 2.1: State of the art high power amplifiers many solutions have already been proposed in the 100 W range. By investigating these references, one can see that the ones with greater power used some type of power amplifier architecture as described in the previous section, being this an indicator that this thesis design should use it too. 1The only efficiency mentioned in this article was the 50% drain efficiency
Chapter 3 PA design steps and simulations The main goal of this thesis was to design a high power amplifier (greater or equal than 200 W) capable of operating in S or L band. In the previous chapters, it was concluded that the operation frequency to be used would be 2.4 GHz with the best possible efficiency, ideally over 50% with little restrictions regarding the bandwidth and linearity. In this chapter, the several steps necessary to develop a good performing amplifier are described. Starting with the active device section, where the device is selected and it is explained how the device model is included in the following simulations. Then, the operation point of the chosen device is studied, followed by the development of the surrounding networks of the active device, mainly power splitter, power combiner and bias networks, responsible to enforce the correct behavior of the circuit at the bias point. A stability analysis is the next step in the process, where it is tested if the system is stable in a small and large signal operation. Adjustments to the surrounding networks to stabilize the system are made, creating the necessary conditions to inspect what is the optimum load to present to the device’s output and input in order to maximize efficiency power and gain wise, a process commonly called Load Pull. Given the desired output and input impedances, one must create a matching network capable of adapting the 50 Ωports into the required impedances at the various harmonics. To top off the design process, a detailed performance characterization of the device is made in the last section. Some mistakes were made during the developing process, which forced the repetition of most of the design process. Despite the fact that most of the presented results and details about the development process contemplate the final iteration, occasional descriptions of the former attempts will be done, focusing on the errors made and on why they were important to overcome. 50
3.1 Active device 51 3.1 Active device 3.1.1 Active device selection To begin the design process of a power amplifier, the active device selection must be the first step. After the selection is made, a simulation model can be obtained from the manufacturer’s design support. The selection process took into account three main factors: the selected device should be capable to output at least 200 W of power; the operation frequency of the amplifier should cover the 2.4 GHz, and it should be an economic solution since this project has a limited budget. Searches on multiple vendors revealed that the BLP2425M10S250P power LDMOS transistor by Ampleon is suitable for applications of up to 250 W at frequencies from 2.4 GHz to 2.5 GHz [51]. Despite the fact that Laterally Diffused MOSFETs technology is not the best power density wise, the selected transistor manifested promising results in the datasheet with drain efficiency of 66.5% in the continuous mode and 67.5% in a pulsed mode with a duty cycle of 10%. It is important to also point out that this results were obtained by the producer having a gain of 16.4 dB at 2.45 GHz. So it is expected to have a slight performance degradation when operating at 2.4 GHz, since one is operating on the edge of the suitable frequencies. The device has a double transistor configuration being the source terminal shared and accessible at the bottom part of the piece, maximizing the contact to the ground plate where it will be mounted. Besides that, it has four more pins being the two gates and two drains, as one can see in figure 3.1a. Regarding the thermal terminal T in figure 3.1b not much information was (a) Transistor outline (image adapted from [51]) (b) Transistor model symbol Figure 3.1: Transistor ports found. Documentation regarding the ADS model was not available and the design support team by Ampleon was not very helpful when contacted.
PA design steps and simulations 52 The only information found was on a model of the transistor for the Microwave Office software by Cadence, that stated that the "T_ext" is the thermal node of the device and should be connected to ground or used in thermal networks [52]. Since no documentation was provided for the ADS model, several tries were made to understand the operation mode of that port. Applying different voltages showed no difference in the device performance, and probing the terminal voltage a constant value of zero was always measured, so its usefulness was disregarded for the rest of the design process. 3.1.2 Active device interface In order to integrate the transistor model in the circuit, one firstly used the symbol model directly in the simulation, but quickly realized that in order to accurately take advantage of the transistor model behavior, an adequate interface should be implemented between the transistor component, presented in figure 3.1b, and the surrounding networks. Since the active device has two drain ports, a power combiner must be made in order to convert them into a single output. Besides that, there must be ports to the bias networks and also ports for the two gate inputs and the transistor pad ports. Because the operation frequency of the layout model presented in the datasheet is not very different from the operation frequency goal, most of the design process took the circuit example, presented in figure 3.2, as a good starting point. Figure 3.2: Circuit example presented in the datasheet for 2.4 GHz [51] In order to develop a more exact model, the printed circuit PCB datasheet of the example circuit, also provided by the manufacturer was used [53], from which an accurate layout of the
3.2 Layout generation and simulation 53 transistor’s footprint was extracted. After that, an electromagnetic simulation of the layout was made, generating the EM model to be used. A symbol was generated from the layout, allowing an integration with the ideal model, as one can see in figure 3.3. Figure 3.3: Transistor footprint integration It is important to mention that as the source terminal will be connected to the ground plane through a relatively large pad, it was considered an ideal ground for the simulation, simplifying it. More information on the layout simulation process will be given in the layout section 3.2. 3.2 Layout generation and simulation Before proceeding to the next development stages, it is important to detail the methodology regarding the Electromagnetic simulations, model generation, as well as the chosen substrate. The chosen substrate was the two layer FR-4 by JLCPCB. The choice was made with the producer of the boards in mind, since they are known to make reliable RF Boards at good prices. The substrate specifications were obtained in [54], presenting the following characteristics: Substrate Height, H 0.8 mm Dielectric Constant, Er 4.5 Conductor Thickness, T 0.035 mm Dissipation Factor, TanD 0.015 Table 3.1: Substrate characteristics obtained from [54] An important detail to take notice is that the considered dielectric constant was not 4.5 as mentioned but 4.4, a common value used by RF engineers at the 2 GHz frequency range, as revealed in a research of the FR-4 dielectric properties variation for higher frequencies [55]. Across all the layout simulations, the port configuration was essential to capture the most accurate behavior of the circuit. Edge ports were configured as TML zero length with 50 Ωimpedance, as suggested in [56]. In ports with component connections auto mode was used with a high
PA design steps and simulations 54 impedance, 10000 ohm, also suggested in [56], where the geometry of the pad was drawn on top of the main copper layer, recreating the Surface Mounted Devices (SMDs) pads interaction with the mounting surface. Since the operation frequency of the amplifier is in the gigahertz range, the wave length is in the order of centimeters, so it was considered that the component pads should be simulated as area pins, since their size is relatively close to the signal wavelength, as suggested in [25]. The frequencies swept in the Electromagnetic (EM) simulation were an adaptive sweep from 1 Hz up to 15 GHz, including the fifth harmonic, being this information particularly used to investigate the device’s stability. Furthermore, frequencies from DC up to 12 GHz with a 2.4 GHz step were also swept, the DC being used for DC/IV purposes, and the remaining for Harmonic Balance (HB) simulations and single tone simulations. A final notice to make is, while the study of the effect of the different passive components values was being made, ideal models were used. Once the values were decided, a spice model of a more realistic performance was utilized. For the case of the inductors, there were no models available, and for the resistors it was made an assumption that the behavior would be close to ideal. The ceramic capacitor models were obtained from the Kemet simulator [57]. Even though some of the capacitors used were not from the mentioned brand, it was considered that they would not differ too much between manufacturers. The electrolytic capacitor model was obtained directly from the producer website. 3.3 Operation point With the active device selected, one is in good condition to start the PA design flow. As stated before, the most interesting classes of operation would be class AB, F or F inverse, as they usually present good efficiency in situations where linearity is not critical. The first step to investigate the limits of operation is to define the "soccer pitch" mentioned in section 2.4.3. After checking the datasheet, it was concluded that the breakdown voltage is 65 V and the VGS must be between −6 V and 13 V. Considering this information, a DC simulation was made sweeping the VGS and the VDS in the mentioned range. Using an Advanced Design System (ADS) display template, one was able to directly estimate the performance of the device while varying the operation point. Another factor that conditioned the selection of the bias point was the available power sources at FEUP for this thesis. There were two options, one of them with 12 V and a maximum current of 25 A, and the other with 28 V and maximum current of 5 A. The author considered that for an easier implementation the 28 V one would be used and associated in parallel if more current was required. The value sits close to the rule of thumb of half the breakdown voltage and close to the VDS voltage of the datasheet examples of 32 V [51]. So, the selected point of the marker 2 was with a VDS of up to 28 V being the VGS =2.279 chosen such that the output power PDC in figure 3.4a would be bigger than the required power,
3.3 Operation point 55 all this while maximizing efficiency and gain. The results obtained evidence a class AB with a conduction angle of about 193 deg and a drain efficiency of almost 70% with a gain larger than the 20dB mark and an output power of 53.74dBm. (a) DC IV simulation results with the transistor model (b) DC IV simulation circuit with the transistor model Figure 3.4: DC IV simulation with the transistor model It is important to notice the mentioned results followed a simulation of the transistor model. As the next step in the design is the stability analysis, more attention was put into simulate the circuit more accurately, so the DC IV examination was repeated, now with the transistor footprint mentioned in section 3.1.2. The results in figure 3.5a differed from the previous ones, specially on the DC current and the output power, as this time the biasing was only done in one side of the transistor, just like the datasheet example of figure 3.2. Nonetheless, the purpose of the template used was met. It was shown that a VDS of 28 V and aVGS between 2 V and 3 V would fulfill the output power requirement with a good efficiency and gain, if an adequate inclination of the load line is presented, that only happens if a suitable load resistance is applied, as explained in section 2.6.1.
PA design steps and simulations 56 (a) DC IV simulation of the transistor model with footprint (b) DC IV simulation circuit of the transistor model with footprint, circuit detailed in figure 3.3 Figure 3.5: DC IV simulation of the transistor model with footprint 3.4 Surrounding networks In order to analyze the stability of the device, it is important to insert it in a somewhat complete circuit that resembles the final one. This way, the behavior of the surrounding networks is taken into account stability wise. Due to the double transistor nature of the active device, a power divider to split the input signal into the two gates is required to be implemented, as well as a power combiner to merge the drains signal into the output. Since the transistor footprint presented in figure 3.3 has already present the combiner, the remaining networks to be implemented are the power splitter and the gate and drain bias gate. Only then an accurate stability analysis can be made. 3.4.1 Power Divider The power divider was implemented referring to [56], where a brief theoretic explanation is given, followed by the design process of the Wilkinson Power Divider (WPD). The document by
3.4 Surrounding networks 57 Keysight regarding power dividers, [58], was also an important resource, giving practical information for the circuit implementation with microstrip and how to simulate it in ADS. A Wilkinson Power Divider is a three port network that splits the signal of one port into the remaining two. This division can be regulated, being usually equitable, without dissipation and mismatch losses, suffering a loss of only 3 dB relative to the input [56]. To optimize the splitting process, obtaining a lossless, reciprocal, matched and providing high isolation between the output ports, the scattering parameters of the three ports network must respect equation (3.1). To do so, the configuration presented in figure 3.6 must be realized, where a line with a characteristic impedance Z0divides into two quarter wavelength of √2Z0lines with an isolation resistor of 2Z0[4, Chapter 7]. ¯ S= S11 S12 S13 S21 S22 S23 S31 S32 S33 =−j √2 011 100 100 (3.1) Figure 3.6: Transmission line equivalent of the WPD In order to implement the WPD in microstrip, the steps mentioned in [58] were followed. The considered Z0along the circuit was 50 ohm, so using the linecalc tool, the width of the 50 ohm and 70.7 ohm lines was calculated, as well as the length of the quarter wavelength section for 2.4 GHz and the chosen substrate. The chosen substrate and how it was simulated is detailed in section 3.2, as well as the port configuration and the frequency plan. It is always worth reminding that the linecalc tool uses equations internally to calculate the dimensions of the microstrips, which are well defined in conditions where the substrate width (d) is much smaller than the wavelength (λ). When this condition is met, approximations of the microstrip performance can be done regarding phase velocity (vp), propagation constant (β) and characteristic impedance Z0. Since some field lines are outside the conductor, mainly in the surrounding air and substrate, a correction is applied at the dielectric constant called effective dielectric constant (εe), being
PA design steps and simulations 58 calculated by the following equation: εe=εr+1 2+εr−1 2 1 p1+12d/W(3.2) With all the mentioned variables and the line width (W), one can calculate the respective characteristic impedance Z0. Z0=(60 √εeln8d W+W 4dfor W/d≤1 120π √εe[W/d+1.393+0.667ln(W/d+1.444)] for W/d≥1(3.3) The reverse process can also be done to determine the dimensions for a given Z0, W d=(8eA e2A−2 2 πhB−1−ln(2B−1)+ εr−1 2εrnln(B−1)+0.39 −0.61 εroi (3.4) being A and B given by: A=Z0 60 qεr+1 2+εr−1 εr+10.23 +0.11 εr B=377π 2Z0√εr.(3.5) The length (`) of a given line is directly related with its electric length (φ), that is, the phase offset of a given signal will be obtained by a product of the length and the coefficient that measures the phase delay per unit of space, which corresponds to the propagation constant (β). This way, to determine a line’s length one just needs to use φ=β`=√εek0` `=φ(π/180◦) √εek0 (3.6) where β=k0√εeand k0=2πf c. With the EM model generated, and associated with the isolation resistor in the respective place, the performance of the WPD was simulated. The first results showed the input resonance, the S11, minimum value at 2.5 GHz. A small adjustment of quarter wavelength section length centered it back in 2.4 GHz, leading to the results presented in figure 3.7b. It is important to notice that the output ports isolation was not ideal, being maximum at a frequency different than the operation frequency, however that did not affect the symmetrical splitting of the signal, since an analysis of the output ports signal in phase and amplitude showed no notorious differences, as one can see in figure 3.8. Another last detail is that the 50 Ωlines in the output ports were distanced to be in line with the transistor gates, an aspect that would help the implementation of the intermediate matching network, to be detailed in the following sections.
3.4 Surrounding networks 59 (a) WPD layout (b) WPD S parameters with a 100 Ωisolation resistor Figure 3.7: Wilkinson Power Divider Figure 3.8: Wilkinson Power Divider magnitude and phase balance between each branch (S21 and S31) 3.4.2 Bias network The bias network is a fundamental part of the circuit that ensures the DC operation point. This way, it should impose a DC voltage at the drain and gate, being completely independent of the RF behavior of the circuit, if not used for matching simultaneously. The classic method for bias networks is the use of a RF choke between the power supply and the terminal that will be biased, together with a DC block capacitor between RF inputs/outputs and the bias ports. A short circuit is created at DC by the RF choke, while simultaneously developing an open circuit for the RF signal. The DC block capacitor does the opposite, as it creates a low impedance path for the RF signal and, ideally, an open circuit for DC, preventing the DC signal from escaping to the RF parts of the circuit. The bias network design was inspired by the datasheet [51], where the impedance chokes resulted from the impedance of the decoupling capacitors being inverted by the quarter wavelength line connecting to the gate/drain. The decoupling capacitors resonate close to 2.4 GHz, presenting low impedance at that frequency and being close to an open circuit at very low frequencies. In-
PA design steps and simulations 66 Figure 3.14: Stability results, stability factors on the left and output voltage on the right Figure 3.15: Hybrid circuit layout 50% and the best possible gain. The load pull was made possible by the ADS Load Pull One-Tone Load Pull Simulations Constant Available Source Power and Load Pull One-Tone Load Pull Simulations Swept Available Source Power. In these simulations, a harmonic simulation is made, while the load tuner sweeps a given interval of loads, calculating the power delivered, efficiency and gain for every load, resulting in constant efficiency and power delivered contours. Some initial simulations were made to understand the impedance range that one should focus on to maximize efficiency, and the source impedance to use. The source impedance 50 Ωwas initially updated as the complex conjugate of the ZIn_at_MaxPAE , being a recursive process. The first template calculated the load that gives maximum efficiency, however, in that load, the power delivered was not enough, so a nearby load should be chosen with slightly more power delivered and, obviously, less efficiency (figure 3.18). The contours could also be seen in this template (figure 3.19), being a very important tool to a designer.
3.6 Load Pull 67 (a) Hybrid design circuit (b) Hybrid design stability results, µfactor on the left and large singal stability on the right Figure 3.16: Hybrid design Figure 3.17: Hybrid circuit stability circles from from 1 Hz up to 16 GHz To find the ideal point, a sweep around the 38.8 dBm input power was made with the other template. Using the data display that allows the selection of the gain compression (Display contours at X-dB Gain compression) the 3 dB compression point was selected, as linearity is not critical. The point was selected in order to satisfy the minimum required output power of 53 dBm,
PA design steps and simulations 68 Figure 3.18: Hybrid circuit load pull maximum PAE point obtained with 38.8 dBm of input power Figure 3.19: Hybrid circuit load pull power delivered and efficiency contours with 38.8 dBm of input power while maximizing the Power Added Efficiency (figure 3.20). On figure 3.20, one can also see Figure 3.20: Hybrid circuit load selection with 3 dB of gain compression the suggested harmonic impedances for the load and for the source. Regarding the tuning of the harmonics, several values were tested, such as alternating odd and even harmonics with open and closed circuits, all closed, all open, only imaginary, and a slight benefit presenting an open circuit to all the harmonics in the load and in the source.
3.7 Matching Networks 69 Therefore, the goal of the matching networks, should be 47.644 −j15.09 for the source impedance at fundamental, 15.759−j36.624 for the fundamental load impedance and open circuit for the remaining harmonics. 3.7 Matching Networks To achieve the required impedances, the Impedance matching tool was given a shot, as this tool allows for experimentation of different typologies of matching networks quickly with various complexities. However, it felt counter-intuitive, with various simulation errors, so the idea was abandoned. Firstly, the output matching was tackled, as it was the most critical, being succeeded by the input matching network development. 3.7.1 Output matching network The first output matching network to be developed was supposed to be for a class F amplifier, with the even harmonics short circuited, being the typology of the matching network inspired by [67]. Although the impedance matching required in the hybrid approach was not characteristic of a class F, the typology was maintained, as it was versatile and it did not require the use of lumped elements that could be a problem to find in the 200 W range of power. The microstrips with the two open stubs where initially implemented with ideal lines, optimizing the impedances of each harmonic to the requested ones. Figure 3.21: Ideal output matching network configuration The ideal design was later converted into microstrips, with the substrate of table mentioned in section 3.2 with the help of the Linecal ADS utility. Tapers and T junctions were added, as well as 50 Ωlines in the end and the beginning, to make the circuit ready for layout conversion. After the conversion, another optimization was made, integrating the output matching network maximizing the PAE and the load power, as well as minimizing the harmonic content of the second and third harmonic, reducing distortions. 3.7.2 Input matching network For the matching of the input the same approach was done, developing the Input Matching Network (IMN), starting with ideal microstrip lines. Despite that, a quick integration test revealed that even the input matching network with ideal behavior did not present substantial changes in the performance of the circuit and, it was decided
PA design steps and simulations 70 Figure 3.22: Output matching network microstrip design that the input matching would be done by the intermediate matching network that followed the WPD. 3.7.3 Final matching Figure 3.23: Final matching optimization, with intermediate matching networks in schematic form inside the HYBRID_Sample_PA block as shown is figure 3.15 To finish the optimization process of the hybrid design, both intermediate matching networks, as well as the OMN, were taken as variables, where the optimization goals continued to be efficiency, power delivery, and harmonic minimization. When the best solution was found and the layout was generated, the obtained results of the layout achieved a PAE of 51.625%, maintaining a power delivered of 53.25 dBm with the spectral content of figure 3.24. Since the stability conditions of the last stability test were altered, meaning the intermediate matching networks were slightly changed and a new matching network was added, a new stability test with the new layout was made, revealing that the hybrid design was still stable. The final layout for RF signal simulation can be seen in figure 3.25, where the bias network layout is disregarded since the first
3.8 Results 71 Figure 3.24: Harmonic content of final matching optimization, with a -147 dBm of DC isolation decoupling capacitor presents a short circuit for signal. And for DC simulations the electric length between the components is irrelevant. Figure 3.25: Final layout for simulations 3.8 Results Figure 3.26: Efficiency and gain versus input power on the left and output power on the right With the final layout obtained, a second HB simulation with a sweeping signal power to understand the variation of the different variables with increasing power was made.
PA design steps and simulations 72 Figure 3.27: Fundamental, first and second harmonic powers One can notice a drain efficiency of 55%, which falls short from the 65% from the datasheet, value at a bias condition of 32 V in the drain with a quiescent current of 100 mA. Analyzing figure 3.27, one could easily calculate IP2 and IP3 in order to conclude about the linearity of the system. Figure 3.28: S Parameters results Additionally, the S-Parameters were also studied for the normal bias conditions of VGS = 2 V and VDS = 28 V. 3.9 Monte Carlo Simulation and yield analysis To analyze the susceptibility of performance degradation due to process variations and component tolerances, a Monte Carlo simulation was done, which tested the circuit behavior for different variations of the discrete components and used the accuracy of the PCB printing process. The uncertainties considered can be consulted in table 3.2. The uncertainty of the microstrip dimensions were considered to be 25% of the drilling accuracy (0.2 mm with JLPCB [54]), following the error percentage used in [25]. The substrate thickness tolerance was obtained directly from [54] for boards with less than 1 mm of thickness (0.8 mm). Although the source mentions a tolerance of 0.1 mm, it is relative to the whole board thickness. A first statistical analysis revealed that a 0.1 mm tolerance greatly
3.9 Monte Carlo Simulation and yield analysis 73 dispersed the results, so a more realistic value of the substrate thickness tolerance of 0.05 mm was used. The capacitor tolerance was extracted from its datasheet [68], and the chosen resistors were all chosen to have 1% tolerance, as one can see in [69]. To apply the variations of the circuit Variable Uncertainty Substrate thickness tolerance ±0.05 mm Microstrip line Heigth ±0.05 mm Microstrip line Width ±0.05 mm Capacitor Value ±0.25 pF Resistance values ±1% Table 3.2: Tolerance values used in Monte Carlo Simulation with a Gaussian distribution dimensions, the layout of 3.25 had to be converted to schematic and the capacitor models extracted from [57] were replaced by ideal capacitors, so the analysis was valid. The layout was converted to schematic, excluding the transistor footprint that had no easy implementation. During this conversion, it was noticed that the performance of the device was affected, once again, proving that the schematic simulation alone is not a good representation of a circuit comportment. 5 10 15 20 25 30 35 400 45 20 30 40 50 10 60 Input Power (dBm) Schematic Output Power (dBm) Layout Output Power (dBm) 5 10 15 20 25 30 35 400 45 10 12 14 16 18 8 20 Input Power (dBm) Schematic Transducer Gain (dB) Layout Transducer Gain (dB) 5 10 15 20 25 30 35 400 45 10 20 30 40 50 0 60 Input Power (dBm) Schematic PAE (%) Layout PAE (%) Figure 3.29: Performance comparison between layout and schematic conversion Notwithstanding, Monte Carlo simulation dispersion of the different trials traduces the reliability of the design. Ideally, the designed PA should have an efficiency greater than 50%, while maintaining an output power of 53 dBm. Projecting this into the schematic simulation, it was assumed that the margin of acceptance of a given design is an efficiency greater than 30%, since the conversion process lost approximately 20% of efficiency compared to the nominal case. Since the output power does not differ significantly, one can directly plot the efficiency and gain versus the output power with the conversion explained above. Analyzing the dispersion graphs for the defined tolerances, one can say that the results present variation, since the 1000 Monte Carlo iteration graphs could be more "compact". This problem was even worst in the first Monte Carlo simulation, where each sub circuit of the network, namely bias networks and matching networks, had independent definitions of the substrate. This was
PA design steps and simulations 74 5 10 15 20 25 30 35 400 45 10 20 30 40 50 0 60 Input Power (dBm) Output Power (dBm) 10 15 20 25 30 35 40 45 505 55 8 10 12 14 16 6 18 Output Power (dBm) Transducer Gain (dB) 10 15 20 25 30 35 40 45 505 55 10 20 30 40 0 50 Output Power (dBm) PAE (%) Figure 3.30: Monte Carlo analysis output power efficiency and power delivered with 1000 iterations corrected to a single substrate width variation, which should represent reality more accurately, due to the small dimensions of the board. Furthermore, to quantify the reliability of the design, and since the main focus of this thesis’ PA is efficiency and power, a yield analysis was made, where it was counted the number of designs with a peak PAE greater than 30% at an output power of 52 dBm (considering the 1 dB difference of the schematic relative to the layout output power visible in figure 3.29). With an uniform substrate variation for all the networks, the number of fails in 1000 tries was 183, translating to a success percentage of approximately 82%. Figure 3.31: Monte Carlo analysis harmonic power relative to the carrier To evaluate the linearity effects, a sweep of the harmonics’ power for the given conditions was also done. As one can see, the device, which is considerably non linear, did not suffer too much. Around 10 dB variations were detected, making it only useful for constant envelope applications where linearity is not critical. A statistical analysis on the S parameters of the device was also done, but the outcome was the same as the above. The results were affected during the schematic conversion, and the dispersion was relatively compact, as one can see in figure 3.32 the effect it had on the small signal gain. With a perfect conversion of the layout behavior, one could calculate the stability factors from the S parameters and evaluate the number of designs potentially unstable with a yield analysis, however such was not possible for the reasons mentioned, making the stability analysis of non representative S parameters unviable.
3.10 AM-PM distortion 75 Figure 3.32: Monte Carlo analysis S(2,1) variation relative to the nominal value Although this statistical analysis step was not ideal, since one was not sweeping the actual performance of the device, or at least what should be an accurate representation of the design, it provided a good idea of how much the process variations could affect performance, for example, examining figure 3.32, one can say that a 2dB variation at a given frequency is to be expected from the projected value. Consequently, this is an important step that gives the designer some perspective and confidence to advance into physical implementation. 3.10 AM-PM distortion The design goal of this thesis’ PA is not to have the most linear amplifier possible, since it was decided that the modulations to be used would be constant envelope. Considering complex communication systems, like Wide-Band Code-Division Multiple Access (W-CDMA), where information is carried in the signal amplitude, that require an amplifier with good amplitude linearity [31, Chapter 2], such is not needed when constant envelope modulations are used. This is even worsened by the typical Peak to Average Ratio (PAR) of close to 10 dB, injuring the efficiency of the system, or requiring efficiency techniques like envelope tracking [24, Chapter 1], increasing the complexity of the circuit. This way, constant envelope systems are usually easier to implement, and the best metric to measure their linearity is by measuring AM-PM distortion, which quantifies how much a variation in the input power affects the output signal phase. Once more, using the "One Tone Harmonic Balance Simulation, swept frequency and power" ADS template, the AM-PM distortion was obtained, as one can see in figure 3.33 The measured value of distortion was done in a narrow band, since that is the application requirement. 3.11 Board generation In order to have a ready to print Printed Circuit Board (PCB) there is still some important details to be taken care off. Firstly, it is important to remember how the PA will be physically mounted. Contrary to what is suggested by the circuit example of figure 3.2, it was decided that
PA practical validation 82 Figure 4.6: Stress test of current consumption, being blue and orange the first and second trials respectively without active cooling along with yellow the last trial with active cooling process. The circuit was implemented with 10.44 V at his terminals, being capable of providing an output from 1.3 V to 2 V. Figure 4.7: Implemented resistive divider on protoboard 4.3 Small signal measurements Once it was verified that the consumption of the device was within the expected levels, one could advance for the next step, measuring the S parameters of the device. The S parameters were measured using active cooling and locking the device operation point at 1.23 A, as discussed earlier. To protect the measuring device, an additional 10 dB attenuator was added to the output port, as one can see in figure 4.8. The first VNA used was malfunctioning, adding an ondulatory behavior to what should be the usual device measurements, as one can see in the small signal gain graphic presented in figure 4.9.
4.3 Small signal measurements 83 Figure 4.8: Small signal measurement setup, with the VNA (A), PA (B), attenuator (C), power supply for the drain bias network (D), power supply for the resistive divider (E) and resistive divider (F) Figure 4.9: S21 Measured at malfunction VNA with nominal bias conditions The second Vector Network Analyzer used produced promising results for the S11 and S21 parameters, however, it presented high measurement noise to the S22 and S12 parameters. This behavior was investigated probing the VNAs with a Spectrum analyzer. The conclusion reached was that port 2 of the device was seriously damaged, having a 30 dB difference when compared to the first port, meaning that measurements where a stimulus signal from port 2 was required, like S22 and S12, had major noise issues. To bypass this problem, the amplifier was measured in reverse and the S11 and S21 of both configurations were combined, obtaining an accurate representation of the device’s behavior. Before each measurement the frequency range was defined, as well as the power level, followed by a Through, Open, Short, Match (TOSM), also known as SOLT, that would put the measuring point at the device’s terminals, removing the effects of the connecting cables and adapters. Analyzing the results in figure 4.11, a narrowing in the amplified band is notorious when
PA practical validation 84 Figure 4.10: S Parameters measurement with nominal bias conditions Figure 4.11: S Parameters measured at right and simulated at left with nominal bias conditions comparing the S21 parameters, being the transconductance gain particularly affected in the middle operation frequency band. The reflection coefficients of both the source and load have similar values to the expected ones. The main difference is the absence of the S11 strong resonating frequency, that would decrease the reflected energy of the input port, and a small peak in the S22 parameter around 2.4 GHz, where the device’s analysis must be done carefully as instabilities can appear. The isolation factor S12 stays within the expected values always below -20 dB, not presenting a problem stability wise. 4.4 Large signal measurements With the device characterized in small signal, what is left to effectively measure a Power Amplifier’ performance is its large signal operation. To characterize the PA, a sweeping input signal should be applied while measuring the output power and power consumption. With this, one has every variable needed to calculate the efficiency
4.4 Large signal measurements 85 and amplifier gain. The available signal generator was monotone and had a limit power level of 16 dBm, meaning that only one frequency could be analyzed at a time and a driver amplifier was required to bring the 16 dBm up to the simulated 38 dBm of maximum efficiency input power point. The available driver amplifier was known to have around 20 dB of gain with a maximum input power of 20 dBm, and with a single 28 V feed point. With this in mind, the driver was characterized so that one could calculate the power at its output that would feed the PA for the sweeping signal generator values. To test the driver, an attenuator was additionally added to the output of the driver, in order to downgrade the signal level to be read in the spectrum analyzer without having the risk of damaging it. The first attenuator that was considered to be used was a chain of attenuators by Tektronix capable of providing an attenuation of 51.3 dB at 2.4 GHz, as one can see in figure 4.12. However, these attenuators were disregarded since the first one in the chain was only rated for 5 W of dissipation. Figure 4.12: Tektronix attenuation chain S parameters The alternative used was a RG-58 coaxial cable with a length of 50 m. To better understand the behavior of the new "attenuator" the S parameters were extracted. Although the attenuation value (S21) is not particularly constant along the measured frequencies, having more quick variations and a bigger drift in the value as the frequency changes comparatively with the previous attenuator, has the advantage of a much smaller S11, making the system much less predisposed to become unstable, which is particularly important in the early stages of testing. The attenuation variations can be overcome by considering the respective attenuation for the given operation frequency. The attenuation used for the first large signal test was 56.3 dB according to the selected frequency of 2.464 GHz. This value of frequency was selected as a starting point for the measurements, since it was the frequency with the small signal peak gain. The outcome of the driver test can be seen in figure 4.14 where, as expected, the output power went up to 37 dBm, being close to what the PA requires in its most efficient operation point. The driver was fed with 28 V with a power consumption measured of less than 3 A, so a single power source was enough to feed it.
PA practical validation 86 Figure 4.13: 50 m RG-58 coaxial cable S parameters Figure 4.14: Driver Gain and PAE However, the PA required much more current, so parallel associations of the available power sources were needed, since each one could only deliver up to 3 A. With this configuration, three double power supplies were connected in parallel, providing a theoretic maximum current of 18 A. Considering a 50% efficient system with 200 W of output power, a DC power consumption of 400 W is needed. With a 28 V voltage, one is left with a current consumption around 14 A, being the power supply association enough for the case. This was done by carefully adjusting the output voltage of all power supplies with a common ground bus and three 28 V connections, that were successively connected to the PA drain port, while analyzing the current drifts between them to see if the supply system was balanced. With the setup of figure 4.15, large signal measurements were done, extracting the spectrum analyzer power values and current consumption for each input power, and sweeping the input power from -20 dBm up to the limit of 16 dBm. Ideally, an isolator would be used between the driver and the PA, preventing any power reflected, caused by a mismatch, to travel back to the driver damaging it. However, at the time of testing there was none available, so a simple coaxial cable was used. The use of an isolator would have the inconvenient of attenuating some of the driver’s power (that ideally would be higher to fully characterize the PA), since it’s scattering matrix is not unitary making it a lossy component.
4.4 Large signal measurements 87 Figure 4.15: Large signal measurements setup, with the signal generator (A), Driver (B), PA (C), RG-58 coaxial attenuation cable (D), spectrum analyzer (E), external cooling (F), power supply for the driver (G1), power supply for the resistive divider (G2), and power supplies for PA’s drain bias network (G3-G8) [4, Chapter 9]. Output Power (dBm) Output Power (dBm) Driver Gain (dB) PA Gain (dB) Chain Gain (dB) 0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40 45 0 5 10 15 20 25 30 35 40 45 0 5 10 15 20 25 30 35 40 Driver PAE (%) PA PAE (%) Chain PAE (%) 0 5 10 15 20 25 30 35 40 45 0 2 4 6 8 10 12 14 Figure 4.16: Large signal measurements results with 2 V of gate voltage at 2.464 GHz The PA’s gain was calculated from the chain gain subtracting the measured driver gain. It was assumed that the driver amplified the same as in the previous trial and the input power of the PA was the signal generator power plus the driver gain measured at that input power. Remembering figure 3.26, one can see that the gain did not suffer too much, with a peak gain value of 16 dB compared with the 18 dB from the simulated layout. Besides that, the implemented PA was compressing at much lower power compared to the simulation, reaching only 42 dBm instead of the minimal objective of 53 dBm. The PAE was brutally hit in the implemented circuit reaching only a peak value of 12% at the measured frequency. Measurements at surrounding frequencies revealed similar results with an output power of 44.2 dBm. The PA contributed with 6.1 dB of gain while having a peak efficiency of only 14.2% operating at 2.545 GHz. A suspicion from the author that could justify these poor
PA practical validation 88 results is a malfunctioning transistor. It could have been damaged in the DC tests before the resistive divider was built, where an overdrive of the gate voltage set the transistor in a momentary unstable regime, or from a thermal shock during the soldering process. Another cause is a common problem with the LDMOS technology (an ESD can create latch up phenomenon effectively damaging the transistor), a problem so critical that various techniques to tackle it have been investigated, being some examples available in [71] and [72]. This issu also crippled the testing process in another way, as it is believed that it was responsible for damaging the transistor (MHT1008NT1 [73]) of the first tested driver (figure 4.17), which was also a LDMOS device. Figure 4.17: First driver tested Fortunately, a replacement for the Ampleon’s device arrived just in time for the tests to be repeated, since the previous design was pretty far from the thesis’ objective. To replace the transistor extra care was taken when handling the replacement, being used a grounding bracelet to prevent any ESD, and performing the soldering in small intervals to not let the transistor heat up too much. Periodic probing was done with an ohmmeter to check if a high resistive path was maintained between every terminal, which was the device’s initial behavior, tested just after unpacking. An initial test of the device’s DC consumption with 50 Ωloads revealed that the new PA had become more efficient with a current consumption much more similar to the simulated one, as one can see in figure 4.18. With the lower current consumption the device heated up a lot less, stabilizing at 0.59 V without active cooling after 5 minutes. The S parameters were extracted again with the current consumption, which can be see in figure 4.19. The results did not differ too much from the ones in figure 4.11. In the new circuit the transconductance gain stays relatively constant in a larger bandwidth, compared with the indentation of the S21 around 2.4 GHz.The S12 was also slightly changed but still below the -20 dB mark. With the S parameters the first testing frequency chosen was 2.4 GHz, since at this frequency the PA’s S11 is minimal whilst the S22 is relatively low. This has particular importance because the test was done without an isolator, which would have been a preventive approach. The analysis of the S22 value along the frequencies, although also critical for stability, is less important in this case due to the low input reflection of the cable/attenuator.
4.4 Large signal measurements 89 Figure 4.18: DC IV comparison between simulation and measured with new transistor measured at 2 V to 1.6 V with steps of 0.1 V Figure 4.19: S Parameters measurement with nominal bias conditions using the new transistor An initial measurement of the output power for 0 dBm, 10 dBm and 15dBm was made at 2.4 GHz and its neighbouring frequencies, resulting in a maximum output power of 50 dBm at 2.35 GHz. Follow up tests would be required to detail the PA’s, driver’s and chain’s PAE and gain, while measuring the consumed current. However, one wanted to test the maximum input power at the most promising frequency output power wise. When 16 dBm of input power were applied to the system, the output DC blocker capacitor heated up very quickly. The user reaction time to turn off the system was enough for it to burn. The high currents meant that the joule effect on the ESR was too much for the capacitor to handle. To address this question, two replacements of 6.8 pF (since they were the available ones with resonance frequency near the operation frequency) were installed in parallel, creating two paths for the current to flow, effectively cutting in half the ESR, without having too much effect on the equivalent impedance since near 2.4 GHz the capacitors’ impedance is very close to zero. With the capacitor replacement the DC consumption was the same as previously, so the S parameters were measured to confirm the circuit’s behavior was maintained. The results, shown
PA practical validation 90 Figure 4.20: Output power measurements versus frequency for 0 dBm (orange), 10 dBm (blue), and 15 dBm (red) of input power in figure 4.21 reveal that changing the capacitor essentially had no effect. Figure 4.21: S Parameters measurement with nominal bias conditions using the 2 DC block capacitors at the output Input power sweeps were done initially for 2.4 GHz and later for 2.35 GHz, revealing the results of figure 4.22. The choice of the second frequency value was based in the performance versus frequency tests presented in figure 4.23, at which the output power was maximum with a 50.9 dBm value. Analyzing figures 4.22a to 4.22d, one can say that the driver contributed a lot for the gain of the chain being essentially constant for the measured input powers. Furthermore, some signs of the PA’s gain compression can be seen around 12 dBm of input power for 2.4 GHz, starting the compression at 15 dBm when a 2.35 GHz signal is used. The mentioned values of input power are relative to the system, in reality the input power of the PA at the compression points are the stated values plus the driver gain. For instance, the PA at 2.4 GHz starts compressing at 37 dBm. Concerning figures 4.22e and 4.22f, one can say that the system is most efficient at 2.35 GHz,
4.4 Large signal measurements 91 (a) (b) (c) (d) (e) (f) Figure 4.22: Device’s performance curves (with a sweeping input power from -20 dBm to 15 dBm) for 2.4 GHz at the left (a, c, e) and 2.35 GHz at the right (b, d, f), being the yellow traces relative to the chain, the blue traces relative to the Driver, and red relative to the PA and it is notorious that the Power Amplifier’s PAE is the dominant factor in the global PAE, since it is this stage that contributes the most for the total dissipation of the system. To analyze the functioning of the system in the neighbouring bandwidth, sweeps in frequency were done for 13 dBm, 15 dBm and 16 dBm of input power, which can be seen in figure 4.23. Additionally, the input power was fixed at 15 dBm (point where the system presented the peak PAE and peak output power) for characterization of the driver, measuring its gain for each frequency and its efficiency. This allowed to inspect the contribution of each part to the system’s global performance. Figures 4.23a, 4.23c and 4.23e show that the gain/output power do not vary too much with the selected values of input power, being required more dispersed values of input power to understand its impact. The PAE of the chain was affected by it, revealing a peak value of 40% at 2.35 GHz in the blue curve (15 dBm). The graphics on the right column of figure 4.23 manifest that the driver amplifier was responsible for most of the gain, while not having the best efficiency. The 50.9 dbm of output power
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