An Integrated Instrumentation Amplifier for Myoelectric Signals

FACULDADE DE ENGENHARIA DA UNIVERSIDADE DO PORTO An Integrated Instrumentation Amplifier for Myoelectric Signals Henrique Rodrigues de Castro Mendes Martins Mestrado Integrado em Engenharia Eletrotécnica e de Computadores Supervisor: Vitor Grade Tavares (PhD) July 26, 2013 c Henrique Rodrigues de Castro Mendes Martins, 2013 c Henrique Rodrigues de Castro Mendes Martins, 2013 Resumo Nas décadas passadas, o setor da eletrónica evoluiu exponencialmente. No nosso dia a dia a eletrónica está presente em tudo, nos nossos carros, e até em algumas das nossas roupas. A verdade é que os desenvolvimentos nesse setor aumentaram a qualidade de vida do Homem. No caso de algumas doenças, apenas com o auxílio de sistemas eletrónicos é possível realizar diagnósticos e tratamentos apropriados. Problemas do foro muscular e de movimento são uma vasta área na qual a eletrónica teve grande influência na ajuda a lidar e a tratar essas doenças. A eletrónica moderna permite uma melhor visão do que se passa ao nivel do músculo. Com instrumentação de grande precisão é possivel obter o sinal gerado pelas fibras das membranas musculares, o sinal miográfico. Os sinais miográficos são sinais muito específicos; eles são formados por variações fisiológicas nas fibras das membranas musculares. A medição e o processamento destes sinais é de grande importância, dado que eles permitem olhar diretamente para o músculo. Isto é uma análise importante que precisa de ser feita para : •Ajudar na tomada de decisão antes/após da cirurgia; •Permitir a medição do desempenho muscular; •Ajudar no processo de reabilitação; Estes são apenas alguns exemplos daquilo que é possível atingir investindo na investigação e desenvolvimento de sistemas aplicados a esta área em específico. Com isso em mente, a necessidade de um sistema que meça e processe tais sinais surge. No entanto, alta precisão e um elevado CMRR têm de ser assegurados, fazendo assim o amplificador de instrumentação uma escolha óbvia para a amplificação destes sinais. Esta tese apresenta o desenho e o desenvolvimento de uma nova topologia para um amplificador de instrumentação baseado na topologia Fully Balanced Differencial Difference Amplifier (FBDDA). O amplificador atinge um CMRR muito elevado de 122 dB, um ruído integrado de 2 µVna gama de 10 Hz a 300 Hz e um offset inferior a 1 mV. Para além disto, ele atinge muito boa estabilidade e boas caraterísticas em geral, assegurando que o espectro de aplicações para o amplificador é muito mais largo. i ii Abstract In the past decades, the electronics sector has evolved exponentially. In our everyday electronics is everywhere, in our cars, in our houses and even in some of our clothes. Truth is, the developments in that sector have increased the quality of life of the average Man. In the case of some diseases, only with the aid of electronic systems proper diagnosis and treatments can be made. Muscular and movement related problems are a wide area in which electronics have a great influence in dealing with such diseases. Modern electronics allows us to take a better look at what is going on at the muscle level. With great precision instrumentation we can obtain the signal generated by muscle fiber membranes, the Myographic signal. Myographic signals are a very specific type of signals; they are formed by physiological variations in the state of muscle fibre membranes [1]. The measuring and processing of these signals is of great importance, since they allow looking directly into the muscle [1]. This is an important analysis that needs to be done to: •Help in decision making both before/after surgery; •Allow measurement of muscular performance; •Aid in the rehabilitation process; These are just a few examples of what we can achieve investing in the research and development of electronic systems applied to this specific area. With that in mind, the need for a system that can measure and process such signals arises. However, high precision and a high CMRR must be ensured, thus making the instrumentation amplifier an obvious choice for the amplification of these signals. This thesis presents the design and development of a novel topology for an instrumentation amplifier based on the Fully Balanced Differencial Difference Amplifier (FBDDA).It achieves a very high CMRR of 122 dB, an integrated noise of 2 µVover the range of 10 Hz to 300 Hz, an offset lower than 1 mV. Beside this, it achieves very good stability and overall good characteristics, assuring that its applications domain is much broader. iii iv Acknowledgements I would like to thank my parents and my brothers for all the support they’ve given me, throughout all these years. Without their sacrifice, I find it hard to believe that I would be where I am at this moment. In the same regard, I would also like to thank Marta Galvão for all her support, and all the inspiration she has given me. Her constant support made the passing of obstacles a much easier task. To my friends - Bruno, Romano and Cristina - goes a big thank you as well, for putting up with me all these years, and making my academic life a much better one. Last but not least, I would like to thank my mentor, Prof. Vitor Grade Tavares for always having an answer ready for every question, and an advice when I needed it. His help greatly influenced my work, and for the better. Henrique Martins v xii LIST OF FIGURES 4.5 Output stage with offset stabilization circuit. Figure obtained from [10] . . . . . 37 4.6 GainandOutputStage ............................... 38 4.7 The Common-mode Feedback Detector. Image obtained from: [11] . . . . . . . . 40 4.8 The Error Amplifier for the CMFB Circuit. . . . . . . . . . . . . . . . . . . . . 40 5.1 Non-Inverting configuration of the amplifier . . . . . . . . . . . . . . . . . . . . 43 5.2 Frequency Response of the amplifier. . . . . . . . . . . . . . . . . . . . . . . . . 44 5.3 Monte Carlo analysis regarding the offset. . . . . . . . . . . . . . . . . . . . . . 46 5.4 Monte Carlo analysis regarding the phase margin. . . . . . . . . . . . . . . . . . 46 5.5 Produced layout without the I/O ring. . . . . . . . . . . . . . . . . . . . . . . . 47 5.6 Frequency Response of the amplifier after post-layout simulation. . . . . . . . . 48 5.7 Monte Carlo analysis regarding the offset and the phase margin of the post-layout simulation. ..................................... 49 5.8 Produced layout with the I/O ring. . . . . . . . . . . . . . . . . . . . . . . . . . 50 B.1 Common-source topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 B.2 Common-source with source resistor topology . . . . . . . . . . . . . . . . . . . 56 B.3 Common-source with capacitor topology . . . . . . . . . . . . . . . . . . . . . . 56 B.4 Source-Follower topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 B.5 Common-gatetopology............................... 57 B.6 Nmos amplifier with an enhancement load . . . . . . . . . . . . . . . . . . . . . 58 B.7 Nmos amplifier with a Depletion load . . . . . . . . . . . . . . . . . . . . . . . 59 B.8 Nmos amplifier with a Pmos load . . . . . . . . . . . . . . . . . . . . . . . . . . 59 List of Tables 4.1 Requirements for the amplifier, regarding myoelectric signals. . . . . . . . . . . 34 4.2 Transistor sizes for the input stage. . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.3 Transistor sizes for the gain and output stage. . . . . . . . . . . . . . . . . . . . 39 4.4 Transistor sizes for the cmfb detector. . . . . . . . . . . . . . . . . . . . . . . . 41 4.5 Transistor sizes for the error amplifier. . . . . . . . . . . . . . . . . . . . . . . . 41 5.1 Characteristics obtained through SPECTRE simulation and Monte Carlo analysis appliedtotheamplifier................................ 45 5.2 Post-layout simulation and respective Monte Carlo analysis. . . . . . . . . . . . 48 B.1 A comparison table between basic transistor configurations . . . . . . . . . . . . 58 xiii xiv LIST OF TABLES Acronyms, abbreviations and Symbols ADC Analog-to-digital converter BPF Band-Pass Filter CM Common-mode CMFB Common-mode feedback CMOS Complementary metal-oxide-semiconductor CMRR Common-mode rejection ratio DAC Digital-to-Analog Converter DC Direct Current DDA Differential Difference Amplifier DRC Design Rule Check EMG Electromyography FBDDA Fully Balanced Differential Difference Amplifier LPF Low-Pass Filter LVS Layout Vs Schematic IC Integrated Circuit MOSFET Metal–oxide–semiconductor field-effect transistor NA Not Available NMOS N-type Metal-Oxide-Semiconductor Op Amp Operational Amplifier In amp Instrumentation Amplifier PDA Pseudo-Differential Amplifier PGA Programmable Gain Amplifier PMOS P-type Metal-Oxide-Semiconductor PSRR Power supply rejection ratio RF Radio frequency THD Total Harmonic Distortion xv Chapter 1 Introduction The system responsible for the measuring and processing of myoelectric signals consists of electrodes, an instrumentation amplifier, a filter, a sample and hold circuit and an analog to digital converter (ADC). Electrodes are an important part of the system, as they allow us to measure the Myographic signals, when strategically positioned on the patient’s skin. Since the characteristics of these signals are far from optimal for one to properly process them, the use of the instrumentation amplifier is justified. It will bring the signal to a range of voltage values that will allow us to handle these signals with no additional efforts. However, precautions must be taken in the development and building of the instrumentation amplifier, to assure that there are no external components interfering with the signal, such as noise. The goal of this thesis is to develop a new instrumentation amplifier topology, based on the CMOS 0.35 µmtechnology, simulate its operation and then implement it in an integrated circuit. 1.1 Problem Presentation and Challenges The problems associated with the amplification of myographic signals are mostly noise related. Putting aside the usual problems associated with multi-stage amplifiers design and development, in this specific case, noise and common-mode interference are the most relevant ones. The tradeoff between area, gain, bandwidth and other specific characteristics is even more tight, as noise and THD must be taken into account first upon the developing of the amplifier. This is due to the signal’s frequency, that is usually very small - a few hundreds of hertz - thus making flicker noise hold a reasonable value. Also, due to their small amplitudes, noise’s influence is much greater as its nominal value might be of the same order of the input signal. Coming from the power-lines, comes the common-mode interference, also known as 50/60 Hz noise. This is yet another problem, as the instrumentation amplifier must neglect all the commonmode signals and amplify the differential ones, thus requiring a very high CMRR. Another problem that was not mentioned before, is the offset. As the instrumentation amplifier is known to be a high-precision and high stable circuit, the offset level must be very low. 1 2Introduction As this amplifier is meant to be integrated on a chip, other problems arise, related to power consumption and area, thus making the choice of the topology and the number of stages a major trade-off between a lot of characteristics. This is the main challenge, to provide a viable new topology that offers optimum qualities, and also possessing low power consumption and low area. 1.2 Motivation With the advances of microelectronics in the past decades, many areas have required more and more from this sector. One example stands out - Health care. Instrumentation electronics has provided a lot of possibilities for health care professionals. One of these cases is the diagnosis of problems related to muscular diseases. These type of diseases can easily be diagnosed by observing the myographic signals of the patients. This procedure requires a complex circuit, referred before. But its applications go far beyond the simple diagnostic. Ideally, this circuit has zero area and zero power consumption. Referring solely to the amplifier, ideally it possesses zero noise and infinite CMRR, meaning that the differential signal we put at the input, is the signal we expect at the output multiplied by the gain. Obviously, those characteristics are impossible to obtain, but we can obtain something that is very close to that, and, that is good enough for the measuring of these signals. 1.3 Objectives The main goals of this thesis are: •Develop a new instrumentation amplifier topology. •Design and fully simulate the new topology, and perform Monte Carlo analysis. •Design the layout of the produced amplifier, optimize it for symmetry, and then perform a post layout simulation, along with its Monte Carlo simulation. •Send the layout to Europractice and then test the chip produced upon its arrival. 1.4 Structure of the Document This document presents the following structure: •Chapter 2 contains the necessary background for one to understand this document minimally, regarding mostly myoelectric signals and differential amplifiers. •Chapter 3 presents a bibliographic review on instrumentation amplifiers and multi-stage amplifiers that suit myographic signals. 1.4 Structure of the Document 3 •In Chapter 4 the proposed amplifier’s topology is explained, and every stage is thoroughly analysed and justified. The starting point is also presented, as well as the topology variations throughout the semester. •Chapter 5 presents the simulation of the amplifier’s topology, as well as the Monte Carlo analysis. In the end, results are presented, then the layout is shown, and the post layout simulation is presented along with its Monte Carlo simulation. •Chapter 6 is the final chapter of this document that presents the conclusions obtained from the work developed along with the proposals for future improvement of the proposed topology. 4Introduction Chapter 2 Theoretical Background The purpose of this chapter is to enlighten the reader, providing the necessary theoretical background for him to read the document with clear understanding of what is the topic of discussion. 2.1 Myoelectric signals 2.1.1 What are they? A myoelectric signal, also called a motor action potential, is an electrical impulse that produces contraction of muscle fibers in the body. The term is most often used in reference to skeletal muscles that control voluntary movements. Myoelectric signals have frequencies ranging from a few hertz to about 300 Hz, and voltages ranging from microvolts to milivolts. 2.1.2 Obtaining and measuring Myoelectric signals are detected by placing three electrodes on the skin. Two electrodes are positioned so there is a voltage between them when a myoelectric signal occurs. The third electrode is placed in a neutral area, and its output is used to cancel the noise that can otherwise interfere with the signals from the other two electrodes. The output voltage is processed using the differential amplifier. The output of the amplifier has much higher voltage than the myoelectric signals themselves. This higher voltage, which produces significant current, can be used to control electromechanical or electronic devices. 2.1.3 Applications Myoelectric signals are of interest to the developers of prosthetic devices, such as artificial limbs. The signals can also be used to facilitate the operation of a computer using small voluntary muscle movements, such as blinking the eyelids. Figure 2.1 contains a summary of applications for electromyography (EMG). 5 12 Theoretical Background Figure 2.6: Differential pair with cascoding Figure 2.7: Differential pair with current source load 2.3.4.1 Frequency Response This section deals with the analysis of the frequency response of the differential pair, both for differential signals and common mode signals. As we can see in Figure 2.8, its frequency response is similar to that of a common source stage, exhibiting miller multiplication of Cgd . In this case both +Vin2/2and−Vin2/2 are multiplied by the same transfer function, that brings us to the conclusion that the number of poles in Vout /Vin is equal to that of each path (rather than the sum of the number of the poles in the two paths). For common-mode signals, the high frequency gain is determined by the capacitance at node P, which consists of Cgd3,Cdb3,Csb1and Csb2. If M1-M3 are wide transistors this capacitance will be of considerable value. Assuming there is a mismatch between M1 and M2,we can obtain the 2.3 Amplifiers 13 common mode high frequency gain simply by replacing in the formula the drain resistor and the output resistor of M3 with its own value in parallel with the capacitance seen through that node. AV,CM =−(∆gm (RD||(1 (CLs)))) ((gm1+gm2)[ro3||(1 (CPs)+1) ). This suggests that, if the output pole is much farther from the origin than is the pole at node P, the common mode rejection of the circuit degrades considerably at high frequencies. For differential pairs with high impedance loads made with active loads, an analysis can be made for differential and common mode signals separately. Figure 2.8: Differential pair equivalent half circuit Figure 2.9: Differential pair with current source load 14 Theoretical Background In this case ( 2.9), G is an ac ground, because Cgd3and Cgd4conduct equal and opposite currents to that node. As we have a very high load seen from the output (ro3||ro1), the dominant pole is given by ((ro3||ro1)CL)(−1). The common mode behaviour of this circuit is similar to the one analysed before. Let us consider now a differential pair with an active current mirror. Figure 2.10: Differential pair with mirror pole representation In contrast to the fully differential configuration, this topology does not have the same transfer function on both sides. The path consisting of M3 and M4 includes a pole at node E, which is known as the mirror pole. This pole is greater in magnitude than the output pole, and it is given by Cgs3,Cgs4,Cdb3,Cdb1,and the miller effect of Cgd1and Cgd4. Even if only Cgs3and Cgs4 are considered, the severe trade-off between gm(1/gm3is the impedance seen through that node) and Cgs of PMOS devices results in a pole that greatly impacts the performance of the circuit. Through some abbreviations, the poles of this circuit are as follows: ωp1=1/(CL(roN ||roP)) and ωp2=gmP/CEwhere CEis the total capacitance at node E. There can also be obtained a zero in the left half plane, and its value is 2ωp2. In summary, fully differential circuits do not possess a mirror pole, another advantage against single ended circuits. 2.3.5 Stability and Frequency Compensation Stability and frequency compensation is a topic that has to be taken into account by analog circuit designers. If we want to achieve higher output voltage swings, then a two stage operational amplifier is required, and the study of such amplifier’s stability is of great importance. 2.3 Amplifiers 15 Figure 2.11: Two-stage operational amplifier Observing figure 2.11, we can identify 3 poles, one at A1(A2), another at B1(B2)and another at X(Y). As stated in the previous section the pole at X lies in the high frequencies. Since the small signal resistance seen at A1 is high, even the capacitances of M3,M5 and M9 can create a pole close to the origin. In the output, the resistance can be small, however, CLcan be high, making the circuit exhibit two dominant poles. A bode plot of this circuit can be found in [13]. Since the poles at A1 and B1 are relatively close to the origin, the phase approaches −180owell below the third pole. This implies that the phase margin may be close to zero even before the third pole contributes with its phase shift. So, how do we compensate this circuit? The goal is to move a dominant pole towards the origin so as to place the gain crossover well below the phase crossover. However, the unity gain bandwidth after compensation cannot exceed the frequency of the second pole of the open-loop system. Thus, the magnitude of ωp,A1must be reduced, however, the available bandwidth will be limited to approximately ωp,A1, which is a low value. Furthermore, the small magnitude of the required dominant pole translates to a very large compensation capacitor, which is not desired. In [13], a better approach is taken, also known as Miller compensation, that creates a large capacitance at node A1, and moves the output pole away from the origin. 2.3.6 Common-mode Feedback As we have seen in the previous sections, fully differential amplifiers have many advantages in comparison with their single ended counterparts, such as greater output swings, avoiding mirror poles, thus achieving a higher closed loop bandwidth. However, high gain differential circuits require common-mode feedback. For a better understanding of the need of this type of feedback, an example is required. In a differential amplifier, sometimes negative feedback is required, and for that, we short the inputs and the outputs of the circuit. The input and output common mode levels are well defined in this case: VDD −RDISS/2. Now suppose the load resistors are replaced 16 Theoretical Background by PMOS current sources , so as to increase the differential voltage gain. Figure 2.12 represents this example. Figure 2.12: Differential pair with inputs shorted to outputs What is the common mode level at the output node? Since each of the input transistors carry half of the tail current, the CM level depends on how close the PMOS current values are to that value. Suppose there is a mismatch in the PMOS and NMOS current mirrors defining an error between their drain currents and ISS/2. If we assume the drain currents of both M3 and M4 in the saturation region are slightly greater than ISS/2, both M3 and M4 must enter the triode region so that their drain currents match ISS/2. Conversely, if their drain currents are inferior to ISS/2 then both Vout1and Vout2must drop so that M5 enters the triode region, thereby producing only 2ID3,4. The above difficulties arise because in high gain amplifiers, we want to use a p-type current source to balance an n-type current source. The difference between the currents, IPand INflows through the intrinsic output impedance of the amplifier, creating an output voltage change equal to (IP−In)(RP||Rn). Since the current error depends on mismatches and the load associated with it is high, the voltage error can become very large, thus driving the n-type or p-type current source into the triode region. It is emphasized that differential feedback cannot define the CM level. As expected, in high gain amplifiers, the output CM level is quite sensitive to device properties and mismatches and it cannot be stabilized by means of differential feedback. Thus, a common mode feedback network must be added to sense the CM level of the two outputs and accordingly adjust one of the bias currents in the amplifier. CMFB consists of three operations: •Sensing the output CM level 2.3 Amplifiers 17 •Comparison with a reference •Returning the error to the amplifier’s bias network Recalling that Vout,CM = (Vout1+Vout2)/2, a resistive divider can be employed as shown in figure 2.13. Figure 2.13: Common-mode feedback with resistive sensing This generates a voltage Vout,CM =(R1Vout1+R2Vout2) (R1+R2), that is equal to (Vout1+Vout2)/2 if the resistors are equal. The difficulty here is that both resistors must be much greater than the output impedance of the amplifier so as to avoid lowering the open loop gain. Such large resistors occupy a very large area and suffer from substantial parasitic capacitance to the substrate. To eliminate the resistive loading, we can interpose source followers between each output and its corresponding resistor as seen in figure 2.14. 18 Theoretical Background Figure 2.14: Common-mode feedback with source followers This technique produces a CM level that is in fact lower that the output CM level by the gatesource voltage of transistors M7/M8. It is also important to state that R1and R2or I1and I2must be large enough to ensure that M7 or M8 can handle a large differential swing on the output. However, this sensing method has an important drawback: it limits the differential output swings (even if the resistors and the currents are large enough) by approximately the threshold voltage. Another type of CM sensing can be seen in figure 2.15: Figure 2.15: Common-mode feedback with MOSFETs operating in deep triode region In this type of sensing, we use two transistors in deep triode region, introducing a total impedance that is equal to the parallel of M7 and M8 output resistors, which vary with the width, 2.3 Amplifiers 19 the length of the transistors and Vout1+Vout2. If both the outputs rise together, then the total load imposed by the transistors will drop, whereas if they change differentially, the load of one transistor will increase and the other will decrease. As the resistor-based sensing method, this method also limits the output voltage swing. Now that we have a method of sensing the CM level, it is imperative to compare it with a reference and return the difference to the bias network. To do this, an op amp can be employed, connected to the NMOS current sources, as we can see in figure 2.16: Figure 2.16: Sensing and controlling the output CM level The mode of operation is as follows: if both the output voltages increase, so does VE, thus increasing the drain currents of M9 and M10 and lowering the output CM level. It can also be interpreted as a form of forcing the CM level of both the outputs to the value of the reference, if the open loop gain is high. This type of feedback can be applied to the PMOS current sources as well. In some cases, the feedback can be used to control only one tail current source, to allow optimization of the settling behaviour. As we have seen, both M9 and M10 were fed by the error coming from the opamp. This technique consists of using only one of them to receive the error, whilst the other is biased at a constant current. 2.3.7 Class Type of Amplifiers This section provides the reader with an insight about the possible classes of the amplifiers. In our case, it is only pertinent to study the A class , the B class and the AB class. For more information on amplifier class types the reader can find it here : [14]. 2.3.7.1 Class A This is the most linear of the classes, meaning the output signal is a truer representation of the input. Here are the characteristics of the class: •The output transistor conducts for the entire cycle of the input signal. In other words, they reproduce the entire waveform in its entirety. 20 Theoretical Background •These amplifiers work at higher temperatures, as the transistors in the amplifier are on and running at full power all the time. •There are no conditions to turn the transistors on/off. That does not mean that the amplifier is never off or can never be turned off; it means the transistors doing the work inside the amplifier have a constant flow of current through them, also known as bias. •Class A is the most inefficient of all power amplifier designs, averaging only around 20%. Because of these factors, Class A amplifiers are very inefficient: for every watt of output power, they usually waste at least 4-5 watts as heat. Because of this, they run hotter than the other class types, increasing somewhat the thermal noise of the devices. All this is due to the amplifier constantly operating at full power. The upside is that these amplifiers are the most enjoyed of all amplifiers. Since the transistor reproduces the entire waveform without ever cutting off, the waveform is more linear; that is, it contains much lower levels of distortion. 2.3.7.2 Class B In this amp, the positive and negative halves of the signal are dealt with by different parts of the circuit. The output devices continually switch on and off. Class B operation has the following characteristics: •The input signal has to be a lot larger in order to drive the transistor appropriately. •This is almost the opposite of Class A operation. •There has to be at least two output devices with this type of amplifier. The output stage employs two output devices so that each side amplifies each half of the waveform. Either both output devices are never allowed to be on at the same time, or the bias for each device is set so that the current flowing in one output device is zero when not presented with an input signal. •Each output device is on for exactly one half of a complete signal cycle. These amps run cooler than Class A amps, but the linearity is not as pure, as there is a lot of "crossover" distortion, as one output device turns off and the other turns on over each signal cycle. This type of amplifier design, or topology, gives us the term "push-pull," as this describes the tandem of output devices that deliver the signal to your speakers: one device pushes the signal, the other pulls the signal. As mentioned before, the input signal has to be a lot larger, meaning that from the amplifier input, it needs to be "stepped up" in a gain stage, so that the signal will allow the output transistors to operate more efficiently within their designed specifications. This means more circuitry in the path of your signal, degrading the signal even before it gets to the output stage. The efficiency of such topology wanders around the 60 per cent, and its linearity is inferior to that of class A, as there is a trade-off between efficiency and linearity. 2.3 Amplifiers 21 2.3.7.3 Class AB This is the compromise between both classes, A and B. Class AB operation has some of the best advantages of both Class A and Class B built-in. Its main benefits are linearity comparable to that of Class A and efficiency similar to that of Class B. Most modern amp designs employ this topology. Its main characteristics are: •In fact, many Class AB amps operate in Class A at lower output levels, again giving the best of both worlds •The output bias is set so that current flows in a specific output device for more than a half the signal cycle but less than the entire cycle. •There is enough current flowing through each device to keep it operating so they respond instantly to input voltage demands. •In the push-pull output stage, there is some overlap as each output device assists the other during the short transition, or crossover period from the positive to the negative half of the signal. There are many implementations of the Class AB design. A benefit is that the inherent nonlinearity of Class B designs is almost totally eliminated, while avoiding the heat-generating and wasteful inefficiencies of the Class A design. And as stated before, at some output levels, Class AB amps operate in Class A. It is this combination of good efficiency (around 50) with excellent linearity that makes class AB the most popular amplifier design. 2.3.8 Instrumentation Amplifiers Probably the most popular among all of the specialty amplifiers is the instrumentation amplifier (in-amp). The in-amp is widely used in many industrial and measurement applications where dc precision and gain accuracy must be maintained within a noisy environment, and where large common-mode signals (usually at the ac power line frequency) are present. It may come to mind that an in-amp might be the same as an op-amp , but several differences exist between them. An inamp is a precision closed-loop gain block. Normally, it has a pair of differential input terminals, and a single-ended output that works with respect to a reference. Usually the feedback is done internally, and there is a gain setting resistor. Its input impedance is quite high, and its CMRR usually surpasses the 80 dB mark. The typical instrumentation amplifier topology can be found in figure 2.17. 28 Bibliographic Review Figure 3.8: The Fully Balanced Differential Difference Amplifier The reader might easily come to the conclusion that this topology entails more area, but it allows for more dynamic range and a higher input impedance value, as well as the ordinary advantages achieved by the differential pairs. This configuration finds its applications in a wide range of areas. In a similar way to the much known op amp configuration, the FBDDA also allows for inverting or non inverting configurations as well as buffer operation. Image 3.9 presents the fundamental applications for the FBDDA. 3.2 Instrumentation Amplifiers Topologies 29 Figure 3.9: Several applications of the FBDDA. (a) single ended buffer. (b) Fully differential buffer. (c) Single ended noninverting amplifier. (d) Fully differential noninverting amplifier. (e) Single ended state-filter. (f) Fully differential state-variable filter. Image obtained from [5] It is also imperative to know the possible negative feedback combinations. Image 3.10 presents all of the possible combinations. These different topologies present different characteristics as well. 30 Bibliographic Review (a) (b) Figure 3.10: Negative Feedback combinations (a) and (b). Outputs are fed back to the same differential pair (a). (b) outputs are fed back to different differential pairs. In [5] it was presented the original FBDDA topology with a cmfb circuit, as well as a class AB output stage. Good results were achieved. Information about FDDAs is not presented here because the FBBDA is , so to speak, an upgrade to that topology and more suitable for instrumentation amplifiers development. However, if required, more information on FDDAs can be found here: [15], [16], [17], [18] and [19]. 3.2.2 Pseudo-Differential Amplifiers (PDA) PDAs are a variation of FDDAs. The major difference is that they do not use a current source in the input pair, as seen in figure 3.11. This allows for higher swings, as the current source does not limit the source voltage of the input transistors. However, this topology suffers in terms of common-mode response, as its CMRR is close to 0 dB , since the differential gain equals the common-mode gain. 3.2 Instrumentation Amplifiers Topologies 31 Figure 3.11: Pseudo-Differential Amplifier. [6] presents a novel PDA topology with a rail-to-rail CMFB detector using a transconductance and a transimpedance amplifier. Low power consumption and small area is achieved. 3.2.3 Chopper-Stabilized Amplifiers Chopper-stabilized amplifiers are amplifiers that present low noise. They are mainly composed by a pre-modulation block, followed by an amplifier, and ending with a demodulator. This allows to amplify the signals in a desired frequency, reducing flicker noise immensely and achieving very low offset. However, chopper amplifiers usually require switching capacity and occupy a rather large area. In [7] a novel chopper amplifier topology is presented , that combines the chopper topology with the DDA topology. This allows for a very low noise and a low offset amplifier. It is a fairly good topology, however, in terms of area, it is quite big. 3.2.4 Comparative Analysis When facing the 3 possibilities to implement an inamp, one should consider the goals he has in mind for the amplifier. The chopper amplifier is better in terms of noise and offset, however in terms of area it would be quite large, and it would imply the use of switching, complicating the circuit. While the PDA presents good characteristics, it lacks the overall better characteristics that the simple DDA presents, namely the much required high CMRR. Since the goal of this thesis was to make a dedicated inamp and at the same time maintain good characteristics to be used in other 32 Bibliographic Review kind of applications, the DDA topology was the one that stood out. Another reason for the choice of this topology was the fact that there are not any instrumentation amplifers based on the FBDDA topology yet. Chapter 4 Development of the Instrumentation Amplifier The first step to take in developing an amplifier is to acknowledge the environment in which it will work, and the signals it will amplify. In this case, the environment is standard (normal temperature, pressure and humidity values), and it will reside on a chip to be placed near the electrodes. This first condition rapidly leads us to the conclusion that the power consumption of the chip has to be very low, to increase the battery life, and its area has to be small, to avoid provoking discomfort on the patient. Regarding the signals, we already know that they are low frequency, and low voltage implying high precision and low noise. These are the top requirements to be satisfied, things such as bandwidth and slew rate, for example, are not so important in the design of such amplifier. Besides these characteristics, there are the usual op amp characteristics that have to be fulfilled, such as the Phase Margin, gain, and others. For a better visualization of the global requirements, the reader can find in table 4.1 an organized view of the desired characteristics. With the requirements in mind, the beginning of the development of the topology is quite simple. The differential pair is a fairly good start, as explained in the previous chapters, and so, the adopted topology was as follows. The block diagram of the proposed amplifier can be seen in figure 4.1. The two differential transconductance amplifiers are the input differential pairs. The currents from the complementary inputs sum, following to a gain amplifier (gain and output stage). This type of configuration is advantageous because it entails high input impedance and increased dynamic range due to the use of not one, but two differential pairs. This is a recent topology, and there are no instrumentation amplifiers implemented yet with it. With the advantageous characteristics, its high flexibility and the fact that it was a recent topology it was set in stone that the amplifier would be built based on this topology. 33 34 Development of the Instrumentation Amplifier Table 4.1: Requirements for the amplifier, regarding myoelectric signals. Characteristic Minimum Required Goal Optimum Value Bandwidth 10*500 Hz = 5000 Hz >5000 Hz PSRR 80dB >80dB CMRR 80dB >100dB Offset 100u <100u Integrated Noise (10Hz - 300Hz) 2µV2<2µV2 Input Impedance 1M >1M Open Loop Gain 80dB >80dB Input Swing Arbitrary rail-to-rail Output Swing Arbitrary rail-to-rail Output Impedance 5K 500 Phase Margin 60o>70o Gain Margin <0 -30 Slew Rate Arbitrary >1 V/us Figure 4.1: Block diagram of the instrumentation amplifier - FBDDA topology. 4.1 Input Stage The input stage is a derivation from the initial topology - it has 2 NMOS differential pairs as well as 2 PMOS differential pairs that entail rail-to-rail operation. This is due to the fact that when the input voltage is near the positive rail, the NMOS are active, while on the other hand, if the input voltage is close to the negative rail, the PMOS are active. In either case, the complementary pairs are cut-off. To maintain the circuit balanced, the NMOS and the PMOS currents are summed up, through a current mirror , allowing for the correct functioning of the circuit upon mid rail operation (both pairs are active). However, this entails a problem, the equivalent gm of the input pair is not constant, affecting the circuit stability and gain. Transistors M1-M8 are the differential pairs, both NMOS and PMOS. Transistors M9-M12 are the gm-control transistors. These transistors are responsible for performing a DC shift in the input voltage, thus making the transistors operating-zones overlap, as explained in the bibliographic 4.1 Input Stage 35 review, allowing for a constant gm throughout the input voltage range. Transistors M13-M20 are current sources that supply the differential pairs, as well as the dc shifting transistors. Since we have NMOS and PMOS differential pairs, we need to have a way to sum the currents in both pairs. Transistors M21-M24 take care of that problem, as they mirror the current from the PMOS branch, to the NMOS. In the end, both currents are summed and carried out to the gain stage (Out1 /Out2). As for the load of the NMOS differential pairs, a cross-coupled load was used - transistors M25-M28. This allows for a higher CMRR, since the impedance they offer is higher for differential signals, and smaller for common-mode signals, unlike the simple PMOS load. Figure 4.2 presents both types of load. (a) Differential pair with a PMOS active load. (b) Cross-coupled load on a single differential pair. Figure 4.2: Types of load. (a) simple PMOS active load. (b) cross-coupled load Even though, the PMOS active load has to offer a slightly higher output impedance, the cross coupled load offers other types of advantages. For common-mode signals, the impedance it of- 36 Development of the Instrumentation Amplifier Table 4.2: Transistor sizes for the input stage. Transistor Size (W/L) M1-M4-M5-M8 50.1/5 M2-M3-M6-M7 150/5 M13-M14-M21-M22-M23-M24 10/1 M16-M19 30/1 M15-M17-M18-M20 25/1 M25-M26-M27-M28 15/1 fers is quite low, approximately 1/gm, and for common-mode signals, it is approximately Ro3/2 assuming the transistors have the same size, since the total impedance seen from the drain is the parallel of (1/gm3// −1/gm4)with Ro3//Ro4. This increases the CMRR, as well as permits the CMFB circuit to drive the current source in the gain stage instead of the current source in the input stage. This would complicate the CMFB circuit, as we would need to have two outputs, instead of one: one for the NMOS current sources, and another for the PMOS. The cross-coupled load is clearly advantageous. With this being said, the reader can find the total input stage in figure 4.3. Figure 4.3: Input Stage of the Instrumentation Amplifier The sizes of the transistors can be found in table 4.2: 4.2 Gain stage and Output Stage As for the gain stage, a simple common-source was used, with miller compensation. The diode connected NMOS function is to balance the gain branch and the branch composed by transistors M29-M31 in terms of voltage. Compensation was made through a Poly capacitor and a triode 4.2 Gain stage and Output Stage 37 transistor. This triode transistor had its bias point controlled by two other diode connected devices, but because of the total power consumption, they had to be removed, making the control of resistance of the transistor externally. This output stage is based on the one developed by Phillip Allen, in [10]. It achieves rail-torail operation, as well as a low output resistance. This topology in particular also guarantees offset protection. Rail-to-rail operation is achieved through the use of transistors in Common-Source configuration. However, the reader might wonder how is the low output resistance achieved, if we are to use Common-Source transistors. This is due to a feedback network applied directly on the output, thus reducing the output resistance by a factor of (1+Loop Gain). In this case, the loop gain is determined by the error amplifiers, as seen in figure 4.4 Figure 4.4: Negative Feedback applied on the output In this case, the error amplifiers are simple differential pairs. Transistors M1 - M8 constitute the differential pairs.Transistors M35 and M34 are the output transistors, and their current is stabilized in case of an offset in the error amplifiers by the feedback loop composed by M29-M33 and M14. Figure 4.5 portrays this situation. Figure 4.5: Output stage with offset stabilization circuit. Figure obtained from [10] 44 Simulation and Results 10−2 1001021041061081010 −140 −120 −100 −80 −60 −40 −20 0 20 40 Frequency Magnitude (a) Magnitude Plot. 10−2 1001021041061081010 −800 −700 −600 −500 −400 −300 −200 −100 0 frequency phase (b) Phase Plot. Figure 5.2: Frequency Response of the amplifier. 5.1 Characterization of the amplifier 45 Table 5.1: Characteristics obtained through SPECTRE simulation and Monte Carlo analysis applied to the amplifier. Characteristics Obtained from SPECTRE simulation Monte Carlo Analysis Aol 78.63 dB NA Acl 20.81 dB 20.81 Input Swing Vmin = -0.75V ; Vmax=1.6V NA Output Swing Vmin = -1.04V ; Vmax=1.61V NA Bandwidth 641KHz 635.5KHz CMRR NA >122dB PSRR NA >86dB Integrated Noise (10 Hz - 300 Hz) 1.8µV2NA Slew-Rate 0.2V/µsNA Load Min R = 500 ohm , Max C=100p NA Power Consumption 6.8 mW NA Phase Margin 84 77 Gain Margin -21.71 -18.79 THD 0.1 % @ 1KHz, Vpp=2mV NA Offset 324.7nV 1.219m Table 5.1 contains the characteristics obtained, as well as the characteristics obtained from the Monte Carlo simulation, applied only to the relevant parameters. Monte Carlo analysis setup: •Number of Samples:1000 •Process and Mismatch variation •Statistical Variation obtained from the Monte Carlo technology files (.mc extension) Since the offset and the phase margin are the most important parameters to visualize in the Monte Carlo analysis, their graphics are presented here. This is due to the fact that the phase margin is the most important stability indicator, so we need to assure the amplifier is stable even if some mismatch is present. Regarding the offset, it is one of the most affected parameters with the mismatch of some transistors, and it is also one of the most important requirements of an inamp, making the need for its graphic an obvious one. Figure 5.3 contains the bar graph regarding the variation of the offset, and figure 5.4 contains the bar graph regarding the variation of the phase margin. 46 Simulation and Results −0.2 −0.15 −0.1 −0.05 0 0.05 0.1 0.15 0 50 100 150 200 250 300 Offset Number of Samples Figure 5.3: Monte Carlo analysis regarding the offset. −60 −40 −20 0 20 40 60 80 100 120 0 50 100 150 200 250 300 350 400 450 Figure 5.4: Monte Carlo analysis regarding the phase margin. 5.1.1 Discussion of the Results All results fit the requirements imposed by the myographic signals. Monte Carlo analysis also shows that even with some variations on the transistors, the amplifier will maintain good characteristics. 5.1 Characterization of the amplifier 47 According to the Monte Carlo results, 0.0987 of the transistors would be discarded, which is approximately 10 per cent. Regarding the values obtained, it is important to note that the bandwidth value is quite high, although the amplifier was designed without having regard to the bandwidth - due to the signals it will amplify. However, this only reinforces the idea that this amplifier can be used in a more generic context. 5.1.2 Layout This section contains information regarding the layout, and the simulations done regarding postlayout simulation. Image 5.5 contains the layout produced without the I/O ring. Symmetry was taken into account , to minimize the possible offset. Figure 5.5: Produced layout without the I/O ring. Multiple fingers were used in the transistors that required symmetry the most, and also in order to minimize the area when possible. After assuring that everything was okay regarding the DRC and the LVS, the parasitics were extracted and the post-layout simulation was done using RCX, as well as the Monte Carlo analysis. Table 5.2 presents the characteristics of the extracted layout, along with its Monte Carlo analysis. The stimuli applied in this case was the same as before. The frequency response can be seen in figure 5.6 48 Simulation and Results Table 5.2: Post-layout simulation and respective Monte Carlo analysis. Characteristics Post-layout simulation Monte Carlo Analysis Phase Margin 77.82 51.67 Offset 515.8n -658.2 µ Gain Margin -11.86 -9.565 Closed Loop Gain 20.81 dB 20.81 dB Bandwidth 656.2KHz 641.8khZ 10−2 1001021041061081010 −100 −80 −60 −40 −20 0 20 40 frequency magnitude (a) Magnitude Plot. 10−2 1001021041061081010 −800 −700 −600 −500 −400 −300 −200 −100 0 frequency phase (b) Phase Plot. Figure 5.6: Frequency Response of the amplifier after post-layout simulation. 5.1 Characterization of the amplifier 49 The graphs that contain the Monte Carlo statistics analysis can be found in figure 5.7 −80 −60 −40 −20 0 20 40 60 80 100 0 50 100 150 200 250 300 350 400 number of samples phase margin (a) Monte Carlo analysis regarding the phase-margin of the post-layout simulation. −0.2 −0.15 −0.1 −0.05 0 0.05 0.1 0.15 0 50 100 150 200 250 offset number of samples (b) Monte Carlo analysis regarding the offset of the post-layout simulation. Figure 5.7: Monte Carlo analysis regarding the offset and the phase margin of the post-layout simulation. 50 Simulation and Results Figure 5.8: Produced layout with the I/O ring. For the I/O ring pads the IOLIB_ANA_3B_4M library provided them with ESD protection (50 ohms). To complete the I/O ring , PERI_SPACER cells were used along with corners, both from the IOLIB_3B_4M library. A dummy pad had to be used, to maintain a symmetrical layout. After introducing the I/O ring, the dimensions of the layout were: Height - 1.0416 mm ; Length - 1.265 mm . The dimensions of the amplifier itself were: Height - 0.303 mm ; Length - 0.5442 mm. Chapter 6 Conclusions and Future Work 6.1 Conclusions To build an amplifier, one must always start from the requirements and aim for certain characteristics. However, most of the times that does not happen, as one can easily change the course in the middle of the design. In this case, that happened more than once , and one great example is the fact that the commmon-mode feedback was to be designed from scratch, but in the end, a suitable replacement was found. This choice was made because there was barely any information regarding MOS rail-to-rail CMFB topologies. The idea that was implemented would allow for a rail-to-rail cmfb, but since it did not present fairly good results on schedule it was discarded, and another author’s topology was adopted. Besides that, a new topology for an instrumentation amplifier was achieved, with success. Regarding the post-layout simulation with the I/O ring, it was not performed due to the non-existence of pad models for the schematic, making the passing of the LVS an impossible task. All objectives were also successfully accomplished with the exception of testing the chip. This is due to the fact that the production of the chip takes approximately 3 months, and its submission date was in July (as predefined by EuroPractice). However, the chip will be tested after the conclusion of the Master Thesis. 6.2 Future Work For the future work, it would be recommended to employ a full rail-to-rail cmfb topology, as the one employed is only quasi-rail-to-rail. This amplifier has quite good characteristics, and it may be suitable for various applications. The only downside to it, is the low slew rate. In the case of myographic signals this is not a concerning parameter, however in other applications it might be. Thus it is recommended the increase of the slew rate, if possible. Another suggestion would be to implement along with the amplifier, a driven right leg circuit, to impose the common-mode level in the input of the amplifier, for optimum operation. 51 52 Conclusions and Future Work Appendix A Expressions and simulation setups A.1 Expressions and Calculations A.1.1 Gain Expression for the novel instrumentation amplifier First stage Transistor M1 and M2 are the input NMOS, transistors Mcc are the cross coupled load, and transitor Mp is the transistor that mirrors the current from the PMOS input pair. Av1=gmt1∗Req , in which Req =Ro1//Rcc/2//Ro2//Ropand gmt1=gm1+gmb1 where gmt1=439.7µ, and Req =288K;Av1=126.6 Measured Av1=125.9 Gain stage M1 is the gain transistor, M2 is the diode connected transistor and M3 is the current source of the gain stage. Av2=gm1∗Req, in which Req =Ro1//(1/gm2+Ro3) where gm1=503.8µ, and Req =130.7K;Av1=65.8 Measured Av2=70.8 Total gain Av=Av1∗Av2=8330,28 =78.4dB Measured Av=8913.72 =79dB A.1.2 Pole and zero Locations The zeros and poles here shown are the most important ones. The transistor numbers are the ones shown in chapter 4. Input poles : wp1= (Ro1//Ro5//Ro24//Ro25)∗(Cgd1+Cgd5+Cgd25 +Cgd27 +Cgs27 +Cgd24 + (Cc+Cgd13)(Av1−1) Gain stage poles: (Ro13//(Ro15 +1/gm15)) ∗(Cgd1+Cgs1+(Cc+Cgd13)(1−Av)) Output stage poles: (Ro35//(Ro34)∗((Cgd35 +Cco)(Av−1)+Cgs33 +Cgd33) Error amplifier poles: (Ro6//Ro8//Ro12)∗(Cgd2+Cgs2+Cgd6+Cgs34 +Cgd34 +Cgd8+Cgd12) Gain stage zeros: gm13/(Cc+Cgd13)(1−Rz) 53 60 Overview of Single Stage Amplifiers Bibliography [1] P. Konrad, The ABC of EMG. Noraxon INC. USA, international ed., 2005. [2] M. Wang, T. L. Mayhugh, S. H. K. Embabi, and E. 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