DC/DC Converter with Transparent Electronics for Application on Photovoltaic Panels

FACULDADE DE ENGENHARIA DA UNIVERSIDADE DO PORTO DC/DC Converter with Transparent Electronics for Application on Photovoltaic Panels Romano Jorge de Sousa Torres Mestrado Integrado em Engenharia Eletrotécnica e de Computadores Supervisor: Vitor Grade Tavares (PhD) Second supervisor: Pedro Miguel Cândido Barquinha (PhD) Second supervisor: Pydi Ganga Bahubalindruni (MSc) July 31, 2013 c Romano Jorge de Sousa Torres, 2013 ii Sumário A eletrónica transparente é uma tecnologia emergente que pode proporcionar sistemas de baixo custo dada a possibilidade de fabricação de dispositivos a baixa temperatura. A sua aplicação pode ser útil em vários domínios como indumentária eletrónica e sensores de monitorização de saúde. Com a implementação de conversores DC/DC em eletrónica transparente, as aplicações poderiam extender-se para dispositivos com fonte de bateria ou painéis fotovoltáicos. A tecnologia transparente é baseada em transístores de filme fino (TFT) com semicondutores aIGZO, material que emergiu nos últimos anos. Os transístores podem ser utilizados para a criação do Conversor DC/DC desejado, o qual pode ser depositado do vidro dos painéis, reduzindo os custos de montagem e conceção de todo o sistema. Esta dissertação tem como principal objetivo o projeto e desenvolvimento para construção de uma topologia de conversor DC/DC com eletrónica transparente para aplicação em painéis fotovoltáicos. Inclui o estudo de elementos passivos, como bobinas e condensadores, e a sua possibilidade de utilização. A construção e melhoria do conversor DC/DC inclui o desenvolvimento de um regulador para estabilização da tensão de saída. O trabalho tem a colaboração do grupo CENIMAT da Universidade Nova de Lisboa. Nesse local será construído o conversor DC/DC e os circuitos desenvolvidos nesta dissertação. iii iv Abstract Transparent electronics is a forthcoming technology, which allows for low-cost systems with devices fabricated at low temperatures. Its application may be useful in various domains, such as wearable electronics and sensors for health monitoring. Designing DC/DC converters with transparent technology could extend its application to battery operated devices or photovoltaic panels. Transparent technology, in this work, is based on thin-film transistors (TFT) with a-IGZO semiconductors, material that has emerged in recent years. Their effectiveness for designing DC/DC converters will be assessed. Such converter could eventually be deposited on the glass casing of photovoltaic panels, reducing installation and designing costs of the whole system. This dissertation has in its main objective the development, design and fabrication of a DC/DC converter topology with transparent electronics, for application in photovoltaic panels. It includes the study of some passive elements, such as inductors and capacitors, and their effectiveness for a possible use. The improvement of the DC/DC converter includes the design of a regulator to stabilize the output signal. The work is developed in collaboration with the CENIMAT group at UNL, where the developed circuits and DC/DC converter will be fabricated. v vi Acknowledgments I would like to thank my family for always support me during this master, to believe in my capability and effort to achieve this important objective in my life. I thank my friends, Bruno Silva e Henrique Martins, for the support in all the challenges that this master created. All the study meetings before exams were very important to a successful accomplishment of the course. I would like to thank Bilal Hussain for the help on the inductor simulation and Nuno Cardoso for the development of layout testing files. I also thank my supervisors, Vitor Tavares, Pedro Barquinha and Ganga Bahubalindruni, for all the help and important discussion regarding the accomplishment of this thesis, the advices and the development of TFT simulation model. Romano Jorge de Sousa Torres vii xiv LIST OF TABLES Abreviaturas e Símbolos a-IGZO amorphous Indium Gallium Zinc Oxide DC Direct current FEUP Faculdade de Engenharia da Universidade do Porto ITO Indium Tin Oxide LCD Liquid-Crystal Display LPF Low-Pass Filter MPDV Multiphase voltage doubler PWM Pulse-Width Modulation PCB Printed Circuit Board TFT Thin-Film Transistor TPVD Two-phase voltage doubler UNL Universidade Nova de Lisboa UV Ultra-violet xv Chapter 1 Introduction 1.1 The World of TFTs and Motivation The industry of integrated circuits design is always searching new ways to improve the performance of the electronic devices. During the last century, electronic technology has emerged in such scale, appearing more and more devices that change the global life style and push the humanity towards new targets previously unreachable. Thin Film Transistors are electronic devices that have been studied in recent years due to their low-cost fabrication, which can decrease the cost of application in various domains such as military, radio-frequency, sensors in health monitoring, wearable electronics and much more. The most common application of TFT is the liquid-crystal display technology (LCD). In this situation, TFT can reduce the crosstalk between the pixels, providing a better control of each pixel and improving the image quality in displays. TFT’s are field effect type, and are structurally built from deposition of thin-films on a nonconductive substrate, like glass or ceramic, which have good electrical isolation properties and reduce the parasitic capacitance comparing with monolithic circuits. A semiconductor layer and a dielectric layer are deposited between two metal contacts that represent the source and drain. Besides the improvement of this technology, transparent conducting oxides have been tested to use in TFT’s, in order to create full transparent electronic devices. One of the most used material in recent years is the amorphous Indium Gallium Zinc Oxide (a-IGZO), which various reports suggest a better performance when compared to Zinc Oxide (ZnO). The main focus of this thesis is the study and implementation of DC/DC converters with transparent electronics. The possibility of fabrication processes at low temperature allows the development of TFT on flexible substrates at an evermore low cost. The transparent DC/DC converters could be used on photovoltaic panels by deposition on glass substrate, possibly raising its cost effectiveness. Today, there are many studies concerning climate changes that result from the burning of nonrenewable energy sources, causing emissions of carbon dioxide to atmosphere and developing greenhouse effect. Due to an increasing world population, the energy demand rises, depleting 1 2Introduction petroleum and other non-renewable energy sources. The research on alternative and renewable energy sources is then of outmost importance. Photovoltaic energy is one possibility. Photovoltaic panels often use DC/DC Converters. They are mainly electronic circuits that change the voltage value from input to output, working with direct currents (DC). Their application extend to battery supplied devices, like mobile phones, laptops, typically to increase the voltage provided. Converters are used also on photovoltaic panels. In this case, the converter produces a regulated output voltage from energy temporarily saved, releasing it on a different voltage value, with increasing efficiency. Now-a-days, the inclusion of photovoltaic panels on daily life is possible, by either using the roofs of buildings or large fields, but the creation of transparent devices can be considered as a possibility of embodying the electronics with panels. Such approach could effectively down-size the overall cost of the electronics (low-temperature fabrication) and of assembly (deposition of electronic system on the glass casing). This is the main motivation behind the present proposal for dissertation. 1.2 Generic Proposed Solution The most common DC/DC Converters use inductors as a passive element to store energy, to increase or decrease the voltage level at the output. Due to the fact that transparent materials have lower conductance than metals, there is a large parasitic resistance associated to them. The creation of a high performance inductor, where the coil needed for magnetic field forces it to have a long path, is expected to be a challenging task. The longer the path is, lower is the quality factor of the inductor. To overcome this problem, other different electronic topologies can be used to increase an input voltage with DC current, such as charge pumps and voltage doublers. These devices have the same purpose as the standard ones, but due to their non-inductive behaviour, they can have more undesirable drawbacks. One of them is the increased voltage ripple, that reduce the precision of voltage level at the output. Another limitation is the lack of p-type devices, due to the undesirable levels of carrier concentration, mobility and band-gap that this type of transparent materials have. Only n-type transistors can be used in transparent circuits designed, that forces to a different implementation of the circuits. The lack of investigation in this field is another limitation. The most common studies of transparent electronics are focused on TFT parameters, which the first report is from Nomura et al. in 2004 [16]. Therefore, new electronic topologies will be needed for the design of a DC/DC converter with transparent electronics. The proposal described in this report, for a positive DC/DC converter topology to be implemented with transparent electronics, uses switched-capacitor concepts to circumvent the need for inductive elements. However, there are other issues that need to be taking into account. In chapter 4is presented the proposal of DC/DC converter and a method to regulate the output voltage, with the study of the respective parameters and behaviours that results from that design. 1.3 Structure of the Document 3 1.3 Structure of the Document Besides the introduction, this report has 4 more chapters. Chapter 2discusses the fundamentals and theory behind the construction of DC/DC converters with transparent electronics and their regulation. Chapter 3presents the state of the art, where various studies, closely related to the goal of this dissertation, are exposed. Chapter 4presents the schematic and the layout of the final proposal for the transparent DC/DC converter and the regulation method, with a deep study of the results obtained with the circuit designed. Chapter 5presents the conclusions and the future work that can be made regarding DC/DC converters with this technology. 4Introduction Chapter 2 Background 2.1 Transparent electronic devices Standard DC/DC converters use various components such as resistors, capacitors, diodes and inductors. Regarding the goal of designing such device with transparent electronics, a study about transparency and its effect on the behaviour of passive devices is very important, to analyse how worth is the usage of each component. To create transparent devices, different materials should be combined to perform the same functions of non-transparent devices. The efficiency of new devices created should be, as possible, equal or better to the existing ones. However, the characteristics of transparent electronic materials comparing with the others, like smaller conductivity, decrease their efficiency. There have been many studies to create high performance devices. They focus on the layout of materials, and the results are sometimes very different from what could be expected with nontransparency. 2.1.1 Resistors A good performance resistor should fulfil the characteristic defined by Ohm’s law; it should have a linear behaviour according to this law. Parasitic capacitance is undesirable, therefore those should be fabricated on insulating substrates. Taking advantage of the smaller conductivity of transparent materials, resistors are created with a long path between two contacts. The layout can be seen in figures 2.1 and 2.2. Figure 2.1: Transparent resistor from a planar view [1] 5 6Background Figure 2.2: Transparent resistor from cross-sectional view [1] The passivation layer is created to protect the resistor physically and chemically. The resistance value depends of the parameters from the equation: R=ρL Wt (2.1) where ρis the resistivity of the material, L is the path length, W is the path width and t is the path thickness. The resistance value is proportional to the resistivity of material and the path length. It is inversely proportional to the width and the thickness. To reduce the area of the resistor and obtain the maximum resistance, a rectangular zigzag shape is normally adopted along the resistor length 2.1. 2.1.2 Capacitors Capacitors should have a linear current-voltage derivative characteristic. They are created to store energy in an electric field form. A transparent capacitor can be achieved with a transparent electric insulator between two contacts. The layout can be seen in figures 2.3 and 2.4. Figure 2.3: Transparent capacitor from plan view [1] Figure 2.4: Transparent capacitor from cross-sectional view [1] 2.1 Transparent electronic devices 7 The capacitance value depends of the parameters from the equation: C=εLW d(2.2) where εis the insulator dielectric constant, L is the length and W is the width of the overlapping area, and d is the dielectric thickness. The capacitance is proportional to the insulator dielectric constant and the plates area. It is inversely proportional to the insulator thickness. 2.1.3 Inductors Inductors store energy in a magnetic field, but due to poor conductance and consequently high parasitic resistance of transparent materials, it is difficult to create these devices with linear voltagecurrent derivative as expected. In fact, the resistance related to the transparent material is so high, that the large number of turns needed for inductor increases the length of material and consequently the parasitic resistance [1]. With high parasitic resistance, the quality factor of inductor will be low. Therefore, other ways to create DC/DC converters need to be studied. One possible solution can be voltage multipliers, referred in the next section. 2.1.4 Thin-film transistors (TFT) TFT’s use the principle of insulated-gate field-effect, which work with similar principals of the MOSFET transitor. The differences between the two devices are the properties of the materials, their fabrication and the smaller thickness of the semiconductor. In fact, the TFT’s are fabricated on the top of an insulating substrate, as opposed to MOSFET technology, that uses the semiconductor as substrate. This difference reduces the parasitic capacitance associated to diffusions that occur in monolithic circuits. The basic function of these devices is to control the current between drain and source with an input voltage at the gate (to the source). Due to their characteristics, transistors can be used as a switch or even as a diode. The ability to set the device in multiple operation modes makes them the core of electronics. Different structures of the device are possible and various technological parameters can change their characteristics. There are four different structures of TFTs studied, the staggered bottom-gate, staggered top-gate, co-planar bottom-gate and co-planar top-gate structures. The different layouts can be observed in figures 2.5 and 2.6. Classification differs with the relative positions of the channel (semiconductor), insulator, gate, source and drain. If the contacts are at the same level as the channel, it is a co-planar structure, otherwise it is staggered. The designation of top-gate and bottom-gate differs on the gate position as the name suggests. 14 Background 2.1.5.5 Atomic layer deposition The thin-film layers are obtained from a sequential exposure of precursors, or chemical gases, reacting with the substrate. It is a self-limiting process, which enables a control on growth deposition and uniformity even on large areas, and it differentiates from chemical layer deposition due to the separation of precursors by inert gas during reaction. 2.1.5.6 Physical vapour deposition These processes create deposition of atoms from a source onto a substrate. The two mainly processes of this type are evaporation and sputtering. In the first, it is created by a resistive heating with electric current. While the material is melting and evaporating, the vapour material condenses, creating the thin film. The second one, sputtering, uses the collision of gaseous ions to dislodge atoms while thin film is deposited. It is a very controllable technique in terms of thickness of the film, and very used nowadays. CENIMAT, a Portuguese scientific research centre, uses the RF sputtering technique [26]. It utilizes energy from radio waves to ionize the gas atoms. Further, the ions get in contact with the substrate, creating the film. 2.2 Voltage Multipliers Voltage multipliers or charge-pumps use capacitors and switches or diodes to achieve a different output voltage. The principle of operation is to store energy in capacitors, charging and discharging, transferring it to the output load [5]. The study of these devices can be important for the implementation of transparent DC/DC converter, because it could enable the desired functionalities of a normal DC/DC converter without using inductors, avoiding the problems referred to the construction of a transparent inductor, such as the low quality factor. 2.2.1 Output Voltage and Load Current In order to build a background on specific parameters, behaviour of the charge-pumps and to understand the principles of functioning that exist in these devices, some of the initial chargepump topologies created will be presented. The first voltage boosting circuit designed was the Cockcroft-Walton [3], presented in figure 2.12. Vin CLK2 CLK1 C C C C C C C Cs Cs Cs Cs Cs Cs Cs Cs Vout Cs Figure 2.12: Cockcroft-Walton configuration [3] 2.2 Voltage Multipliers 15 This circuit uses n-stage diodes connected to coupling capacitors that are charged by the clock signals with the same voltage level as Vin, and provide this charge to the output stage. With N stages, the output voltage expected would be (N+1)Vin if the non-ideal characteristics are not taken into account. In a way of improving, J. Dickson [4] modified the circuit, connecting each of the coupling capacitors directly to the clock inputs, designing the capacitors in parallel. The circuit is presented in figure 2.13. CCC C Cs Cs Cs Cs Vin CLK1 CLK2 Vout Figure 2.13: Dickson charge pump [4] The increased voltage in each stage is given by: VN−Vin =VC−VD−VL(2.11) where VCis the voltage level due to the coupling capacitors, given by the ratio VC=C C+CSVCLK , VDis the voltage drop in each diode and VLis the voltage that the capacitors charge and discharge with a load current at the output given by Iout =f(C+CS)VL(f is the clock frequency). The final expression for N stages is given by: VN−Vin =N[( C C+CS )VCLK −VD−Iout (C+CS)f](2.12) The maximum output resistance of a charge-pump with N stages depends of the frequency and the pumping capacitors by: Rout =N fCCLK (2.13) An important theoretical analysis of the charge-pumps is made by R. Perigny [27]. This author calculates the output voltage level of one stage of a charge-pump with an inclusion of ripple maximum and minimum level. In the load capacitor, the charge Qload accumulated when the lower voltage Vlow is applied to the terminals is: Qload =CloadVlow (2.14) 16 Background When the boosting capacitor Cais charged to VDD, the charge is expressed as: Qa=CaVDD (2.15) When Caconnects to Cload, it is applied the voltage Vhigh, and the charge at the load Qload2is: Qload2=CloadVhigh (2.16) At this time, the charge stored in the boosting capacitor is: Qa2=Ca(Vhigh −VDD (2.17) The principle of conservation requires that: Qa+Qload =Qa2+Qload2(2.18) The slope at the output is given by Iout /(Cload +Ca, and it decreases in half clock period, so: Vhigh =Vlow +Iout 2fclk(Ca+Cload (2.19) Combining the two equations and simplifying, the lower voltage is given by: Vlow =2VDD −Iout 2fclkCa (2.20) With no load current, the output voltage is estimated by 2VDD, but this level changes when it is applied a load resistance at the output, creating a load current. Therefore, there is a decrease of Io/Caon the output voltage, where Cais the pumping capacitance, so the voltage difference between maximum and minimum, with a clock frequency of fclk, is: ∆Vout =Io 2fclkCa (2.21) If a load capacitor Cxis added to the output, the voltage ripple is not so large, due to the slower transition of voltage level. The slope can be calculated by: ∆Vout =Io 2fclk(Ca+Cx)(2.22) With the voltage ripple calculated, the minimum voltage level is the difference between 2VDD and ∆Vout without the load capacitor. Notice that the load capacitor is used only to reduce the maximum voltage Vhigh, and it does not have influence on the Vlow. The maximum voltage is: Vhigh =Vlow +Io 2fclk(Ca+Cx)=2VDD −Io 2fclk(Ca+Cx)+Io 2fclk(Ca+Cx)(2.23) 2.2 Voltage Multipliers 17 This expression does not take into account the on-resistance of the diodes, that reduce the output voltage as higher as the resistance is. In chapter 3will be presented and discussed newer and improved topologies, which reduce some constrains that exist in these circuits. 2.2.2 Power and Efficiency Efficiency is an important parameter to study when DC/DC converters and charge-pumps are designed. D. Baderna et al. [28] calculate the efficiency by the relation between the power at input and output. The power at the input is equal to the sum of power at the output, added by the resistive and dynamic losses, so the efficiency is: η=VoutIout VoutIout +Pres +Pdyn =VoutIout VoutIout +Rout,idI2 out +kN fCparV2 DD (2.24) where k is a coefficient of proportionality and Cpar is the equivalent parasitic capacitance in each stage. The author divides the parasitic capacitance in two parts, Ctop and Cbot . The first component is more dependent of the topology, because it is created by the design of wider transistors and the voltage level that the transistors have in their terminals. If C represents the value of the pumping capacitors in each stage, the output voltage of the both devices can be calculated as: Vout =C C+Ctop [(N+1+β)VDD −Rout,idIout](2.25) The effective output resistance is Rout =C C+Ctop Rout,id, and the maximum load current that the devices can deliver is Iout,max =NVDD Rout,id =fCVDD, so the efficiency can be estimated as: η=VDDIout (N+1+β−Rout,idI2 out VDDIout (N+1+β)+(α+β)(1+β)N fCV2 DD (2.26) The conclusion is that the efficiency ηdecreases as higher as βis. J. Starzyk [5] compare different charge-pump designs on the boosting energy required. Since the load resistance is not infinite, the circuits do not present a perfect behaviour, such as Vout/Vin = 0.5 in step-down and Vout /Vin =2 in step-up converter. The output voltage is as lower as the load resistance is. The author [5] present a two-phase voltage doubler (TPVD) with the design in figure 2.14. The doublers can be used in cascade as represented in figure 2.15. Removing the second capacitor in each doubler, J. Starzyk [5] presents a multiphase voltage doubler (MPVD), which need half of the capacitors for the same output/input voltage ratio. The circuit is shown in figure 2.16. Starzyk compares the improved charge-pumps to the standard one from Dickson in figure 2.17. Some of the Starzyk’s conclusions [5] are that the number of stages used does not affect the output power. It depends on the load resistance, capacitors and clock frequency. When the value 18 Background Vin Vss CL Vo2 1 2 1 C1 +- Figure 2.14: Voltage doubler [5] Vin Vss 2 1 2 1 C1 +- Vss C2 C4 2 1 12 C3 Vss CL C2n-1 2 1 12 RL Vo Figure 2.15: Simply cascade voltage doublers [5] Vin Vss 2 1 2 1 C1 +- Vss C2 Vss CL RL Vo 43 3 4 Cn 2n 2n-1 2n-1 2n Figure 2.16: Multiphase voltage doublers [5] Vin 1 2 Vo CL CCCCCCC Figure 2.17: Dickson charge pump [5] of capacitors increase, power increases. The author estimates the boosting energy for Dickson 2.2 Voltage Multipliers 19 charge pump as: WD=(N+1)(N+2) 12 AV 2 in (2.27) where A is the designed area with equal capacitors and N is the ratio Vout/Vin. The TPVD’s topology has a boosting energy of: Wt p =5(N2−1)A 12log2NV2 in (2.28) and for MPVD’s topology: Wmp =(4N2−1)A 6log2NV2 in (2.29) The results show that for TPVD’s and MPVD’s energy depends less than quadratically with voltage gain [5]. For Dickson’s charge pump, the dependency is higher. In fact, the output power for the same load resistance is higher on Dickson’s charge pump and lower on TPVD’s. TPVD’s presents also lower rise times than MPVD’s. 2.2.3 Step-Up and Step-Down - a question of design M. Wens and M. Steyaert [6] presented another example of charge-pump step-up DC-DC converter based on charge-pump, as shown in figure 2.18, studying its output voltage level and efficiency expected. + − S1 S2 S2 S1 C1 C2Vin RL Vo + - Figure 2.18: Charge-Pump Step-Up Converter [6] When the switches are at position 1, the voltage source charges capacitor C1.CLdischarges to RL. When the switches are at position 2, the lower terminal of C1connects in series with the voltage source, and CLand RLreceive charge from the both. Hence, the output voltage is higher than the input. Makowski in [5] refers that the Vout /Vin ratio is limited by 2n, where n is the number of capacitors used. M. Wens and M.Steyaert [6] estimate the output voltage for ideal converter by: Vout =RLIout =RLfSW ∆QSW =RLfSW C1∆VC1=RLfSWC1(2Vin −Vout)(2.30) 20 Background Vout =RLfSW C1V in 1+RLfSWC1(2.31) where fSW is the switching frequency, ∆QSW is the amount of charge being transferred to the output in each switching cycle and ∆VC1is the difference of voltage level between switching state 1 and 2. The efficiency of the converter is divided by the two stages of switching. The efficiency on first stage is calculated by the energy in C1divided by the energy transferred to the capacitor: ηΦ1=EC1 EVin→C1 =Vout 2Vin (2.32) When C1is discharged, the efficiency is estimated with the energy in C2divided by the energy transferred from source and C1to C2: ηΦ2=EC2 EVinC1→C2 =2C1Vin +C1Vout +2C2Vout 4C1Vin +2C2Vin +C2Vout (2.33) The resulting efficiency of the circuit is: ηup =ηΦ1ηΦ2=Vout(2C2Vout +C1(2Vin +Vout)) 2Vin(4C1Vin +C2(2Vin +Vout)) (2.34) The authors in [6] estimate an efficiency between 35% if Vout/Vin =1 and 100% if Vout/Vin = 2. This circuit has some issues due to the large number of switches comparing with pumping capacitors. For the transparent technology, the switch is substituted by a TFT with larger onresistance. The voltage level is reduced if there are many transistors used on the converter main path. Besides, there is no full time boosting to the output, because it is used an output capacitor to hold the voltage level at good level. However, a large ripple at the output is not avoided. Beyond the analysis of a step-up charge-pump, there is also the possibility to create a stepdown circuit. This one returns a lower voltage at the output than the applied at the input. M. Wens and M. Steyaert [6] present an example of charge-pump step-down DC-DC Converter based on voltage doubler in figure 2.19. + − S1 S2 S2 S1 C1 C2 Vin RL Vo + - Figure 2.19: Charge-Pump Step-Down Converter [6] 2.3 Operational Amplifiers with transparent TFT’s 21 When the switches are at position 1, capacitors C1and C2are charged by the connection in series with the voltage source. A portion of current goes also through RL. With switches at position 2, there is no connection with the source, C1discharges its energy to C2and RL. With this principle of switching, Vout will be, ideally, Vin/2. Physically, the authors [6] estimate the output voltage using the same fundamentals as with the step-up converter: Vout =RLIout =RLfSW ∆QSW =RLfSW C1∆VC1=RLfSWC1(Vin −2Vout)(2.35) Vout =RLfSW C1Vin 1+2RLfSWC1 (2.36) To estimate efficiency, on the first switching position, the energy in C1and C2is divided by the energy transferred from voltage source to these capacitors: ηΦ1=EC1C2 EVin→C1C2 =Vin +2Vout 2Vin (2.37) On the second switching mode, efficiency is calculated by the ratio between the energy in C2 and the energy transferred from C1to C2: ηΦ2=EC2 EC1→C2 =C1Vin +2C2Vout Vin(2C1+C2)−2C1Vout (2.38) Total efficiency of the circuit is obtained multiplying both values: ηup =ηΦ1ηΦ2=(C1Vin +2C2Vout )(Vin+2Vout 2Vin ) C2Vin +2C1(Vin −Vout)(2.39) The same authors [6] estimate an efficiency of 100% if Vout/Vin =0.5. This value decreases with lower values of Vout/Vin. Analysing the step-up and step-down circuits, there can be concluded that the difference between a step-up and step-down converter is the position of first capacitor, namely, the flying capacitor C1. As referred in last subsections, on the second switching position, step-up converters have this capacitor connected in series with RLand the input source. In fact, the voltage source is never disconnected from the rest of the circuit, in contrast to step-down converters. Therefore, step-down converters have the flying capacitor always connected to output, in opposition to the step-up that has it always connected to the input. The adaptation of the converter for a desired output voltage is achieved with a different schematic of the circuit. The position of capacitors influences the output voltage level, so the design of circuit must take into account what is expected. 2.3 Operational Amplifiers with transparent TFT’s The questions of transparency changes not only the design of DC/DC Converters, but also the limitations of an operational amplifier. In fact, the most important difference that exist between 22 Background a non-transparent and transparent amplifier is the lack of p-type transistor devices. This section presents the different existing stages and factors that must be taken into account when an Op-Amp with only n-type transistors is designed. 2.3.1 Single-Stage Amplifiers 2.3.1.1 Common-Source Stage The common-source stage is one of the most common stages in an Op-Amp. The configuration is presented in figure 2.20 Vdd Vin Vout M1 Rd Figure 2.20: Common-source stage One of the most important characteristic that this topology presents is the small-signal gain presented by: Av=−gm(RD||ro)(2.40) Analysing this configuration, this stage can be used to invert the signal due to the negative gain. It can be well used to increase the small-signal gain, if a correct combination of the transistor output resistance ro, and the load resistance RD. To have higher values of gain, the resistances should be similar to have a high value of equivalent resistance. The voltage gain of this topology has a high dependence on the intrinsic parameters of the transistor, which can be prevented with a common-source stage with source degeneration, presented in figure 2.21. If a resistance is applied to the source of the input transistor and the expression of small-signal gain is: Av=−gmRD 1+gmRs (2.41) And the equivalent output impedance is: Rout =RD||ro(2.42) If gmRs>> 1, the gain expression is more dependent of the resistance ratio Av=−RD Rs. 2.3 Operational Amplifiers with transparent TFT’s 23 Vdd Vin Vout M1 Rd Rs Figure 2.21: Common-source stage with source degeneration 2.3.1.2 Source-Follower Stage This stage is mostly used to connect high load impedance stages to low impedance stages, operating as a voltage buffer. The schematic is presented in figure 2.22. Vdd Vin Vout M1 Rs Figure 2.22: Source-follower stage The small-signal gain for this stage is: Av=gm(Rs||ro) 1+gm(Rs||ro)(2.43) With the gm in this expression, the gain begins from zero with Vin =Vth, and increases with higher values of Vin, with a approximation to 1. To have a lower dependence of the current to the input voltage level, a transistor operating in saturation region can replace the resistor Rs. This transistor will work as a current source. The output impedance is estimated by: Rout = (1/gm)||Rs||ro(2.44) Comparing with common-source stage, source-follower presents a lower output resistance, due to the low values of 1 gm. 30 Bibliographic Review field-effect mobility of 24.5cm2/V.s, maximum drain-source current of 0.08mA and threshold voltage Vth =12.8V. The transistor was created in a staggered bottom-gate structure with a 100 nm thick SiO2gate dieletric, a Ti/Au contacts with 15 nm and 135 nm of thickness, respectively, and 50 nm-thick a-IGZO layer deposited by RF sputtering. Annealing was performed after all depositions. In 2009, K. Nomura et al. [29] reported a bottom-gate TFT with saturation mobility of 12.6cm2/V.sand a threshold voltage between 1.4 V and 1.8 V. TFT’s were created on SiO2substrate. A 40 nm-thick a-IGZO was deposited by pulsed laser deposition with oxygen partial pressure and a width and length of 300 and 50 µm, respectively. The device was subjected to annealing with water vapour at partial pressure, and Ti/Au were used for source/drain contacts. A. Suresh et al. [30] in 2010 created an a-IGZO TFT using staggered bottom-gate structure. Gate dielectric was deposited with 120 nm-thick Al2O3with atomic layer deposition. A 40 nmthick a-IGZO layer and 200 nm-thick indium tin oxide were created by physical vapour deposition. No annealing steps were employed. The authors present a threshold voltage of 3.5 V and saturation field effect mobility of 15cm2/V.swith VDS =20V. There was reported a leakage current of 1pA. S. Hong et al. [10] use in their transparent DC/DC converters a-IGZO TFT with co-planar top-gate structure. As source-drain material, there is deposited by sputtering indium-tin oxide. For the insulator there was used Al2O3deposited by atomic layer deposition at 150oCThe results present a threshold voltage of -0.8V to reach a drain current of 100pA, 20.6cm2/(V.s)of field effect mobility and a subthreshold slope of 0.2 V/dec at room temperature. D. Kang et al. [31] created in 2011 a TFT using co-planar top-gate structure. On 200 nmthick glass substrate, a 20 nm-thick a-IGZO layer was deposited using sputtering. For insulator, the authors used 200 nm-thick SiO2and patterned molybdenum for gate electrodes. After patterning a-IGZO and etched SiO2, a 400 nm-thick SiNxlayer was deposited. Then, a 200 nm-thick molybdenum was deposited for source-drain contacts. With VG=20V, field-effect mobility is 24.7cm2/V.sin saturation mode and 21cm2/V.sin linear mode. Threshold voltage is around 3.6 V. The different studies made suggests a improvement on TFT behaviour, with better field-effect mobility, lower threshold voltage and lower resistance. During the years, various materials for insulators and source-drain contacts were tested and results were compared. For channel layer, a-IGZO is actually the material with best performance. For the source-drain contacts, the main materials reported with better results are Ti/Au and molybdenum. Analysing the performance of the TFT depending of the structure used, the recent reports suggest better results of mobility with a top-gate structure, due to the better isolation of the channel to external factors. The transparent TFT fabricated in CENIMAT use the staggered bottom-gate structure, so the performance of the transistor in terms of mobility is not expected to be higher than 20cm2/(V.s). The effects of 3.2 Charge-Pumps 31 high on-resistance in charge-pumps and DC/DC converters using switched-capacitor stages were discussed in chapter 2. 3.2 Charge-Pumps This section presents the charge-pumps designed during the years. Initially, there is considered the first topologies in non-transparent electronics. Later, the configurations designed with transparent TFT’s. 3.2.1 Non-transparent designs 3.2.1.1 Initial Configurations The first charge-pump reported are dated from 1932, with the Cockcroft-Walton multiplier [3]. As mentioned in the last chapter, it used clock signals to charge the capacitors and diodes through the main path, increasing the voltage in the output to an expected voltage of 2VDD. However, the circuit has some constrains. One of them is that the coupling capacitors C must have a much larger value of capacitance than the stray capacitances Cs, to have an efficient voltage increase. Due to the high values of stray capacitance in the substrate of monolithic circuits, the circuit has limitations on efficient voltage multiplication. Besides, the voltage drop associated to the diodes limits the output voltage level even with a large number of stages. With transparent technology, diodes are replaced by TFT’s, which several constrains were discussed such as the on-resistance and voltage drop. Another initial configuration referred in the last chapter is the Dickson’s charge-pump dated from 1976 [4]. This is a improve of the Cockcroft-Walton configuration, due to the connected pump capacitors directly to the ground. According to the author, this enables a smaller difference between the coupling and stray capacitances, in order to have efficient multiplication of voltage. Although the problem with stray capacitances is reduced, the voltage drop across the diodes is not avoided. Furthermore, there is a high threshold voltage needed for the transistors, due to the differentiation between switching stages, and a large voltage drop across the transistor when the following capacitor is transferring its charge. These facts increase the parasitic capacitances associated to the circuit, according to Baderna [28]. These capacitances reduce the time response of the circuit and the maximum frequency allowed, resulting in worse response of the circuit to the load currents. 3.2.1.2 Cross-connected Configuration P. Favrat et al. [7] proposed a new voltage doubler with cross-connected transistors to reduce the parasitic capacitances, improving the charge-pump cell from Y. Nakagome et al. [32] with a double series switch of p-type transistors. The circuit is presented in figure 3.1. With the two series p-type transistors added, the author refer that the load capacitor have not to be very high, without affecting the charge-pump efficiency. The cross-connection reduces 32 Bibliographic Review Vdd Vout CLK1 CLK2 C C M1 M2 M3 M4 M5 M6 Cb Cout Figure 3.1: Cross-connected configuration from P. Favrat et al. [7] the voltage drop on the transistors to a value lower than VDD, because when one capacitor is discharging, the opposite side is charging, creating a full reverse bias of the junctions. The onresistance is also lower, due to the synchronization of boosting on gate transistors. The Favrat voltage doubler, with a cross-connected topology, has transistors with lower parasitic capacitance than the first topology, increasing the efficiency. Theoretically, Baderna [28] estimates the Dickson’s charge-pump efficiency as 44.8%, and 56% for the Favrat’s doubler efficiency. The p-type transistors can be substituted by a diode-connected TFT’s, to answer to the transparent constrains. 3.2.1.3 Switch Bootstrapping Technique The parasitic capacitance and output voltage level are two of the main concerns when a DC/DC converter using charge pumps topology is created. According to Y. Allasasmeh and S. Gregori [8], the usage of bootstrapping switches prevents short-circuit losses, due to the precision in controlling the switching times, and enables good efficiency with low supply voltage, due to a lower switch on resistance and lower power losses. The schematic of bootstrapping topology for a voltage doubler is presented in figure 3.2. Vdd Vdd Vout Nb1 Nb2 N1 N2 Cn1 Cn2 P1 P2 Pb1 Pb2 Cp1 Cp2 C1 C2 CLK1 CLK2 CLK2 CLK1 CLK1 CLK2 CLK1 CLK2 Nd2 Nd1 Pd1 Pd2 Figure 3.2: Bootstrapping configuration of charge-pump from Allasasmeh and Gregori [8] 3.2 Charge-Pumps 33 Due to the added transistors and capacitances are not in the main current path between VDD and Vout, the authors [8] refer that their area can be reduced, decreasing the parasitic capacitances. This phenomenon is helped with the fact that the gates of the first transistors are not connected to the main current path. They also report a higher output voltage in 1.5% due to this fact. 3.2.1.4 Switched-Capacitor based Embedded DC-DC Buck Converter B. Maity and P. Mandal [9] present a non-transparent device that uses switched-capacitors to create a step-down DC/DC converter. The importance of this reference is the use of concepts that can be applied on the desired transparent DC/DC converter. The design is presented in figure 3.3. Vdd M1 M5 M2 M6 M3 M7 CL RL Vout Cf1 Cf2 M8M4 1 2 2 1 Figure 3.3: Switched Capacitor based Buck Converter [9] Internal signals are used to control half of the switches, in order to reduce switching power loss and output ripple noise. The circuit shown in figure 3.3 is repeated 11 times and their output connects together with load capacitor and current source. For a 10 mA current, results present a 1.35 V, with an input voltage range between 2.9 V and 3.8 V. For this voltage level, and a 25 mA load current, output ripple is 8 mV. Efficiency established on 79.5% for a load current between 1 mA and 25.5 mA. When the output voltage increases to 1.55 V, with load current from 1 mA to 7 mA, a peak power efficiency of 87% is achieved. This proposal uses p-type transistors, which can easily be replaced by n-type. 3.2.2 Configurations with TFT’s 3.2.2.1 DC/DC Converters using Indium Gallium Zinc Oxide Thin-Film Transistors S. Hong et al. [10] present the most close device to what we need to achieved. The proposed positive DC/DC Converter is presented in figure 3.4. It has eight n-type IGZO TFT’s, four pumping capacitors and two storage capacitors. When CLK =1, the voltage level of node D is 2VDD because it receives the energy stored on capacitor C1. Node C has a voltage level of 2VDD −Vth due to voltage drop across transistor N3. Therefore, node 34 Bibliographic Review Vdd C A B D E N1 N2 N3 N4 N5 N6 C1 C2 N7 N8 C3 C4 C5 C6 Vout CLK CLKB CLKB CLK Figure 3.4: Transparent Step-Up DC/DC Converter [10] B will receive the energy stored in capacitor C5, so its voltage level becomes 3VDD −2Vth. With the voltage drop in transistor N8, output voltage level is 3VDD −3Vth. The same sequence happens in complementary nodes with CLKB =1. As Vth << VDD, the output voltage level is higher than the input voltage level. The authors [10] compared the behaviour of positive circuit design proposed with Dickson’s charge pump and positive cross-coupled DC/DC converter using n-type TFT’s, presented in figures 3.5 and 3.6. Vdd CLK CLKB Vout Figure 3.5: Dickson charge-pump [10] With a supply voltage of 10 V and no load current, positive DC/DC converter presents an output voltage level of 25 V. On other hand, Dickson’s charge pump presents 25.5 V and positive cross-coupled DC/DC converter presents 19.5 V. With a load current of 250µA, output voltage levels are 21.3 V, 20.4 V and 16.1 V respectively. In this case, the power efficiencies measured are 69.5%, 58.4% and 77.3%. The values show that Dickson’s charge pump has a good output voltage level, but its efficiency is much lower than the other circuits. Cross-coupled DC/DC converter has good power efficiency, but its output voltage level is lower than the others. The authors explain this fact with low driving capability of n-type TFT’s on source follower structure during pull-up. The proposed positive DC/DC converter has also a better behaviour with load current. Its 3.2 Charge-Pumps 35 Vdd CLK CLKB Vout C3 N1 N2 N3 N4 C1 C2 Figure 3.6: Cross-coupled DC/DC converter [10] output voltage decreases less than others, and power efficiency approaches the values of crosscoupled design. S. Hong et al. [10] also proposes a negative DC/DC Converter with six n-type IGZO TFT’s, four pumping capacitors and one storage capacitor. The layout is presented on figure 3.7. GND Vout CLKBCLK CLK CLKB C2C1 A BN1 N4 N2 N3 N5 N6 C4C3 C5 E C D Figure 3.7: Transparent step-down DC/DC converter [10] With CLK =1, node C connects with the ground, so its voltage level is 0. The energy stored in capacitor C4turns the voltage level of node D to −VDD. The output voltage level is −VDD because the transistor is turned on. As in positive converter, the same sequence happens in complementary nodes with CLKB =1. So the output voltage, on ideal behaviour, will always be −VDD. The authors [10] compare the behaviours of negative circuit design proposed with Dickson’s negative charge pump and negative cross-coupled DC/DC converter, shown in table 3.1. Cross-coupled DC/DC converter Dickson’s charge pump Proposed DC/DC converter Output Voltage (V) -4.5 -3.8 -5.1 Power Efficiency (%) 47.1 45.2 56.1 Table 3.1: Simulated results of negative DC/DC converters with load current 36 Bibliographic Review The proposed negative DC/DC converter presents a lower output voltage level and better power efficiency. The results for both proposals suggests a good efficiency and constant output voltage, which allows an increasing knowledge on how to reduce undesired behaviours, such as parasitic capacitance and resistance. 3.2.2.2 DC/DC Converters in Organic Thin-Film Transistor Technology H. Marien et al. [11] propose a DC/DC converter using organic thin-film transistors with a modified Dickson’s charge pump. Organic technology only uses p-type transistors in contrast to transparent TFTs. The authors report some advantages of this technology, as the production at low-temperatures, reduced complexity and cost of the process. However, low mobility, transistor parameters variations and influence of oxygen and water, like transparent technology, are real limitations. The schematic is shown in figure 3.8. + −+ − Vin Vdd CLKB CLK CLK CLKB CL VoutCLKCLKBCLKCLKB C1 C2 C3 Figure 3.8: DC/DC converter design in organic technology [11] The authors [11] describe the ideal output voltage with the following formula: Vout =Vin +N(Vdd −Iout fCD )(3.1) N is the number of stages of charge pump, Iout is the output current, fis the clock frequency and CDthe capacitor value for each stage. Internal leakage current is estimated with and without 10µA load current by: Iint =10µA4Vdd −Vout1 Vout1−Vout2 (3.2) where Vout1is the output voltage with Iout =0 and Vout2is with a current of 10µAat the output. The power efficiency follows the equation: ηpower =10µA Iint +10µA(3.3) Simulation shows an output voltage level around 75 V with a voltage source of 25 V and no load current. With 10µAload current, output voltage is more than 10 V lower. It is very unstable, with a visible difference. Efficiency achieved is around 48%, which is relatively small. Authors in [11] explain it with leakage in capacitors. This proposal use a design based on Dickson’s charge pump. It uses a large number of capacitors and transistors, increasing the problems referred in 3.3 Regulators 37 chapter 2with large use of these devices. Dickson’s charge pump was compared with other topologies in [10] and [5], with worse results for the first one. 3.3 Regulators To have a constant output voltage level at the output of the DC/DC converters, several regulation topologies have been presented. The regulation can be achieved by linear or pulse-width modulation. This section presents the state-of-the-art for regulation of DC/DC converters. 3.3.1 Linear Regulation In 2009, K. Bhattacharyya et al. [12] presented a linear regulator with a differential pair amplifier and a current mirror configuration, to control the load current and reduce the voltage ripple of the DC/DC Converter designed. The schematic of the linear regulator amplifier is presented in figure 3.9. Figure 3.9: Proposal of linear regulator from Bhattacharyya et al.. Image obtained in [12] It is used in the DC/DC converter configuration as shown in figure 3.10. The current mirror introduce a reference current on the differential pair stage. The input voltages are applied on the p-type transistors. The n-type transistors are used to introduce the same current at the both sides of the differential pair, as a second current mirror. The differential pair compares the voltage received in the inputs, applying an output voltage as mentioned in last chapter. In 2010, B. Maity et al. [13] designed a regulator with a push-pull structure for feedback loop, as presented in figure 3.11. The output of the regulator is applied to the input of the DC/DC converter. A dual pushpool is introduced to increase the bandwidth and to have faster response during transient. The configuration is presented in figure 3.12. 38 Bibliographic Review Figure 3.10: Schematic of regulation from Bhattacharyya et al. [12]. Image obtained from [12] Figure 3.11: Proposal of linear regulator from B. Maity et al. [13]. Image obtained from [13] Figure 3.12: Schematic diagram of regulation from B. Maity et al. [13]. Image obtained from [13] 3.3 Regulators 39 The frequency stability of the amplifier is ensured with a RC compensation to increase the frequency stability, that would decrease by the influence of three poles, the one at the output of the error amplifier, the one at the input of the pass transistor and the one associated to the load, with a value of 1/RCCC. The comparison is made with two differential pairs, one of them with a telescopic cascode stage to increase gain. Results show a peak output voltage of 117% of the steady state voltage and a dip voltage of 81.4% of the stead-state. In 2011, Maity et al. [14] added a differential current starved inverter to have good levels of efficiency independent of the load current required. The inverter changes the levels of frequency depending of the current that goes through each side. The inverter controls the voltage control oscillator to give a lower frequency with lower load currents, reducing the switching losses. The schematic of the inverter and the circuit where it is used is presented in figure 3.13. Figure 3.13: Schematic diagram of regulation with inverter from B. Maity et al. [14]. Image obtained from [14] The results reported introduce a larger range of load current that can be applied, due to the optimization of the circuit to the changes of this parameter. Without the inverter, the output voltage level of the circuit has a large decrease above 25mA of load current. With the inverter, the output voltage becomes more stable even with an increasing load current. 3.3.2 Pulse-Width Modulation The pulse-width modulation (PWM) is another technique to regulate the output of DC/DC converters. This technique was used by several authors not only for the regulation of the output voltage and compensation to have the desired voltage level, but for the stability of the voltage multipliers against load variations as well. Although the various authors use different voltage multiplier topologies, the main idea behind the PWM regulation is basically the same. In figure 3.14, it is presented the configuration of PWM controller presented by Y. Chang [15]. The load current of the charge-pump enters in a low-pass filter (LPF) to the high-frequencies rejection. Then, the current is compared with Ire f using a high-gain amplifier, in order to have the 46 Proposed Configuration be very high, causing a high difference of voltage level between source and gate of transistor TFT5/6. Two more boosting stages and one separation stage were designed to increase the output voltage level. In a way to reduce the on-resistance of the TFT’s, were designed four transistor of 320µmin parallel for each diode or switch connection, except on the bootstrapping stage in TFT1 and TFT2, because they are not in the main path between the input and the output. The overall resistance of the DC/DC converter only considers the main path of the circuit between input and output. A high TFT on-resistance decreases the voltage level between drain and source, and can increase the time response of the circuit, by an increasing time constant RC. Thus, the boosting capacitors does not have enough time to charge, resulting in a lower output voltage level. However, the large TFT’s used can increase the parasitic capacitances associated and the charge injection effect, and the efficiency drops. The sizing of the boosting capacitances was made by analysing the time constant, ripple and load current. The size of each capacitor is presented in table 4.2. Capacitor C1 and C2 C3 and C4 C5 and C8 C6 and C7 C9 and C10 Size (pF) 100 200 100 400 500 Table 4.2: Sizing of the capacitors for the proposed DC/DC converter The amplifier created for regulation needs around 100µAof current, so the DC/DC converter should present a load current of 200µAif the case of using the DC/DC converter connected to other circuits is considered. The ripple voltage on a boosting stage can be calculated by R. Perigny [27] analysis: ∆V=Io 2fclkCa (4.1) With a switching frequency of 1MHZ, for a 100pF boosting capacitor, the voltage ripple is 1 V. With 500pF, it is 0.2 V. The output voltage depends of boosting capacitance Cbin each stage by replacing Vhigh and Vlow calculated in the analysis by R. Perigny [27]: Vout =2VDD −Io 2fclkCb +Io 2fclk(Cb+Cload)(4.2) Analysing the equation, if a load capacitance is used, the output voltage has reasonable values with boosting capacitances above 50pF. The capacitors should not be very large to not exceed area constrains, so depending on the efficiency, time response and ripple voltage desired, the values of capacitance are chosen. Another detail to be considered is the level of approximation to the output. If the larger capacitors are closer to the output, the ripple is lower with the correction of ripple created by the initial stages. This fact explains the different values of boosting capacitors for the proposal designed. 4.1 DC/DC converter 47 The load devices are designed depending of output voltage, current and frequency used. If the DC/DC converter returns 16 V at the output, to achieve a current of 200µit is necessary a load resistor of 100kΩ. The load capacitor is used to reduce the ripple by the last equation. To estimate the expression of the output voltage for the designed configuration, there is considered also the voltage drop in the transistors due to their on-resistance considered by B. Razavi [2]. There are 6 TFT in the main path between VDD and Vout, so the overall expression is: Vout =4VDD −3[Io 2fclkCb −Io 2fclk(Cb+Cload)]−6[Vth +1 1 2µnCG CH W L 1 fCLK +1 VDD−Vth ](4.3) This expression explains the usage of 4 large TFT in parallel at each transistor designed in the main path. As larger the transistor is, lower is the voltage drop across it. The expression also suggests better results if there are used DC/DC converters in parallel, due to the lower equivalent resistance of the block. The layout of the single DC/DC converter is presented in figure 4.4. Figure 4.4: Designed layout of the single DC/DC converter The red colour represent the gate material, which last reports of fabrication refer the usage of Indium Tin Oxide (ITO). The green colour represent the source/drain material, which Ti/Au 48 Proposed Configuration is commonly used. The blue colour represent the semi-conductor of the TFT (a-IGZO). The squares pads and rectangular vias use small squared metal inside, which is represented in white. To calculate the area of the capacitors, it was used a value of relative dielectric permittivity of 10.5 and a dielectric thickness of 275nm. For the designed values of capacitance, the area obtained is presented in table 4.3. Capacitance values Area (µm2) Capacitor associated 500pF 1.479 C9 and C10 400pf 1.183 C6 and C7 200pF 0.5916 C3 and C4 100pF 0.2958 C1, C2, C5 and C8 Table 4.3: Area of each capacitor designed To get a lower parasitic resistance associated, wider connections were designed and with as many as possible source-drain material (Ti/Au), which has better parasitic parameters in comparison to gate material (ITO). There was also the concern to avoid the usage of a large number of vias, which can increase the parasitic capacitances. About the behaviour of the circuit, a tradeoff exists between the area used and the parasitic parameters associated. However, a small-sized and efficient circuit can be obtained if the overlap between the 2 materials is avoided and the distances of the connections are not so large. The load capacitor and resistor were not designed in the layout due to external testing with PCB. The designed layout of the single DC/DC converter has 5793.55µmof length and 3058.55µmof width. 4.1.2 Simulation Using the verilog-A TFT model for simulation, the topology presented has an output voltage of 16.37 V with 10 V of VDD and clock voltage, and 162uA of load current. The frequency used is 1 MHz. The plot of the increasing voltage during the time is presented in figure 4.5. Comparing with the simulation of the same topology with NMOS, which has 23.17V and 203µAat the output, the simulation with TFT’s have lower output voltage due to the higher onresistance of the transistors. Using the TFT model of simulation, the bootstrapping stage on the single DC/DC converter represents an increment of only 0.04V, but the circuit is faster to achieve the final voltage level. This fact is very important for a fast start of the amplifier, which expects a high supply voltage. The comparison of the output voltage response with and without the bootstrapping stage is presented in figure 4.6. The additional stage designed at the output represents an increment of 2.9V for the simulation with the NMOS. However, with the TFT’s simulation, that only represents an increasing of 0.6V. Despite the low increasing, the second stage was used due to a necessary high voltage in the 4.1 DC/DC converter 49 Figure 4.5: Output voltage of the single DC/DC converter during the time Figure 4.6: Comparison of output voltage during the time with and without bootstrapping stage input of the regulator, and there are better results when this stage is used with more converters in parallel. In fact, to have a higher output voltage, it was used the same topology repeated 10 times in parallel, which will be explained later. The results of the simulation with the TFT model for the proposed single DC/DC converter with different values of load resistance are presented in table 4.4. Load resistance 60kΩ80kΩ100kΩ120kΩ140kΩ Output voltage 13.43V15.1V16.37V17.39V18.24V Load current 223.2µA188µA165.5µA145µA130µ Table 4.4: Output voltage and current for different values of load resistance for the proposed DC/DC converter 50 Proposed Configuration Analysing the table, as the load resistance is, the higher is the load current and voltage. The load current has a huge impact on DC/DC converter output voltage. Another important parameter to refer is the dimensions of the transistors. As explained before, four TFTs of 320µmin parallel were designed to reduce the on-resistance, with exception of the bootstrapping stage. The voltage level simulated without the designed transistors in parallel, so just one transistor of 320µmin each position, is 8.42V and the correspondent load current is 84.7µA, values much lower than with the final transistors. The dimensions of the capacitors change the voltage level and ripple at the output of the DC/DC converter. For the simulation of such changes, the DC/DC converter was tested only with 100pF capacitors. The output voltage is 16.25V, lower than before, and the ripple is higher, around 5mV, comparing with the 860µVof the final proposal. The circuit proposed use 10 DC/DC converters in parallel to increase the voltage level and the load current. The increasing voltage during the time is presented in figure 4.7. Figure 4.7: Output voltage of 10 DC/DC converter in parallel during the time Output voltage is 27.8V and the current is 277µAwith the same load devices. By comparison, ten converters without the last boosting stage have an output voltage of 20.05V, which is not enough to feed the regulator with a 24V expected. Notice that, although the difference of output voltage for one converter is not so large, for ten converters in parallel it is larger than 4 V. This fact is explained by the reduction of the equivalent resistance of the converter block. The resistance of each DC/DC converter is higher than the overall equivalent resistance, so the additional stage does not represent an increase of this parameter in all the circuit as much as with only one converter. 4.2 Amplifier 4.2.1 Design The regulation is achieved with a high-gain amplifier using a differential pair with a positive feedback at the load, to increase the voltage gain. The amplifier was designed to receive a supply 4.2 Amplifier 51 voltage VDD of 24V from the output of DC/DC converters. The final proposal for the amplifier is presented in figure 4.8. + − + − Vdd Vout Vin+ VinRc1 Cc1 Cc2 Rc2 Vbias1 Vbias2 TFT1 TFT2 TFT3 TFT4 TFT5 TFT6 TFT7 TFT8 TFT9 TFT10 TFT11 TFT12 TFT13 TFT14 TFT15 TFT16 TFT17 TFT18 TFT19 TFT20 TFT21 TFT22 TFT23 TFT24 TFT25 TFT26 TFT27 Figure 4.8: Proposal of regulator The differential pair is the stage that compares the two input voltages for the regulation of the output. Additionally, two source followers were added to decrease the output resistance, and two common-source stages to increase the gain. The positive feedback connected to the differential pair is used to increase the gain by increasing the load resistance. Due to the difficulty that exists with the lack of p-type transistor in increasing the load resistance to achieve a high gain, positive feedback can be used as with TFT1 to TFT6 presented in figure, which equivalent load resistance is found to be: RL=ro2|| 1 gm2(1−Af)(4.4) where Afis the feedback gain. Therefore, the voltage gain of the common-source stage is: Av=−gm1[1 gm2(1−Af)||ro2||ro1](4.5) With a feedback gain close to 1, the voltage gain is approximately −gm1(ro1||ro2). With a feedback gain higher than 1, instability is created in the amplifier, which is undesirable. The feedback gain in the proposal presented is calculated by: Af=gm2(1 gm6 ||ro6||ro2)(4.6) Theoretically, the gain Afis 0.8572. A higher feedback gain could increase the overall gain, but if in theory the feedback had a gain very close to 1, due to errors in fabrication, the maximum value could be exceeded, just with some difference on TFT’s width. 52 Proposed Configuration The topology proposed of positive feedback uses a cascode stage instead of common-source, due to a high VDD expected. Three TFT’s in this stage decreases the VDS and the VGS applied in each transistor, which enables a efficient operation of transparent TFT’s. Notice that the values of VGS should be between 5 and 7 Volts, to prevent lower or higher levels of voltage applied to the TFT than those that are expected by analysis of the background. The dimensions of the transistors for feedback topology are presented in the table 4.5. Width Length TFT 1 and 2 75µm20µm TFT 3 and 4 75µm20µm TFT 5 and 6 80µm20µm TFT 7 160µm20µm Table 4.5: Dimensions of TFT for the feedback stage In the differential pair, a diode-connected transistor is used, that in addition to the decrease of voltage applied in the transistor, which was explained before, it increases the voltage gain due to a higher load resistance. Therefore, the voltage gain of the differential pair with the feedback stage is: Av=−gm8[( 1 gm12 ||ro12)+( 1 gm10(1−Af)||ro10)||ro8](4.7) The dimensions of the transistors take into account two factors, the need to have all transistors in saturation and the voltage gain, by increasing the load resistance using narrow dimensions on TFT’s 10, 11, 12 and 13. The dimensions used are presented in table 4.6. Width Length TFT 8 and 9 80µm20µm TFT 10 and 11 80µm20µm TFT 12 and 13 160µm20µm TFT 14 160µm20µm Table 4.6: Dimensions of TFT for the differential pair The high impedance and the high output voltage level of the differential pair is decreased by using a source-follower stage. Despite its unitary gain, it is very useful for the addition of the two out-of-phase input signal voltages. Notice that the TFT16, to be in saturation, needs a low gate voltage due to the low voltage applied to the drain. It is also important to refer that the TFT15 receives a bias voltage at the gate instead of being connect directly to the gate of TFT16, which could create a negative gain at this stage. If the gate and drain of TFT15 were connected, the source resistance would be 1/gm15, resulting in a very low source resistance applied to the sourcefollower. That would decrease the value of gm17Rs, which should be much higher than one to do not result in a negative gain. 4.2 Amplifier 53 The voltage gain of the source-follower stages and the common source applied to TFT16 is: AvSF17 =gm17[[( 1 gm17 ||ro17)+( 1 gm15 ||ro15)]||ro15] 1+gm17[[( 1 gm17 ||ro17)+( 1 gm15 ||ro15)]||ro15](4.8) AvSF18 =gm18[[( 1 gm18 ||ro18)+( 1 gm20 ||ro20)]||ro16] 1+gm18[[( 1 gm18 ||ro18)+( 1 gm20 ||ro20)]||ro16](4.9) AvCS16 =gm16[[( 1 gm18 ||ro18)+( 1 gm20 ||ro20)]||ro16](4.10) The dimensions of the TFT are presented in the table 4.7. Width Length TFT 15 and 16 80µm20µm TFT 17 and 18 80µm20µm TFT 19 and 20 80µm20µm Table 4.7: Dimensions of TFT for the source-follower stages In order to increase the voltage gain of the amplifier, two common-source stages were designed at the output. It was used diode-connected TFT’s for the same reasons explained with the differential pair, increasing the gain and decreasing VGS. The transistors that determine the load resistance should be as narrow as possible, to get lower values of gm. The load transistors use the same width, so the voltage gain of each stage can be calculated as: AvCSt ft21 =−gm21[3 gm22 ](4.11) AvCSt ft25 =−gm25[2 gm26 ](4.12) The dimensions of the transistors are presented in table 4.8. Width Length TFT 21 and 25 80µm20µm TFT 22, 23 and 24 70µm20µm TFT 26 and 27 50µm20µm Table 4.8: Dimensions of TFT for the common-source stages The voltage gain of the amplifier can be estimated by analysis of each stage and then for all. Notice that the voltage gain of the source-follower stages is around 1. Therefore, the voltage gain 54 Proposed Configuration for the amplifier is estimated as: Avop−amp =−gm9[( 1 gm13 ||ro13)+( 1 gm11(1−Af)||ro11)||ro9][−gm21(3 gm22 )][−gm25(2 gm26 )] (4.13) In order to achieve a high phase-margin, frequency compensation is needed. To determine how to use the compensation technique, it is estimated the node where the dominant pole is located. Due to the positive feedback stage, which creates a very high load resistance, the impedance at the output node of the differential pair is very high, creating the dominant pole. A capacitor connected to this node move it into the lower frequencies, increasing the phase margin. For an efficient compensation, the capacitor should be high to ensure that the pole is at lower frequencies. With a multi-stage amplifier, it is possible to use the properties of the Miller effect to have a high capacitance associated to the node without using a large capacitor, which would increase the necessary area of the circuit. In addition to the effect of a dominant pole in the phase margin, there is also the effect of a zero. The zero is created by the signal path between the compensation capacitor nodes. This zero degrades the phase margin because is located at the right side of the S plane, creating a decrease of phase at lower frequencies. It also slows down the decreasing curve of the magnitude, moving the point of zero magnitude into higher frequencies. These two facts are responsible to the degradation of the phase margin and the stability. The technique used to eliminate the zero effect is by the additional resistor Rcadded. The zero introduced by the compensation is: wz=1 Cc(1 gm18 −Rc)(4.14) With a Rc≥1/gm18,wz≤0, the resistance should be higher enough so to move the zero to the left half plane and cancel the first non-dominant pole, if possible. By an iterative mode, the resistance and capacitance value were obtained when the phase margin ensured a good stability of the amplifier. For the layout design, the same care was considered as it was for the DC/DC converter. However, this circuit is pad-limited, the large number of pads determines the area that can be used. The layout of the proposed regulator amplifier is presented in figure 4.9. The layout designed does not have the compensation resistors and capacitors, due to a following testing of those values using the PCB. The dimensions of the designed layout are 2383.8µm on the vertical axis of the figure presented and 2450µmat the horizontal axis. 4.2.2 Simulation For the simulation of the amplifier, it was considered parasitic capacitances with values of CGD = 1pF and CGS =5pF. The voltage gain of the amplifier is 36.7dB and the phase margin is 83.79 degrees. The plot of voltage gain and phase is presented in figures 4.10 and 4.11. 4.2 Amplifier 55 Figure 4.9: Designed layout of the proposed regulator amplifier Figure 4.10: Voltage gain of the amplifier for a logarithmic frequency scale Figure 4.11: Phase response of the amplifier for a logarithmic frequency scale 62 Conclusions and Future Work regulation that can achieve better results and better performance due to the direct regulation of the duty-cycle for the DC/DC converter. The circuit presented in this report only regulates the voltage level according to the output of the DC/DC converters with some error. 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