Analog Circuit Design With Transparent Electrics

FACULDADE DE ENGENHARIA DA UNIVERSIDADE DO PORTO Analog Circuit Design with Transparent Electronics Bruno Filipe Guedes da Silva Mestrado Integrado em Engenharia Eletrotécnica e de Computadores Supervisor: Vitor Grade Tavares (PhD) Second Supervisor: Pedro Miguel Cândido Barquinha (PhD) Second Supervisor: Pydi Ganga Bahubalindruni July 26, 2013 c Bruno Filipe Guedes da Silva, 2013 ii Resumo O domínio da eletrónica transparente tem tido um grande desenvolvimento na última década, com o aparecimento e desenvolvimento de transístores transparentes baseados em tecnologias de filme fino. Várias tecnologias estão atualmente sob estudo e todos os anos são publicados diversos artigos sobre novas descobertas realizadas na área. A investigação deste tema tem se concentrado tanto ao nível da descoberta de novos materiais e melhoria dos processos de fabrico, como do aprofundamento da compreensão dos mecanismos físicos que ditam as características funcionamento destes dispositivos. Atualmente a principal aplicação deste tipo de transístor é a construção de FPDs (Flat Panel Display). No entanto a possibilidade de realizar circuitos analógicos e digitais totalmente transparentes tem também vindo a ser estudada. Uma das tecnologias de TTFT (Transparent Thin-Film Transistor) mais promissoras é a tecnologia a-GIZO. Esta tecnologia apresenta interessantes características elétricas e é fabricada a baixas temperaturas, o que representa uma vantagem significativa relativamente aos processos de fabrico de circuitos integrados convencionais. Esta última característica permite a integração destes TTFTs em substratos transparentes e flexíveis originando uma redução dos custos de fabrico. Esta dissertação nasce da necessidade do projeto de circuitos eletrónicos em a-GIZO TFT com vista a permitir o desenvolvimento futuro de sistemas on-chip, integrando num mesmo substrato sensores e sistemas de condicionamento e processamento de sinal, todos implementados na mesma tecnologia. Para possibilitar este tipo de aplicações é necessário o desenvolvimento de circuitos de processamento de sinal como amplificadores, filtros e conversores. Com esta necessidade em mente, a presente dissertação tem como objetivo o desenvolvimento e projeto para fabricação de um dos principais circuitos necessários para a realização de processamento de sinal, o amplificador operacional. Como resultado deste trabalho apresentam-se dois novos amplificadores operacionais implementados em TFTs a-GIZO. Uma destas topologias é um amplificador operacional comutado, uma técnica que é utilizada em circuitos de baixa potência no domínio de capacidades comutadas. No entanto esta técnica é aqui utilizada para reduzir o efeito da variação, ao longo do tempo, da tensão de limiar nos TFTs a-GIZO quando estes estão continuamente em condução. Incluída nestes amplificadores operacionais, apresenta-se uma nova topologia de andar diferencial de alto ganho com apenas transístores de enriquecimento do tipo n. Este andar permite obter o maior ganho de tensão entre todos os andares que usam realimentação positiva para aumentar a resistência de carga e que conseguem amplificar sinais dc. No entanto, o aumento do ganho é conseguido à custa de uma redução da gama dinâmica e largura de banda. Finalmente, um circuito Sample-and-Hold é implementado usando o amplificador operacional comutado proposto. Para a realização de simulações dos circuitos projetados, foi utilizado um modelo de tecnologia previamente construído com base num sistema de rede neuronal. Sendo que o processo de projeto de circuitos neste tipo de tecnologia é análogo ao utilizado em tecnologias convencionais. Este trabalho é realizado em colaboração com o grupo CENIMAT da UNL, que fabricará o amplificador operacional e circuitos auxiliares produzidos durante a realização da dissertação. iii iv Abstract The area of transparent electronics has had a great development in the last decade, with the emergence and development of transparent transistors based on thin-film technologies - TTFTs. Several technologies are presently under study and every year numerous articles are published regarding new advances made in this area. Directions have been focusing both in the discovery of new materials and improvement of manufacturing processes, and in deepening the understanding of the physical mechanisms that dictate the electrical characteristics of these devices. Currently TTFTs find its main application in the construction of FPDs (Flat Panel Display). However, the possibility of realizing analog and digital circuits, with fully transparent electronics, has also been studied. One of the most promising TTFT technologies is a-GIZO (amorphous Gallium-Indium-ZincOxide). This technology presents interesting electrical characteristics and can be manufactured at low temperatures. It represents a significant advantage over the manufacturing processes of conventional integrated circuits. This feature allows the integration of the TTFTs on transparent and flexible substrates and also enables a reduction in manufacturing costs. This dissertation stems from the need to design electronic circuits that enable the development of future systems-on-chip, integrating on a single substrate sensors and signal processing systems. To make such application possible with a-GIZO, the development of analog processing and conditioning circuits, such as amplifiers, filters and converters, is required. Having this need in background, the present dissertation fosters its main goal in the development, design and fabrication of one of the most important circuits needed to perform signal processing, the operational amplifier. Two novel operational amplifier topologies result from this work. One is a switched operational amplifier, a technique that is used in low-power design for switched-capacitor circuits. Here however, this technique is introduced to reduce the shift in the threshold voltage of a-GIZO TFTs under stress. Included in the operational amplifier, a novel topology for a differential high-gain stage, with only n-type enhancement transistors, is also proposed. This stage gives the highest voltage gain, amongst all of the stages that use positive feedback to increase the load resistance, while still being able to amplify dc signals. Nevertheless, the higher gain is achieved at the cost of a reduction in dynamic range and bandwidth. Finally, a Sample-and-Hold circuit is implemented using the proposed switched operational amplifier. For electric simulation, a previously designed behavioural model was used. The rest of the design process follows a similar track to that of conventional technologies, namely CMOS. This work is conducted in collaboration with the CENIMAT group at UNL, which will manufacture the operational amplifier and auxiliary circuits produced during the course of the Master Thesis. v vi Acknowledgements I begin by thanking my parents and my brother who always supported me in all of my decisions and gave me the strength to go after my objectives. My parents also sacrificed a lot so that I could have a good education and without them I wouldn’t be where I am today and for this I am very grateful. I also want to extend my thanks to my best friends Henrique Martins and Romano Torres with whom I have shared this five year journey at FEUP. We have been trough a lot together and helped each other surpass many obstacles along the way. Without them all those hours studying for exams and spent in front of a computer screen developing the projects that were done throughout the course would have been much more difficult to pass. Before concluding I would also link to thank Ganga Bahubalindruni for her support and help during these last few months in the development of the master thesis. Even though she was busy she would always find time to help solve some of the problems that occurred during the development of my work and she shared all of her finds and knowledge on thin-film transistors with me. Without her work the work developed would not be possible because it was she who paved the way in the design, simulation and testing of circuits with a-GIZO TFT in FEUP. In the same regard I want to thank Nuno Cardoso for all the help he gave on how to work with the tools he developed for Layout design in a-GIZO TFT technology. I would also like to thank Prof. Dr. Pedro Barquinha of CENIMAT for tall of the help with the layout design and fabrication of masks for the fabrication process and with the fabrication of the produced circuits themselves. Finally, I thank Prof. Dr. Vítor Grade Tavares for all the advice and ideas he gave me during my work and for all of the support he gave during the elaboration of documents. His advice played a great part in the work that was ultimately developed and helped solve numerous problems found along the way. And maybe the most amazing thing is that sometimes 5 minutes talking with him could help solve a multitude of problems. Bruno Silva vii xiv CONTENTS List of Figures 2.1 Bottom-gate a-GIZO TFT Device Structures . . . . . . . . . . . . . . . . . . . . 7 2.2 Top-gate a-GIZO TFT Device Structures . . . . . . . . . . . . . . . . . . . . . . 7 2.3 TTFTinCut-offmode ............................... 9 2.4 IDS of an a-GIZO TFT biased with constant VDS .................. 10 2.5 TTFTinLinearmode................................ 10 2.6 TTFTinSaturationmode.............................. 11 2.7 Generic Common-source amplifier with complementary active load . . . . . . . 14 2.8 Generic Common-source amplifier with diode connected enhancement load . . . 15 2.9 Time dependence of ∆Vth for gate bias stresses, reprinted from [1] . . . . . . . . 16 2.10 Small-Signal Model of an ideal a-GIZO TFT . . . . . . . . . . . . . . . . . . . 19 2.11 Small-Signal Model of a non-ideal TTFT . . . . . . . . . . . . . . . . . . . . . 19 2.12 Common-source stage with positive feedback in the active load . . . . . . . . . . 20 2.13 Active load positive feedback loop implemented with a buffer . . . . . . . . . . 21 2.14 Active load positive feedback loop implemented with capacitive bootstrapping . . 21 2.15 Miller Effect applied to a floating impedance . . . . . . . . . . . . . . . . . . . 22 2.16 Common-source stage with parasitic capacitances . . . . . . . . . . . . . . . . . 23 2.172-stageMillerOpamp................................ 23 2.18 2-stage Miller Opamp with a source follower in series with the compensation capacitor........................................ 25 2.19 2-stage Miller Opamp with transistor in triode in series with the compensation capacitor....................................... 25 2.20 Symbol representation of a single-ended opamp . . . . . . . . . . . . . . . . . . 26 2.21 Symbol representation of a fully-differential opamp . . . . . . . . . . . . . . . . 26 2.22 Generic representation of a CMFB topology . . . . . . . . . . . . . . . . . . . . 27 2.23 Common configurations used to sense the CM level at the output of a fully-differential amplifier....................................... 28 2.24 Operation principle of a switched-capacitor CMFB network . . . . . . . . . . . . 29 3.1 Block diagram of the internally compensated NMOS opamp reported by Tsividis and Gray in 1976, reprinted from [2] . . . . . . . . . . . . . . . . . . . . . . . . 32 3.2 Complete schematic of the internally compensated NMOS opamp reported by Tsividis and Gray in 1976, reprinted from [2] . . . . . . . . . . . . . . . . . . . . . 33 3.3 Block diagram of the NMOS opamp reported by Young in 1979, reprinted from [3] 34 3.4 Complete schematic of the NMOS opamp reported by Young in 1979, reprinted from[3]....................................... 34 3.5 Complete schematic of the NMOS opamp reported by Calzolari et al. in 1979, reprintedfrom[4].................................. 35 xv xvi LIST OF FIGURES 3.6 Schematic of the novel high-gain common-source stage with only n-type enhancement transistors proposed in 2013 by Bahubalindruni et al., reprinted from [5] . . 36 3.7 Complete schematic of the a-Si:H NTFT Operational Amplifier proposed by Tarn et al. in 2010, reprinted from [6] . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.8 Complete schematic of the single stage opamp in p-type pentacene-based dualgate organic thin-film transistors using bootstrapped gain-enhancement, proposed by Marien et al. in 2011, reprinted from [7] . . . . . . . . . . . . . . . . . . . . 39 3.9 Complete schematic of the Switched opamp presented by Crols and Steyaert in 1994,reprintedfrom[8] .............................. 40 3.10 Schematic of the low-Q biquad filter with switched opamp presented by Crols and Steyaert in 1994, reprinted from [8] . . . . . . . . . . . . . . . . . . . . . . . . 40 3.11 Complete schematic of the switched opamp proposed in 1997 by Baschirotto and Castello, reprinted from [9] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.12 Complete schematic of the switched opamp proposed in 1998 by Waltari and Halonen,reprintedfrom[10]............................... 42 3.13 Schematic of the SCCMFB network proposed in 1998 by Waltari and Halonen for their switched opamp, reprinted from [10] . . . . . . . . . . . . . . . . . . . . . 43 3.14 Schematic of the switched opamp proposed in 2008 by Qin et al., reprinted from [11] 43 3.15 Schematic of the CMFB loop porposed by Qin et al. for their switched opamp, reprintedfrom[11] ................................. 44 3.16 Schematic of the sample and hold implemented by Qin et al. using their switched opamp, reprinted from [11] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.1 High-gain single-stage differential amplifiers using ac bootstrapping . . . . . . . 53 4.2 High-gain single-stage differential amplifiers using a differential amplifier to implement positive feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.3 Single-stage version of the novel topology for high-gain with only n-type enhancementtransistors................................... 54 4.4 Simplified models of the proposed topology . . . . . . . . . . . . . . . . . . . . 55 4.5 Sweep of both Af and Af1 in the novel topology, NMOS implementation . . . . . 56 4.6 Sweep of Af in the novel topology keeping Af1=0.95, NMOS implementation . . 56 4.7 Sweep of Af1 in the novel topology keeping Af=0.95, NMOS implementation . . 57 4.8 Sweep of both Af and Af1 in the novel topology, a-GIZO TFT implementation . 58 4.9 Sweep of Af in the novel topology keeping Af1=0.95, a-GIZO TFT implementation 58 4.10 Sweep of Af1 in the novel topology keeping Af=0.95, a-GIZO TFT implementation 58 4.11 Cross-coupled load with p-type transistors . . . . . . . . . . . . . . . . . . . . . 60 4.12 Voltage gain of the novel topology when Af and Af1 are swept from -1 to -0.9, NMOSimplementation............................... 62 4.13 Simulation results of high-gain single-stage differential amplifiers with only ntype enhancement transistors, NMOS implementations . . . . . . . . . . . . . . 63 4.14 Simulation results of high-gain single-stage differential amplifiers with only ntype enhancement transistors, a-GIZO TFT implementations . . . . . . . . . . . 63 4.15 Input stage of the proposed opamp . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.16 Schematic of the second stage of the opamp . . . . . . . . . . . . . . . . . . . . 66 4.17 Final stages of the proposed opamp . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.18 CMFB circuit of the proposed opamp . . . . . . . . . . . . . . . . . . . . . . . 70 4.19 Schematic of the proposed opamp without frequency compensation . . . . . . . 73 4.20 Schematic for the calculation of the input impedance of a source-follower stage . 76 4.21 Complete schematic of the proposed opamp . . . . . . . . . . . . . . . . . . . . 78 LIST OF FIGURES xvii 4.22 Frequency response of the a-GIZO TFT opamp . . . . . . . . . . . . . . . . . . 80 4.23 Fully-differential implementation of a non-inverting switched capacitor charge amplifier....................................... 82 4.24 Frequency response of the CMFB network . . . . . . . . . . . . . . . . . . . . . 82 4.25 Transient response of the CMFB network and of the output of the opamp when no signalisapplied................................... 84 4.26 Transient response of the fully-differential switched capacitor amplifier when differential sine waves with 1V of amplitude at 100Hz are applied to the inputs . . . 85 4.27 Transient response of the fully-differential switched capacitor amplifier when differential voltage steps with 1V of amplitude at 100Hz are applied to the inputs . . 85 4.28 Example of a chip for fabrication . . . . . . . . . . . . . . . . . . . . . . . . . . 88 4.29 Layout of the proposed opamp . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 4.30 Layout of the Common-mode feedback network . . . . . . . . . . . . . . . . . . 89 4.31 Multifinger layout for an a-GIZO TFT with W/L=320/20µm........... 90 4.32 Interdigitated layout of two 160/20µma-GIZOTFTs ............... 91 4.33 √IDS for various values of VGS for 320/20µma-GIZO TFTs with different layout structures, results obtained from physical circuits . . . . . . . . . . . . . . . . . 91 5.1 Generic topology to implement a pulsed biasing scheme . . . . . . . . . . . . . 95 5.2 Switch-off mechanism for the first common-source stage . . . . . . . . . . . . . 95 5.3 Schematic of the output stage of the switched opamp . . . . . . . . . . . . . . . 96 5.4 CMFB circuit of the proposed switched opamp . . . . . . . . . . . . . . . . . . 97 5.5 Complete schematic of the novel switched opamp with a-GIZO TFTs . . . . . . 100 5.6 Schematic of the sample and hold circuit implemented with the proposed switched opamp........................................ 102 5.7 Frequency response of the switched opamp in a-GIZO TFT . . . . . . . . . . . . 104 5.8 Output voltage of the proposed switched opamp with no signal applied to the input at a switching frequency of 200Hz . . . . . . . . . . . . . . . . . . . . . . . . . 104 5.9 Output signal of the CMFB circuit of the switched opamp . . . . . . . . . . . . . 105 5.10 Positive phase differential input and output signals of the S/H for a 20Hz sinusoidal signal with an amplitude of 1V, S/H operated at Fs=200Hz . . . . . . . . . . . . 106 5.11 Differential signals at input and output of S/H circuit. S/H operated at Fs=200Hz 107 5.12 Power sepctral density of the differential output signal of the S/H circuit. Fundamentalfrequency20Hz................................ 107 5.13 Layout of the complete S/H topology . . . . . . . . . . . . . . . . . . . . . . . . 108 5.14 Layout of the Common-mode feedback network of the switched opamp (SOCMFB)109 A.1 Small-signal equivalent of the load for the novel high-gain topology with n-type enhancementtransistors............................... 116 B.1 Common-SourceStage ............................... 125 B.2 Common-Source Stage with Source Degeneration . . . . . . . . . . . . . . . . . 126 B.3 SourceFollowerStage ............................... 127 B.4 Common-GateStage ................................ 128 B.5 CascodeStage.................................... 129 B.6 Differential Pair with resistive load . . . . . . . . . . . . . . . . . . . . . . . . . 130 B.7 Differential Pair with common-mode input . . . . . . . . . . . . . . . . . . . . . 131 B.8 Equivalent Circuit of a differential pair with common-mode input . . . . . . . . 131 xviii LIST OF FIGURES C.1 Layout of an a-GIZO TFT with W/L=40/20µm.................. 134 C.2 Via that interconnects GATE and SOURCE/DRAIN layers . . . . . . . . . . . . 134 C.3 Externalpad..................................... 134 C.4 LayoutofaCapacitor................................ 135 C.5 Complete Layout of the Switched Opamp . . . . . . . . . . . . . . . . . . . . . 136 C.6 Layout of the first stage without the positive feedback network . . . . . . . . . . 136 C.7 Positive feedback network, drive transistors W/L=90/20µm, load transistors W/L=160/20µm137 C.8 Positive feedback network, drive transistors W/L=120/20µm, load transistors W/L=160/20µm137 C.9 Positive feedback network, drive transistors W/L=140/20µm, load transistors W/L=160/20µm138 C.10 Complete layout of the novel high-gain stage with only n-type enhancement transistors ........................................ 138 C.11 Layout of the second Stage of the proposed opamps . . . . . . . . . . . . . . . . 139 C.12 Layout of the third stage of the regular opamp . . . . . . . . . . . . . . . . . . . 139 C.13 Layout of the output stage of the regular opamp . . . . . . . . . . . . . . . . . . 140 C.14 Layout of the switched version the third stage of the switched opamp . . . . . . . 140 C.15 Layout of the switched version of the output stage of the switched opamp . . . . 141 C.16 Layout of the first stage without the positive feedback network, transistors with multifingerstructure................................. 141 C.17 Differential amplifier with positive feedback, positive feedback amplifier kept external ........................................ 142 C.18 Positive feedback network, drive transistors W/L=120/20µm, load transistors W/L=160/20µm, all transistors with multifinger structure . . . . . . . . . . . . . . . . . . . . . . 142 C.19 Positive feedback network, drive transistors W/L=140/20µm, load transistors W/L=160/20µm, all transistors with multifinger structure . . . . . . . . . . . . . . . . . . . . . . 143 C.20 Layout of all the stages that are connected to the output of the input stage . . . . 143 C.21 Layout of the first stage without the positive feedback network, transistors with multifingerstructure................................. 144 C.22 Layout of the differential amplifier with single capacitive bootstrap load . . . . . 145 C.23 Layout of the differential amplifier with cascade capacitive bootstrap load . . . . 146 D.1 Setting up a pss analysis in Cadence Virtuoso . . . . . . . . . . . . . . . . . . . 148 D.2 Selecting the maximum frequency for the pss analysis . . . . . . . . . . . . . . . 148 D.3 Setting up a pstb analysis in Cadence Virtuoso . . . . . . . . . . . . . . . . . . . 149 D.4 Verifying the results of a pstb simulation . . . . . . . . . . . . . . . . . . . . . . 149 D.5 Setting up the correct options to execute simulations in ADE L of circuits using the verilog-A model for a-GIZO TFT . . . . . . . . . . . . . . . . . . . . . . . 150 E.1 I-V characteristics of a a-GIZO TFT with W/L=320/20µm. Results obtained from theneuralnetworkmodel.............................. 151 E.2 Decrease of IDS in relation to the increase of VDS in saturation region . . . . . . . 152 E.3 Comparison between the measured I-V characteristics of a 320/20µma-GIZO TFT (blue) and the characteristics obtained in simulation through fitting with the level 1 equations for MOSFET (green) . . . . . . . . . . . . . . . . . . . . . . . 152 E.4 Estimation of the Ron of an a-GIZO TFT with W/L=320/20µm.......... 153 E.5 Estimation of the Vth of an a-GIZO TFT with W/L=320/20µm.......... 153 F.1 Bendable a-GIZO TFT transimpedance amplifier proposed by Zysset et al. in 2011[12] ...................................... 157 List of Tables 4.1 Transconductance values of the transistors used in the simulations . . . . . . . . 60 4.2 Values of the factor aand of Aol measured in simulation . . . . . . . . . . . . . . 60 4.3 Values of the factor aand of Aol calculated with the formulas in 4.10 . . . . . . . 60 4.4 Comparative analysis of the performance high-gain differential stages with n-type enhancement transistors in NMOS . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.5 Number of components necessary to implement each of the high-gain stages only with n-type enhancement transistors analysed . . . . . . . . . . . . . . . . . . . 64 4.6 Aspect ratios of the transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 4.7 Bias Voltages of the opamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 4.8 Characteristics of the opamp’s open loop response . . . . . . . . . . . . . . . . . 79 4.9 Small signal gain of each stage of the opamp . . . . . . . . . . . . . . . . . . . . 80 4.10 Current per stage in the proposed opamp . . . . . . . . . . . . . . . . . . . . . . 81 4.11 Characteristics of the opamp that are not determined directly from the analysis of the open-loop frequency response . . . . . . . . . . . . . . . . . . . . . . . . . 81 4.12 Characteristics of the frequency response of the Common-mode feedback loop . 83 4.13 Characteristics of the transient response of the CMFB circuit . . . . . . . . . . . 84 4.14 Step response results for the unity gain fully-differential switched capacitor amplifier 85 4.15 a-GIZO TFT Layer color scheme . . . . . . . . . . . . . . . . . . . . . . . . . . 87 4.16Layoutareas..................................... 88 5.1 High voltage level and phase of each clock in the novel switched opamp . . . . . 99 5.2 Bias Voltages of the switched opamp . . . . . . . . . . . . . . . . . . . . . . . . 99 5.3 High voltage level and phase of each clock exclusive to the S/H . . . . . . . . . . 102 5.4 Characteristics of the switched opamp . . . . . . . . . . . . . . . . . . . . . . . 105 5.5 Layoutareas..................................... 109 A.1 Aspect ratios and biasing conditions used in the simulations of the novel topology 119 A.2 Aspect ratios for the differential amplifier with single ac bootstrapped load in NMOS(figure4.1a)................................. 119 A.3 Bias voltages for the differential amplifier with single ac bootstrapped load in NMOS(figure4.1a)................................. 119 A.4 Aspect ratios for the differential amplifier with cascade ac bootstrapped load in NMOS(figure4.1b)................................. 120 A.5 Bias voltages for the differential amplifier with cascade ac bootstrapped load in NMOS(figure4.1b)................................. 120 A.6 Aspect ratios for the differential amplifier with single differential feedback in NMOS(figure4.2a)................................. 120 xix xx LIST OF TABLES A.7 Bias voltages for the differential amplifier with single differential feedback in NMOS(figure4.2a)................................. 120 A.8 Aspect ratios for the differential amplifier with cascade differential feedback in NMOS(figure4.2b)................................. 120 A.9 Bias voltages for the differential amplifier with cascade differential feedback in NMOS(figure4.2b)................................. 121 A.10 Aspect ratios for the differential amplifier with single ac bootstrapped load in aGIZOTFT(figure4.1a)............................... 121 A.11 Bias voltages for the differential amplifier with single ac bootstrapped load in aGIZOTFT(figure4.1a)............................... 121 A.12 Aspect ratios for the differential amplifier with cascade ac bootstrapped load in a-GIZOTFT(figure4.1b).............................. 121 A.13 Bias voltages for the differential amplifier with cascade ac bootstrapped load in a-GIZOTFT(figure4.1b).............................. 121 A.14 Aspect ratios for the differential amplifier with single differential feedback in aGIZOTFT(figure4.2a)............................... 122 A.15 Bias voltages for the differential amplifier with single differential feedback in aGIZOTFT(figure4.2a)............................... 122 A.16 Aspect ratios for the differential amplifier with cascade differential feedback in a-GIZOTFT(figure4.2b).............................. 122 A.17 Bias voltages for the differential amplifier with cascade differential feedback in a-GIZOTFT(figure4.2b).............................. 122 Abbreviations, Acronyms and Symbols ADC Analog-to-digital converter a-GIZO Amorphous Gallium-Indium-Zinc-Oxide a-Si:H Hydrogenated Amorphous Silicon AOS Amorphous oxide semiconductor CAD Computer-aided design CM Common-mode CMFB Common-mode feedback CMOS Complementary metal-oxide-semiconductor CMRR Common-mode rejection ratio DAC Digital-to-Analog Converter FPD Flat-panel display GBW Gain–bandwidth product IC Integrated Circuit MOSFET Metal–oxide–semiconductor field-effect transistor NMOS N-type metal-oxide-semiconductor OTFT Organic Thin-film transistor Opamp Operational Amplifier PSRR Power supply rejection ratio RF Radio frequency RO Ring-oscillator SCCMFB Switched Capacitor Common-mode feedback SFDR Spurious-free dynamic range S/H Sample and Hold SPICE Simulation Program with Integrated Circuit Emphasis SRAM Static random-access memory TAOS Transparent amorphous oxide semiconductor TFT Thin-film transistor THD Total Harmonic Distortion TTFT Transparent thin-film transistor ZnO Zinc-Oxide dB decibel gds Drain to source transconductance gm transconductance Hz Hertz Vth threshold voltage roIntrinsic output resistance of a transistor µnMobility of charge carriers in the channel of an n-type transistor xxi Chapter 1 Introduction Transparent electronics is a rapidly growing field that has garnered a lot of interest from researchers around the world, especially in the last decade. This interest was mainly fuelled by the first reports on transparent thin-film transistors published in 2003 [13, 14, 15], all of which used a ZnO as the channel layer material. In the following year Nomura et al. reported the successful fabrication at room-temperature of transparent and flexible TFTs in polyethylene terephthalate substrates using an amorphous oxide semiconductor, a-GIZO, as the active layer material [16]. This active layer material is also optically transparent, allows low-temperature processing and presents higher carrier mobility than other amorphous semiconductors used in TFTs, namely a-Si:H which is widely used in the flat panel display industry. Various researches have been carried out in recent years concerning the physical characteristics and the limitations of a-GIZO TFTs. This is so because they are seen as viable candidates to substitute a-Si:H TFTs in the production of the next generation of flat panel display technologies, and in the fabrication of flexible displays. Due to these researches work, considerable advances have been made in the fabrication process of these devices, resulting in the compensation of some performance limitations presented by the technology, especially in terms of electrical characteristics and semiconductor stability. Still, this technology is not yet matured and as of the moment of the writing of this document, various improvement proposals are being conducted on this subject. This work aims to show that it is already possible to implement operational amplifiers with significant voltage gain in a-GIZO TFTs as well as in other technologies that only have available a single type of device. We propose two operational amplifiers that include a novel high-gain topology intended for technologies with only n-type enhancement devices. Both of the proposed topologies have the same signal path but have different schemes of countering the effect of the shift in the threshold voltage of a-GIZO TFTs under stress. In the continuous time version of the amplifier, the threshold voltage shift is mainly countered by means of common-mode feedback, while in the switched operational amplifier the transistors are periodically cut-off. An actual pulsed biasing scheme is then implemented to minimize transistor stress. Such technique has been previously demonstrated with digital circuits to decrease the threshold voltage shift and consequently increase the lifetime of circuits in a-GIZO TFTs [17]. 1 8Background 2.3.2 Materials used in a-GIZO TFT Source/Drain electrodes The source/drain electrode composition has a significant impact on device performance, consequent of its high-resistivity contact values. This problem affects the carriers mobility and therefore the device transconductance, hindering its application in amplifier circuits. The topic of contact resistance will be revisited and further explored later in 2.5.4. Other parameters of a-GIZO TFT performance that have shown alterations with different source/drain materials are the threshold voltage, VON and the ratio between on and off currents [24]. Among others ITO, Ti/Au and Mo are currently being used for source/drain electrodes. The devices using Au/Ti electrodes demonstrate better performance, however, lack of transparency is a major drawback associated with this material. On the other hand, ITO electrodes are transparent but TFTs with such electrodes present significantly reduced performances in comparison to those using Ti/Au [24]. 2.3.3 Other techniques used to improve performance of the a-GIZO TFT The studies on the fabrication process of this type of TFT have also led to the utilization of techniques that increase the devices performance without changing, directly, the materials that constitute the semiconductor layer and the source/drain electrodes. One of these techniques is annealing. This process can be done after the deposition of the semiconductor layer and before source/drain electrode deposition, or it can be done after the deposition of both. In either case, annealed devices show better performance in terms of channel mobility, sub-threshold voltage swing, on/off current ratio and they present decreased shifts in the threshold voltage due to biasing stress. Still, if the annealing process is done after the deposition of source/drain electrodes the performance of the device is further augmented [24]. Another technique that has been used to improve the performance of a-GIZO TFTs is passivation. This technique turns the surface of the device less reactive to the environment reducing the negative effects that occur in devices presenting a bottom-gate configuration when the semiconductor layer is in contact with the atmosphere. 2.4 a-GIZO TFT Operation Principle As previously introduced, some of the physical aspects of the device are still not fully understood. Still TFTs are field-effect transistors and the I-V characteristics indicate that the equations that describe the operation principle of a MOSFET provide a reasonable approximation to the characteristic of an a-GIZO TFT. However, this approximation is not very accurate due to the difference among semiconductor materials, mainly because of the amorphous nature of the a-GIZO semiconductor. More accurate models of operation for these devices have been proposed recently [25, 26]. 2.4.1 Ideal TTFT Operation With n-type TTFTs the biasing of the gate, by a positive voltage, attracts electrons, creating an accumulation layer at the surface of the semiconductor close to the gate dielectric. This accumulation layer provides a conductive channel from the source to the drain of the device. To explain how 2.4 a-GIZO TFT Operation Principle 9 the conduction of current happens in these devices, consider a TTFT with its source grounded and biased by a positive voltage at the gate electrode, ensuring that a conductive channel is formed. If under these conditions a positive voltage is applied to the drain electrode, a positive VDS is achieved and electrons will be injected from the source to the channel layer and then extracted at the drain electrode. The transportation of negative charge from source to drain through the channel layer generates a flow of current in the opposite direction which is denominated as drain current, IDS. As can be concluded from previous explanation, there will only be current flow between source and drain if there is a conductive channel formed between these contacts. From this last fact, we can extract the conditions that define the first operation mode of the device denominated as cut-off mode. In this mode the device is considered as being off because there is no significant current flow between the source and drain contacts due to lack of a conductive channel between them, as depicted in figure 2.3. To define the conditions on which this mode is reached, it is important to define the parameter VON. This parameter corresponds to the minimal source to drain voltage that guarantees that an electron accumulation channel is formed in the device. With this parameter defined, the condition on which the transistor is defined to be in cut-off mode can be determined as VGS <VON. Figure 2.3: TTFT in Cut-off mode Now, if we analyse the behaviour of the device when current is flowing between source and drain, which corresponds to VGS >VON (reasonably higher) and VDS >0, like with a MOSFET, we can define two different regions of operation: the linear mode, or pre-pinch-off in which VDS < VGS −Vth and the saturation mode, or post-pinch-off in which VDS ≥VGS −Vth. Before beginning to explain and characterize both of these modes of operation it is important to explain the difference between the concepts of VON and Vth in terms of what they represent in this technology. In a MOSFET the parameter that is defined as the threshold voltage, normally referred as Vth, corresponds to minimum value of VGS necessary to induce an inversion layer in the interface between the gate dielectric and the substrate of the device, to a level of charge concentration equal to that of the substrate. In a n-type TTFTs VON is the minimal voltage necessary to ensure an electron accumulation layer in the interface between the semiconductor and the gate insulator. This parameter is extracted from heuristic measures of the devices characteristics. The threshold voltage, Vth in TTFTs has no actual physical meaning, it is a pseudo-constant that is defined for analysis purposes because in these devices the current IDS measured when VGS =VON is relatively small. Vth is defined as the intersection with the x-axis of the linear part of the transfer curve of 10 Background I1/2 ds for various values of VGS. This parameter defines the minimum voltage for which the drain current characteristic is approximately proportional to the square of VGS. Figure 2.4 shows the iDS characteristic of one of the a-GIZO TFTs previously characterized at CENIMAT, here both Von and the reduced sub-threshold swing of these transistors are clearly visible. 0 1 2 3 4 5 6 7 8 9 10 0 0.5 1 1.5 2 2.5 3 3.5x 10−4 Vgs (V) Ids (A) Figure 2.4: IDS of an a-GIZO TFT biased with constant VDS Hoping that the disambiguation between those two parameters has been settled, it is possible to proceed with analysis of TTFT operation when the device is in linear mode. In this mode the device shows an IDS −VDS characteristic that is approximately linear and the value of the drain current is approximately given by IDS =µW LCG[(VGS −Vth)VDS −V2 DS 2],(2.1) where CGis the gate capacitance per unite area, µis the mobility of the electrons in the channel, W and L are, respectively, the width and length of the channel. respectively. In this mode of operation there is a continuous conductive channel that connects the source and drain, as represented in figure 2.5. TTFTs biased in linear region can be used to implement small value active resistors suitable for switching. Figure 2.5: TTFT in Linear mode The last mode of operation is saturation. In this mode, the drain voltage rises above the gate voltage. As that voltage rises, the channel close to the drain becomes depleted of carriers. The local potential difference, between the channel and the insulator, is not high enough to keep an inversion layer. Under this condition the channel is pinched-off, as represented in figure 2.6, and 2.4 a-GIZO TFT Operation Principle 11 the IDS current becomes constant, as it no longer increases with the increase of VDS. This is better explained if we consider that charge density at a generic distance form the source xin the channel is given by [27, p. 20] Qd(x) = CG[VGS −V(x)−Vth](2.2) At the drain where x=L the charge density in the channel becomes Qd(L) = CG[VGS −VDS −Vth] = 0 (2.3) In this operation mode the drain current is given by IDS =µW 2LCG(VGS −Vth)2(2.4) Figure 2.6: TTFT in Saturation mode In a final comparison between the physical operation of TFT devices and the MOSFET it is important to reference that since the substrate of TFTs does not influence their operation, TFTs do not suffer from body effect. 2.4.2 Channel length modulation in TTFTs In an ideal representation of a TTFT operation, the current in saturation was described as being constant. For this to be true the output resistance of the device would have to be infinite and this is not verified when extracting the device’s I-V characteristic. Therefore, it is crucial to explain why there is a finite output resistance and how it can be characterized. This parameter is very important to determine the intrinsic gain of the transistor, given by: Aint =−gm.ro(2.5) Returning to equation (2.2), it can be easily concluded that if VDS continues to increase, relatively to VGS, the pinch-off point will start moving towards the source because V(x) will be equal to VGS at a point x<L, thus reducing the effective length of the channel. Re-examining IDS in saturation (2.4), if the length of the channel is reduced the drain current is increased, given the fact that the drain current is inversely proportional to the effective length 12 Background of the channel. Then, the characteristic of the drain current in saturation is better approximated if we replace L by L−∆L, where ∆Lis the difference between the length of the channel and the distance between the source and the point where the channel is pinched-off. After substituting the value of the channel length in the equation, and after a few mathematical manipulations, IDS in the saturation region can be expressed by, IDS =µW 2LCG(VGS −Vth)2(1+∆L L),(2.6) considering that the position of the pinch-off point, and therefore ∆L, is approximately proportional to the VDS, we can define ∆L L=λVDS (2.7) combining (2.6) and (2.7) we can express IDS as IDS =µW 2LCG(VGS −Vth)2(1+λVDS),(2.8) where λis a proportionality constant, expressed in V−1. The above equation (2.8) shows that IDS for the saturation region is not constant, opposed to and ideal operation model, but linearly proportional to VDS, thus explaining the finite value of the output resistance presented by a-GIZO TFTs in saturation. As with MOSFET, the Early voltage, VA, is defined by the point, in the negative axis, where the straight-line formed from current characteristics in saturation regime, for different VDS values, converge. It represents the voltage at which IDS would be zero if the transistor always operated in saturation, independently of the value of VGS. This parameter can also be determined as being equal to 1/λ. The output resistance of the device can then be estimated by ro=VA IDS (2.9) 2.5 Limitations of the technology An important part of trying to implement analogue or digital circuits with a-GIZO TFTs passes through the understanding of the limitations imposed by the technology. The importance of this step is crucial because the TFT represents the main building block and if the limitations it presents are not understood, it is not possible to explore the full potential of the technology when implementing electronic circuits. On the other hand, such limitations may lead to the conclusion that for now it is not possible to implement a specific type of circuit, or that the final implementation does not present the necessary performance that the circuit designer set out to achieve at the beginning of the design process. This is a consequence of the fact the technology is still in the early stages of its development which is of course a big limitation but does not mean that it is impossible at this point to start implementing some types of electronic applications with it. Backing up this theory 2.5 Limitations of the technology 13 is the fact that some limitations presented by this technology can be circumvented using specific techniques when designing circuits. This shows that the maturing process depends not only on the improvement of the physical properties of the devices, but also on the development and improvement of circuit design techniques aimed specifically for the characteristics of the a-GIZO TFT technology. In this section the most relevant limitations of the a-GIZO TFT technology, regarding the design of amplifying stages, are addressed in order to set up the background for the design of an operational amplifier, which is the main goal of the work carried out in the Master Thesis. 2.5.1 Carrier mobility The first technological limitation to be considered, when designing amplifying stages with a-GIZO TFT, is the field effect mobility of n-type devices in a staggered bottom-gate structure. For these devices the carrier mobility has typical values around 10cm2V−1s−1, attained in the earlier stages of development, and 73.9cm2V−1s−1reported on a more recent study [22]. Comparing these values with the ones of an n-type a-SI:H TFTs, which are typically 1cm2V−1s−1, it is easy to realize that, at least in this aspect, a-GIZO TFTs are superior, but when compared with the field effect mobility values of polycrystalline TFTs, and of MOSFET devices, the field effect mobility of a-GIZO TFTs is inferior by some orders of magnitude. The mobility values affect the transconductance of the transistors in saturation given by gm =dIDS dVGS VDS,const (2.10a) =µCG W L(VGS −Vth)(2.10b) The above equation implies that gm increases with the increase of the intrinsic mobility of carriers in the device, µ. So a-GIZO TFTs will have transconductance values superior to the ones of a-Si:H TFTs but inferior to the transconductance values of polycrystalline TFTs and MOSFETs, considering of course that all devices present the same aspect ratio. From the above analysis and from (2.5), it is also demonstrated that the intrinsic gain values of a-GIZO TFTs are superior to those of a-Si:H TFTs but also inferior to the ones from polycrystalline TFTs and of MOSFETs. This in turn implies that for the same amplifying stage topology and the same load resistance, a common-source stage using a NMOS transistor for the drive will have a much superior gain to that of one using an a-GIZO TFT with the same aspect ratio. 2.5.2 Complementary devices Another limitation that is directly related to the difficulty of implementing high-gain stages, with these transistors, is the lack, at this time, of p-type transistors for this technology. The existing p-type devices present poor characteristics which make them inappropriate for circuit application, mainly due to extremely low hole mobility. 14 Background As introduced before in chapter 1, without complementary type transistors there are only two options available to the circuit designer regarding the transistor to be employed as an active load. The first option, which is to use a depletion type transistor seems to be the more logical one because we could achieve a higher load resistance with only one transistor, but to fabricate these type of transistors an extra mask would be necessary increasing the overall fabrication cost. With the possibility of low fabrication costs being one the the main advantages of this technology, this option becomes somewhat counter-productive. Thus the best option really seems to be the implementation of electronic circuits with only n-type enhancement a-GIZO TFTs. This of course has a very big impact on the gain values achievable in high-gain stages such as the simple commonsource stage. Consider a common-source stage using a complementary device as an active load, as depicted in figure 2.7 the gain of this stage is given by, Figure 2.7: Generic Common-source amplifier with complementary active load Av=−gm.(roN||roP),(2.11) if rois the same in both the driver and the load transistors, the gain becomes equal to Av=−gm.roN 2,(2.12) which is half of the intrinsic gain of the drive transistor. Considering now the same topology but implemented with only n-type enhancement transistors, as represented in figure 2.8. The gain of this stage now is given by Av≈−gm1 1 gm2 (2.13) Since gm is directly proportional to the aspect ratio of the transistors (2.10), the gain of this stage is given by the relation of the aspect ratios of the drive and load transistors. In this configuration, to achieve, for example, a 20dB gain, the gate of the driver transistor would have to be approximately 10 times wider than the gate of the load transistor, considering that both transistors have the same gate length. This leads to circuits with a large area, poor performance because of the large gate capacitance associated to the driver transistor and the use of higher supply voltages. Unlike the low-carrier mobility, the non-existence, at this time, of viable complementary devices can be compensated if positive feedback is used in the active load. This topic will be explored in section 2.6.2. 2.5 Limitations of the technology 15 Figure 2.8: Generic Common-source amplifier with diode connected enhancement load 2.5.3 Gate-bias Stress Of all the limitations currently presented by this technology the one that is probably the biggest obstacle to the development of electronic circuits and specifically analog circuits is the existence of gate-bias stress. This phenomenons corresponds to the change, over time, of a transistor’s threshold voltage, Vth, due to constant biasing. This effect has been also verified in other TFT technologies, such as a-Si:H, and impacts the behaviour of amplifying stages in a significant manner. Consider the simple common-source with only n-type enhancement transistors stage previously presented in 2.8. If we take into account that due to constant positive biasing of the transistors their threshold voltages will increase as time passes, eventually at least one transistor in the circuit will get out of the saturation region and will go into cut-off as Vth >VGS, and the circuit will stop working. Since this effect can become quite significant in short periods of time, variable according to the fabrication processes, ranging from some minutes to a few hours, the produced circuits will have low lifetimes. But, at least for the most part, when the circuits are turned off the effect is also reversible, although it can take hours or even a few days [28]. The cause of this effect has been attributed to a trapping of charge carriers in defects that exist in the dielectric and at the interface between the semiconductor and the dielectric [29]. These defects generate extra electron states that can be occupied due to stress. The Vth shift with time, due to biasing, can be expressed by [1, 30, 31], ∆Vth =Vth0(1−e−t τ β),(2.14) where τis a characteristic time constant, βis the stretched-exponential exponent, and ∆Vth0is the device threshold voltage shift as time goes to infinite. The annealing of a-GIZO devices, introduced in section 2.3.3, reduces the effects of the shift in the threshold voltage [31]. Gate-bias stress is not the only phenomenon with impact on the stability of a-GIZO TFTs. It has also been demonstrated that the device characteristics are sensitive to light, exposure to water vapour and to temperature variations [32]. Nonetheless, for the purpose of designing amplifying 16 Background Figure 2.9: Time dependence of ∆Vth for gate bias stresses, reprinted from [1] stages the most relevant cause of device instability is the shift over time in the Vth, in consequence of the constant biasing of the gate. 2.5.4 Contact Resistance As introduced earlier in section 2.3.2, the materials employed for source and drain contacts also influence the overall performance of the a-GIZO TFT because of possible high values of contact resistance that can be attained. High values of contact resistance at the source/drain electrodes cause an effect of current crowding that negatively affects various electrical characteristics of the device, such as the threshold voltage, the mobility of carriers in the channel, the ratio between on and off currents and the subthreshold voltage swing [33]. Barquinha et al. reported a study of a-GIZO TFT characteristics for different source/drain materials, IZO, Ti, Mo, Ti/Au with the annealing process done both before and after the deposition of the materials [24]. This study concluded that of these materials Ti/Au was the one who led to a higher µf e and that there was a significant reduction in this parameter for devices with lower values of L, which was attributed to a higher influence of contact resistance in the total resistance of short-channel devices. It was also concluded that if the device was annealed after the deposition of source/drain electrodes, the electric characteristics achieved were improved. In terms of the design of amplifier stages, the impact of this issue is again related to decreased values of the mobility of carriers in the channel, which leads to a lower intrinsic gain of the transistors. 2.5.5 Gate Capacitance Devices built in bottom-gate staggered configuration present an additional limitation, which is the large value associated with the parasitic gate capacitance. The high gate capacitance value is the result of a significant overlap between the source/drain electrodes and the gate. As in a MOSFET device, the overlap is increased with an increase in the dimensions of W and L. The total gate 2.6 Operational Amplifier Design 17 capacitance can be approximated by the sum of the channel and overlap capacitances, assuming that these capacitors are linear. CChannel =CG×W×L(2.15) COverlap =CG×W×Loverlap (2.16) CGate =CChannel +COverlap (2.17) From this model it can be verified that if the length of the overlap between the source/drain electrodes and the gate is significant, relatively to the effective channel length, the overall gate capacitance of the transistor will be increased significantly. In terms of amplifying stages, high values of gate capacitance lead to potential low-frequency poles, affecting the overall frequency response and bandwidth of the circuits. 2.6 Operational Amplifier Design After going through the analysis of the limitations posed by the transistor that was used in this work it is important to also have knowledge about the various steps that are involved in the design of an operational amplifier. In this section some background information regarding the design of opamps, such as the definition of target parameters and the analysis of topologies with more than one stage are presented so that the reader may better understand the work presented in later chapters. The concept of positive feedback applied in the increase of load resistances is also introduced because this technique played an important role on the amplifier topologies that were developed. To start, it is important to state the importance of Operational Amplifiers (opamp). These electronic circuits are an essential part of modern day electronics and are of vital importance in mixed signal circuits where they find a wide application spectrum, both in linear (e.g. amplification and filtering) and nonlinear applications (e.g. comparator). The application of opamps in microelectronics is very diverse and the design of operational amplifiers is often more oriented for specific applications than for generic purposes. For this reason the design of operational amplifiers follows different objectives than those that are intended to achieve amplifiers with characteristics similar to those of the an Ideal opamp, namely high open-loop gain, very high-input resistance and a low-output impedance. This change in paradigm occurred due to the existence of other characteristics associated with the performance of opamps besides these last three and because there are trade-offs between some of these characteristics. Therefore, it is necessary to design these circuits considering that there are many variables associated with this process and knowing that by trying to maximize a certain characteristic, such as 24 Background capacities, are given by, CA=CGS3+CGS4(2.20a) ReqA =ro1||ro3|| 1 gm3 (2.20b) CB=CGS6+CGD6(1−A)(2.20c) ReqB =ro2||ro4(2.20d) CC=Cload +CGD7(2.20e) ReqC =ro6||ro7(2.20f) From this analysis it is possible to verify that if 1/gm3<< ro1||ro2, the pole associated with node A will be at high frequencies and the dominant poles of the amplifier will be the ones associated with nodes B and C, due to the large capacitor value at node B, originated by the Miller multiplication of CGD6and the potentially high values of Cload that may be connected to node C. Due to the relative difference in the frequency domain between the two dominant poles and the third pole, the negative phase shift due to the effect of the dominant poles may possibly lower the phase margin in such a way that it comes close to zero, making the system potentially unstable. The principle of frequency compensation for this topology is to move the dominant pole of the system towards lower frequencies. Considering the pole associated with node B to be the dominant before compensation, one way of lowering its frequency is by using a capacitor connected between nodes B and C. This capacitance will be multiplied by Miller effect, introducing a very-large capacitance at node B and moving the pole associated with this node closer to the origin. As an additional effect of adding the compensation capacitor, the pole associated with node C is moved away from the origin [27, p. 363] (pole splitting). A drawback associated with this method is the possibility of CLoad being unknown or variable, which degrades the phase margin of the op amp if the non-dominant pole, associated with the output, is moved closer to the dominant pole due to a high output capacitance. The use of a compensation capacitor also introduces a right-half plane zero at low frequencies, which contributes to a degradation of 90oin the phase of the opamp, further reducing the phase margin of the system and potentially turning it unstable. This right-half plane zero derives from the feedforward formed by the compensation capacitor. Considering the topology in 2.17, the right-half plane zero can be moved to very high frequencies if the compensation capacitor only conducts current from the output to node B but not in the opposite direction [27, p. 369]. This behaviour can be imposed by using a source-follower in series with the compensation capacitor, as seen in figure 2.18, if the gate-source capacitance of this transistor has a value much inferior to that of the compensation capacitor. Another possibility for removing the right-half plane zero is to move it in frequency and ideally make it so that it goes to a frequency in the left-half plane. In this case it can be used to cancel one of the non-dominant poles of the opamp. One way of doing this is by placing a resistor in 2.6 Operational Amplifier Design 25 Vdd Vbias Vin1 Vin2 Vout M1 M2 M3 M4 M6 M5 M7 A B C Cc M8 M9 Figure 2.18: 2-stage Miller Opamp with a source follower in series with the compensation capacitor series with the compensation capacitor, usually implemented by a transistor in the triode region as depicted in 2.19. In this case the frequency of the zero will be approximately given by ωz=1 Cc(1 gm6−Rc)(2.21) Vdd A Cc Vout M1 M2 M3 M4 C B Vbias M5 M6 M7 M8 Vres Vin1 Vin2 Figure 2.19: 2-stage Miller Opamp with transistor in triode in series with the compensation capacitor 2.6.4 Single-ended Amplifiers vs Fully-differential Amplifiers Another important analysis to be done, during the design of operational amplifiers, is to decide if the configuration at the output should be single-ended or differential. As referred earlier, the input stage of an operational amplifier is always a differential pair and this stage possesses two outputs that have the same magnitude but a 180ophase difference between them, under the assumption that the differential stage is completely symmetrical. In spite of this, the most common operational amplifier topologies are single-ended, presenting a differential input and a single-ended output. A symbol representation of this topology can be seen in figure 2.20. 26 Background − + Figure 2.20: Symbol representation of a single-ended opamp The use of opamps with differential outputs, figure 2.21, brings, however, advantages when compared with single-ended topologies. Some of these advantages concern the avoidance of mirror poles that are introduced by differential to single-ended conversion, leading to higher closedloop speed, greater swings at the output of the differential pair and the cancellation of even-order harmonics [27, chap. 9]. A disadvantage is the need for common-mode feedback in high-gain fully-differential amplifiers when using technologies with complementary transistors. The output common-mode level in these topologies is sensitive to the properties of the transistors and possible mismatches, and cannot be resolved by the negative differential feedback. − + + − Figure 2.21: Symbol representation of a fully-differential opamp 2.6.4.1 Common-Mode Feedback The purpose of common-mode feedback is to sense the common-mode levels of the two outputs of a fully differential amplifier and adjust the bias currents of the differential stage in order to control the common-mode level of the outputs, so that none of stages of the amplifier saturates when negative differential feedback is applied to the circuit. A generic scheme of a common-mode feedback network is presented in figure 2.22. The task of CMFB can be divided in three operations: •sensing of the common-mode level at the differential outputs •comparison with a reference •feedback of the error to the amplifiers biasing network 2.6 Operational Amplifier Design 27 Vdd CM Measurement − + Vref Vout2 Vout1 (Vout1+Vout2)/2 Ibias Figure 2.22: Generic representation of a CMFB topology There are various ways of sensing the common-mode (CM) level at the outputs and of carrying out the comparison of this level with a reference. It is up to the circuit designer to define and employ a CMFB topology that can better suit the configuration of the differential amplifier used and of course the circuit in which the amplifier is to be applied. In particular, the CM sensing method has a great influence on the performance of the amplifier’s differential loop because the sensing scheme loads the output of the stage at which the CM level is being measured. Typically the sensing of the CM level is done with: •Resistors •Transistors in triode •Source-followers •Capacitors Simple examples for these sensing schemes are shown in figure 2.23. Analysing the different topologies presented above the following conclusions can be taken: •Using resistors the load impedance of the differential amplifier is altered and the differential gain is potentially hindered. •The use of transistors in triode introduce non-linearity because their on resistance depends on the mobility of charge carriers in the channel. •Employing source followers also affects the linearity of the CMFB network and introduces extra poles in the system. •Sensing the common-mode level through capacitors does not affect the differential gain but lowers the frequency of the poles present at the output node. Still, it is a highly linear method and in regular IC design the capacitors can be fabricated with great accuracy, leading to low matching errors. 28 Background VCM,out Vop Von (a) CM level sensing with resistors Vop Von VCM,out (b) CM level sensing with transistors in triode Vdd VCM,out VonVop (c) CM level sensing using source followers Vop Von VCM,out (d) CM level sensing with capacitors Figure 2.23: Common configurations used to sense the CM level at the output of a fully-differential amplifier It is important to emphasize that there are two types of common-mode feedback networks, switched or continuous. Switched CMFB networks use capacitors to sense the CM level and are typically employed in switched capacitor circuits. Continuous networks are typically employed in continuous applications and tend to use the other sensing methods referred. Regarding the operation of the two different types of networks it is easy to deduce that in the case of a continuous network the measurement of the CM level is carried out continuously. The principle of the switched-capacitor networks is however partially different. This is so because in these types of networks the sensing of the CM level and respective comparison to a reference voltage are implemented only through the use of sensing capacitors which are precharged to a reference voltage [34]. This principle can be demonstrated by the following example. Consider the simple capacitor sensing pair depicted in figure 2.23d. In one clock phase both capacitors will be precharged to a reference voltage, Vre f . An illustration of the state of the system in this clock phase is shown in figure 2.24a. In the other phase of the clock the CM level will be sensed by the capacitors that are connected to nodes Vop and Von, which represent the differential outputs of the opamp. Then, voltage Vb, which represents the output of the common-mode feedback circuit and also the bias voltage to be applied to the biasing network of the opamp, is obtained by: Vb=C1VC1+C2VC2 C1+C2(2.22) 2.6 Operational Amplifier Design 29 C1 C2 VrefVref (a) Precharge phase C1 C2 Vb + − + − Vref Vref Vop Von Vc1 Vc2 (b) Sensing and comparison phase Figure 2.24: Operation principle of a switched-capacitor CMFB network Considering that in this last clock phase the voltages VC1and VC2correspond respectively to the voltages Vop and Von level-shifted by Vre f , determined as VC1=Vop −Vre f and VC2=Von −Vre f , equation 2.22 then becomes: Vb=Vop +Von 2−Vre f (2.23) Looking closely at the previous equation we see that the term (Vop +Von)/2 corresponds to the common-mode voltage at the output of the opamp and that it is being compared to the reference voltage. Thus, if the reference voltage is correctly defined as Vcmre f −Vbias, where Vcmre f is the desired common-mode voltage at the output, and Vbias is the voltage that when applied to the biasing network guarantees the desired common-mode level at the output, the switched-capacitor CMFB network will function as expected and will impose the desired CM voltage at the output when it reaches steady-state. 2.6.5 Switched Operational Amplifier The final concept summarized in this theoretical background is the switched opamp technique, which is employed in one of the novel topologies proposed in this work. Being first introduced by Crols and Steyaert in 1994 [8], this technique is mainly used in low-power IC design. As the name might already imply, a switched operational amplifier is in short an operational amplifier in which at least part of the circuit is switched off in one of the clock phases. For this reason, it is exclusively employed in switched capacitor configurations. The motivation behind the proposal of this technique was the need for circuits that could operate at very low supply voltages and that would also decrease overall power consumption. Until the proposal of this technique there were only two ways of implementing switched-capacitor IC’s with very low supply voltages, either through the use of transistors with low threshold voltage or with on-chip voltage boosters. The former option is expensive [9] and the latter may cause reliability problems in the long run because of the maximum allowed voltage being exceeded [35]. In terms of implementation a switched opamp is in its core a regular opamp with the addition of internal switches that are used to turn-off all or some of the biasing currents in the circuit during the clock phase where the amplifier is not required. It is important to note that the output stage must always be turned off during this phase to put the output in a high impedance state and therefore avoid the discharge of capacitors connected to this node. The number of stages disabled during the off-phase, the levels of voltage imposed at the output when the amplifier is turned off and the 30 Background switching schemes employed are determined in CMOS by the minimum turn-on speed desired, power-consumption requirements and by the topology employed in the core amplifier itself. An example of an application where this technique can be employed is the Sample-and-Hold because the opamp is only required during the holding phase and can be partially or completely turned-off during the sampling phase. 2.7 Summary In this chapter an overview was given on the characteristics of the a-GIZO TFT from the materials to its internal characteristics and limitations when compared to well know silicon based technologies. This overview is instrumental in the comprehension of many of the topologies used throughout this work, as the design of the topologies presented in chapters 4 and 5 is greatly conditioned by the specific characteristics of the a-GIZO TFT technology used. Along with an overview on a-GIZO TFT a set of concepts regarding the design of operational amplifiers is also given. These concepts are intended to help the understanding of developed topologies, as some of them are not commonly used in typical operational amplifier designs. For this reason, relevance is given to the concepts of fully-differential opamps, common-mode feedback, design of high-gain stages with only n-type enhancement transistors and switched operational amplifiers, all of which play an important part on the opamp topologies presented in later chapters of this document. Chapter 3 Bibliographic Review In this chapter an assessment on the current state of operational amplifiers with single type transistors on TFT technologies, with characteristics similar to the ones of a-GIZO, is presented, along with the review of some old articles related to the design of high-gain operational amplifiers in technologies with only n-type transistors. Finally, the state of the art regarding switch operational amplifiers is summarised. The atypical structure of this bibliographic review is justified by the fact that although a non negligible number of circuit implementations, with a-GIZO TFTs, does exist, these implementations are mainly for digital circuits. Also, to the knowledge of the author, to date no operational amplifier has ever been built with a-GIZO TFTs. This fact, plus the limitations associated with a-GIZO TFT technology, presented in 2.5, motivates a review on amplifier design with solely ntype transistors. The exploration of this subject was done mainly during the 70’s because CMOS technology was not yet fully matured as it is today. Although some of these techniques are now obsolete for MOSFET technologies, they are of great importance to the design of opamps with a-GIZO TFTs, because for now p-type devices are not yet viable for circuit implementation. The state of the art on switched opamps is presented because one of the topologies developed is of this kind. The state of the art in circuits with a-GIZO TFT is however included in appendix F to give the reader an overview on the circuits implemented to date with this technology even if it is not directly related with the work presented in this Thesis. 3.1 High gain Operational Amplifier Implementations with only ntype enhancement transistors The research in the design of operational amplifiers with only n-type enhancement transistors was explored in the 70’s and in the 80’s for NMOS. Along this period, several different techniques of achieving high gain and of realizing frequency compensation in opamps with only n-type enhancement transistors were proposed. Facing the limitation of not possessing complementary devices in a-GIZO TFT technology, it is important now to analyse the work done previously in the field 31 32 Bibliographic Review of n-type amplifiers, in order to be able to establish a background for opamp design with a-GIZO TFTs. In 1976 Tsividis and Gray [2] reported an NMOS operational amplifier designed to drive capacitive loads of 50pF, with fast settling. A block diagram and the complete schematic of this amplifier are presented in figures 3.1 and 3.2, respectively. In the reported operational amplifier, the voltage gain is achieved by making the drive transistors much wider than the diode connected n-type enhancement mode transistors used as active loads, which leads to a bigger area consumption, bigger input capacitances in the drive transistors and does not give a very significant gain per stage. Nonetheless, voltage gain was not the main objective in this design but rather the settling time of the circuit when driving capacitive loads. Many techniques were employed to improve the amplifiers frequency response. The first of which is the cascode stage that is connected to the output of the differential to single-ended converter stage in order to decrease the load capacitance seen by this stage, which otherwise would be big due to Miller effect and would degrade the overall frequency response of the opamp. Other examples of design techniques used to improve the frequency response of this circuit are the source follower applied to drive the output stage, which isolates the input capacitance of the output stage from the cascode stage, and the shunt-shunt feedback topology used at the output stage to reduce the overall output resistance of the amplifier, with the purpose of increasing the frequency of the pole associated with the output when driving capacitive loads. The most relevant frequency compensation technique employed in this opamp was, however, the compensation capacitor applied between the output of the differential to singleended converter stage, and the output of the cascode formed by M20 and M19. This capacitor is multiplied by Miller effect to set the dominant pole of the opamp. Another interesting aspect of this compensation scheme is the source-follower M13 that is connected in series between the output of the cascode stage and the compensation capacitor. This source follower is used to shift the right-half plane zero introduced by the compensation capacitor, to high frequencies, since the capacitance at the gate of the source follower is expected to be much smaller than that of the compensation capacitor. If this right-half plane zero was not shifted to high frequencies, the phase of the amplifier would be decreased by 90oaffecting the phase margin of the system. The proposed amplifier is reported as having a 51 dB low-frequency gain, a 70 dB CMRR and a unity-gain frequency of 5MHz. Figure 3.1: Block diagram of the internally compensated NMOS opamp reported by Tsividis and Gray in 1976, reprinted from [2] 3.1 High gain Operational Amplifier Implementations with only n-type enhancement transistors33 Figure 3.2: Complete schematic of the internally compensated NMOS opamp reported by Tsividis and Gray in 1976, reprinted from [2] In 1979 Young [3] presented another operational amplifier with only n-type enhancement type NMOS transistors. A block diagram and the complete schematic of this amplifier are presented in figures 3.3 and 3.4, respectively. The topology proposed in this work was similar in many aspects to the one presented previously by Tsividis and Gray [2]. The gain stages were also implemented with enhancement mode transistors, using the differences in the relative dimensions of W and L for the drive and load transistors to determine the voltage gain of the stages, with the topology of the output stage being the same as well. However, in this topology the frequency compensation scheme was implemented in a different way. This compensation scheme starts at the output nodes of the differential stage, the positive output is fed to a source follower, M9, and then to a high-gain stage that also inverts the signal. On the other hand, the negative output of the differential stage is applied to a source follower, M11, and then summed in phase to the other differential component in the output of the high-gain stage composed by transistors M12 and M11. Between the input and the output of this stage, a compensation capacitor is connected, which introduces a high capacitance at the gate of M12 due to Miller effect, determining the dominant pole of the amplifier and also introducing a right-half plane zero in the system. Each of the source followers used introduce a zero and a pole in the system as well. From this analysis, the author implemented a frequency compensation scheme by defining a value for the dominant pole associated with the compensation capacitor and for the VGS voltages of the source followers M9 and M11 that try to place all the zeros of the system that occur below the unity gain crossover frequency, close to their matching pole in order to ensure pole-zero cancellation. For this amplifier, a low-frequency voltage gain of 66.84dB is reported, along with a CMRR of 72dB and a unity-gain frequency of 3MHz, achieved through the additional use of two-bypass capacitors in the source follower signal paths used to move the dominant zero, introduced by the compensation capacitor, to a frequency close to that of the second dominant pole. The reported low-frequency gain of this topology was very high but at the cost of area because it was achieved through manipulation of the aspect ratios of drive and load transistors in the gain stages. In addition, the frequency compensation scheme required the 40 Bibliographic Review Figure 3.9: Complete schematic of the Switched opamp presented by Crols and Steyaert in 1994, reprinted from [8] The proposed topology worked with a power supply voltage of 1.5V with the input and output common-mode levels equal and defined as 0.425V and with it a low-Q biquad filter, shown in figure was implemented. The implemented filter was shown to have a total harmonic distortion of -64dB for a output swing of 550mVpp. Also as an additional performance advantage it is stated that the overall power consumption was reduce to 75% when compare to the one attained if the amplifier were to be always active. Figure 3.10: Schematic of the low-Q biquad filter with switched opamp presented by Crols and Steyaert in 1994, reprinted from [8] As precursors of switched opamp techniques, the authors also established many principles that still serve to this day as the foundations of the entire switched opamp theory. Of these concepts the most important is maybe the one that states that a switched opamp technique can be applied in every switched capacitor circuit in which every switch is connected either to the output of the OTA (operational transconductance amplifier) or to a reference voltage. This property showed that the switched opamp could have a wide range of applications because it means that good number of switched capacitor circuits can be adapted into an equivalent circuit that uses an opamp of this type. Three years later, in 1997, Baschirotto and Castello proposed a different approached for the realization of a switched opamp. The main difference between this topology and the one previously presented is the use of a fully-differential output and of a common-mode feedback circuit, which is necessary since the opamp was implemented in CMOS. Other alterations proposed in this 3.3 Switched Operational Amplifiers 41 work were aimed at the increase of swing levels and at the reduction of the turn on-time of the circuit. The swing levels were increased using different common-mode voltages for the input and output, which were set at Gnd and Vdd/2 and lead to a lower minimum supply voltage than the one attained in the previous work, while enabling at the same time a rail-to-rail output swing when combined with the use of a folded structure at the input stage. The reduction in turn-on time was achieved by only turning-off the output stage and by opening the connection of the compensation capacitors to the input stage during the turn-off phase so as to keep these capacitors charged. An image of the complete topology proposed in this work can be seen in figure 3.11. With this amplifier a switched-capacitor filter using a 1V supply was implemented in a 0.5µm CMOS topology, presenting a power consumption of 160µW. This filter could be operated with a 1.8MHz frequency and according to the authors it would still be operational with supply voltages as low as 0.9V. Figure 3.11: Complete schematic of the switched opamp proposed in 1997 by Baschirotto and Castello, reprinted from [9] In the following year Waltari and Halonen introduced in switched opamps the concept of using the common-mode feedback network to also speed up the turn-on of the operational amplifier as well as setting the CM-level at the output [10]. Another interesting characteristic of this topology is the use of a cross-couple load in the input stage, which eliminates the necessity of including another CMFB circuit for the first stage of the amplifier. The cross-coupled load presents a high resistance for differential signals but a low resistance for common-mode components, which guarantees for this topology that the rejection of common-mode disturbances will be considerable in the input stage. The authors used this property to apply CMFB only to the output stage which makes the CM loop simpler an with lesser poles leading to a faster settling of the CM-level at the output of the opamp. In this way the need for signal inversion in the CM loop is also avoided making the implementation of this network with passive components possible. The complete amplifier topology is presented in figure 3.12. From the analysis of the remaining topology it is possible to see that, apart from the details discussed above, this topology has many common aspects with that proposed by Baschirotto and Castello 3.11. A folded cascode structure is also used in the input stage, only the output stage is turned-off and the compensation 42 Bibliographic Review capacitor has a series switch to ensure that it stays charged during the phase where the amplifier is turned-off, which, as seen in the previous work, is a way of increasing the overall turn-on speed of the circuit. Figure 3.12: Complete schematic of the switched opamp proposed in 1998 by Waltari and Halonen, reprinted from [10] The common-mode circuit proposed in this work is depicted in figure 3.13. This circuit as four capacitors C1-4, three of which, C1-3, must be of the same value for proper functioning of the circuit because these are the capacitors involved in the measurement and comparison to the reference level of the CM voltage at the outputs. The sensing and comparison operation for the CM level can be summarized in the following way. During the amplifier’s off phase C1 and C2 are charged to Vdd because the output of the opamp is railed to this level and n0 is pulled to ground using a switch. In the same phase C3 is reset as both of its terminal are connected to ground. When the amplifier is turned on C3’s top plate will be connected to Vdd and the top plates of C1 and C2, which remain connected to the differential outputs of the amplifier, will tend towards Vdd/2. Therefore when steady state is reached the voltage at node n0 will be ideally equal to ground as half of the charge stored in C1 and C2 during the off-phase is used in the on phase to charge C3 to Vdd. The remaining capacitor, C4, is used as a level shifter in order to apply a voltage with an adequate dc level to the active load of the output stage, which is implemented with a NMOS transistor. This level shift capacitor in precharged during the amplifiers off phase using a replica of the current source present in the amplifiers output stage. So, when steady state is reached the voltage applied to the active loads of the output stage is equal to the reference voltage at which C4 was precharged, which means that the circuit maintains the same operation principle of a switched capacitor CMFB netowork, previously presented in 2.6.4.1 but adapted into the specific context of switched opamps. In terms of measured characteristics it is only mentioned that the opamp can work with a 1V supply. However the specific technology used for the implementation is not stated. 3.3 Switched Operational Amplifiers 43 Figure 3.13: Schematic of the SCCMFB network proposed in 1998 by Waltari and Halonen for their switched opamp, reprinted from [10] More recently, in 2008, Qin et al. presented an improvement proposal for the switched opamp presented above [11]. Figure 3.14: Schematic of the switched opamp proposed in 2008 by Qin et al., reprinted from [11] Depicted in figure 3.14, this topology employs most of the characteristics that had been introduced in the fully-differential switched opamps presented in [9] and in [10], such as the use of different common-mode voltages for the input and output of the circuit, set as ground and Vdd/2 respectively, the switch in series with the compensation capacitor and the use of a folded cascode structure in the input stage with a cross-coupled load, albeit this time presenting a cascode structure. However, as a distinctive feature, this topology used a revised version of the CMFB circuit porposed in the work of Watari and Halonen. This CMFB circuit, depicted in figure 3.15, is based on the previous implementation proposed by the other authors but with the addition of an extra nonlinear amplifier to the loop. This extra component increases the voltage gain in the CMFB loop and provides a larger discharge current for the output stage of the amplifier during turn-on, consequently reducing the overall turn-on time of the opamp. 44 Bibliographic Review Figure 3.15: Schematic of the CMFB loop porposed by Qin et al. for their switched opamp, reprinted from [11] With this opamp a sample-and-hold operating at 1V was implemented in a 0.18µmCMOS technology. This circuit is said to achieve 50MSPS (mega samples per second) with a THD (total harmonic distortion) of -76dB and a SFDR (spurious-free dynamic range) of 76dB over the entire Nyquist Rate. The topology for the sample-and-hold is presented in figure 3.16 and as it can be seen that the output of the circuit is not taken at the output of the amplifier but in the opposite plate of the feedback capacitor. The selection of this point for the output is justified by the fact that in this way a loading free architecture can be implemented using the feedback capacitor of the sampleand-hold to serve as the input capacitor for another circuit. An approach that makes perfect sense considering that a sample-and-hold is always used as a part of a larger signal processing chain like, for example, an ADC (analog-to-digital converter). Figure 3.16: Schematic of the sample and hold implemented by Qin et al. using their switched opamp, reprinted from [11] In terms of its operation the circuit is configured to accommodate the existence of different common-mode voltages at the input and output of the amplifier during its active phase as well as the setting of the voltages in these terminals to Gnd and Vdd, respectively, during turn-off. The opamp is turned-off during the sampling phase because in the holding phase the amplifier must be active for there to be transfer of charge from the sampling to the hold capacitor. The equations for 3.4 Summary 45 the charge and holding phases are respectively QS= (Vin −gnd).Cs+(V dd −gnd).Cf(3.3a) QH= (Vdd −gnd).Cs+(Vout −gnd).Cf(3.3b) Since the input signal and the output voltage of the amplifier in the holding are defined as Vin =Vdd/2+vsignal and Vout =Vdd/2+vsignal,QSand QHwill be equal ensuring the correct operation of the sample and hold configuration. 3.4 Summary In this chapter a review of the state of the art is given for opamps with only n-type enhancement transistors, opamps with TFT technologies that have a single type of transistor and switched operational amplifiers. No review is given on previous opamps with a-GIZO TFTs as there are none reported to this date, which also constitutes the reason for the review of operational amplifiers in technologies with similar characteristics. The bibliographic review on switched opamps is presented to better contextualize the introduction of this concept to the design of operational amplifiers with a-GIZO TFTs presented in chapter 5, as although the developed switched opamp is fairly different to those that currently exist for CMOS, many of concepts presented in work here reviewed were employed or adapted in the work carried out in the present thesis. 46 Bibliographic Review Chapter 4 Development of the a-GIZO TFT Operational Amplifier This chapter presents the detailed description of the design of the a-GIZO TFT operational amplifier and the respective results obtained from the simulation of the proposed topology. Before detailing the design process of the operational amplifier it is very important to highlight both the methodology and performance goals that were defined for this work. These two steps are of paramount importance because the overall approach taken in the design process helps contextualize the majority of the decisions taken. 4.1 Methodology To define the methodology the first thing that needs to be kept in mind is that working with a technology that is still in a research phase will always result in a great component of exploratory work. This last fact becomes even more apparent when all the limitations associated with the technology are considered, especially due to the fact that the simulation model used for the TFT is itself still not a completed work, as it does not characterize the intrinsic capacitances of a-GIZO TFTs. For this reason great care was taken in the definition of the methodology in order to ensure that results and conclusions could already be taken from simulation, at least to some extent. In this way the work developed could be partially validated through simulation instead of becoming exclusivity dependent on the results taken from fabricated circuits. Taking these factors into account the decision was made on using both the a-GIZO TFT model and that of a commercial NMOS technology. Therefore all of the topologies developed were also implemented and simulated using a BSIM3V3 model in 0.35µm technology. An accurate model for MOSFET simulation can be used to validate the developed topologies since in terms of operation principle our device is also a field effect transistor and has been proven to present a drain current characteristic that can be approximated with a reasonable accuracy using the level 1 MOSFET equations. Still, in order to try and replicate the behaviour of circuits with a-GIZO 47 48 Development of the a-GIZO TFT Operational Amplifier TFTs, the following precautions were taken in order to ensure that the circuits implemented in NMOS operate under similar conditions: •Only n-type enhancement transistors were used because this is the only type available in the a-GIZO TFT technology. •The body-effect was mitigated by connecting the body to the source in all NMOS transistors as there is no body effect in TFTs. •Wide transistors were used to avoid narrow and short channel effects. The rest of the design methodology was similar to that of a typical IC design and involved the conceptual study of the topologies employed, performing appropriate simulations for the developed circuits, optimization of these circuits according to a set of performance goals and finally the production of their layout so that they could be fabricated and validated through physical characterization. After this process the next step taken was the definition of the preliminary performance goals for the amplifier. This process took into account the objectives of the Master Thesis but also the limitations of the technology that were known at the beginning of the design process so that the objectives defined could be met. 4.2 Performance Goals The first step in this stage was to select the context in which the amplifier was to be applied. A first decision was then made to have generic switched capacitor circuits as the target application for the opamp because in a-GIZO TFTs the ratio between gds and gmis much smaller than the one typically encountered in MOSFETs. This implies that even a topology with an output impedance of 1/gmwould present significant output impedance. In fact, from the simulations performed, the typical gmvalues for the a-GIZO TFTs used were found to be in the order of some tens of µA/V. Consequently 1/gmwould easily reach several tens of kΩwhich in practical terms translates in a necessity of using very high values of resistors in the feedback network so as not to significantly diminish to open loop gain of the opamp. In switched capacitor circuits however, there is no resistive loading of the amplifier which makes them a more suitable application for an opamp designed in this technology due to the limitations regarding the implementation of gain stages. Still, the capacitors in the feedback network will provide capacitive loading at the output which must be taken into account in the stability analysis of the opamp. With the selection of switched capacitor circuits as the target application a generic analysis regarding these circuits was made in order to identify the common performance goals that should be met by an opamp employed in these types of circuits. In switched capacitor applications speed and accuracy are two very important performance parameters. Both of which are affected by characteristics of the opamp used, namely its voltage gain and gain–bandwidth product. The latter characteristic influences the settling time of a switched 4.2 Performance Goals 49 capacitor circuit, which will tend to be smaller for higher values of gain-bandwidth product. On the other hand, the voltage gain of the opamp is directly related to the accuracy of the steady state value. To comprehended this effect let us briefly analyse the static error that occurs when a voltage step with amplitude Vstep is applied to the input of the opamp. In a real opamp with finite voltage gain, Aol, the static error will be given by εs=Vstep/β−Vout Vstep/β=1−βAol 1+βAol ,(4.1) where βis the feedback factor and Aol is the amplifier’s open loop gain. Assuming that βAol 1 the previous expression can be further simplified to εs=1 βAol (4.2) Ultimately the maximum acceptable tolerance in the static error determines the minimum open loop gain required for the op amp which is directly obtained by manipulating equation 4.2. Aol =1 βεs (4.3) In terms of the impact of the gain-bandwidth product on the settling time for a switched capacitor circuit, the following approximation for the closed loop gain of an opamp is considered [36, p. 852]. ACl =1/β 1+jf funβ ,(4.4) where fun is the gain-bandwidth product calculated as f3dB.Aol(0). In the previous assumption the system possess a single pole, which is a valid approximation if the dominant pole occurs at much lower frequencies than the first non-dominant pole. From equation 4.4 the closed loop time constant can obtained as τ=1 2πfunβ(4.5) If slew rate limitations are neglected, the output voltage of the circuit in response to a voltage step input can be approximated by using the simple equation for capacitor charging Vout (t) = V0(1−e−t τ)(4.6) If for example a 1% settling is required at least 5τseconds are needed, so it is important to have a unity gain frequency as high as possible so as to reduce the time constant and consequently increase the speed and the maximum switching frequency of a switched capacitor circuit. In a more simplified analysis an estimate for the settling time can be obtained as a rule-of-thumb by 1/(funβ)[36, p. 853]. 56 Development of the a-GIZO TFT Operational Amplifier Aol =gm2+gm.gds (A f −1).(2.gm.gds +gm2)+(a−1).(2.gds2+gm.gds)−gds2(4.10a) Rload =ro 1−a−gm.(A f −1).ro (4.10b) a=gm.(A f 1−A f +1)+gds gm +2.gds (4.10c) In simulation the analysis of the voltage gain and of the gain factor awere first performed using a BSIM3V3 model for a 0.35µmNMOS technology. Also, the implementation of the feedback networks for this simulation was realized using an ideal opamp in order to accurately control the feedback factors. At this point the objective is to demonstrate the validity of the equations as well as estimating the variation of the voltage gain with relation to the variation of the feedback factors Af and Af1. 100101102103104105106107108 −40 −20 0 20 40 60 80 100 120 Frequency (Hz) Gain (dB) Af=0.90 Af=0.92 Af=0.94 Af=0.96 Af=0.98 Af=1.0 (a) Gain 100101102103104105106107108 0.88 0.9 0.92 0.94 0.96 0.98 1 Frequency (Hz) a Af=0.90 Af=0.92 Af=0.94 Af=0.96 Af=0.98 Af=1.0 (b) Value of a Figure 4.5: Sweep of both Af and Af1 in the novel topology, NMOS implementation 100101102103104105106107108 −40 −20 0 20 40 60 80 100 Frequency (Hz) Gain (dB) Af=0.90 Af=0.92 Af=0.94 Af=0.96 Af=0.98 Af=1.0 (a) Gain 100101102103104105106107108 0.94 0.96 0.98 1 1.02 1.04 1.06 Frequency (Hz) a Af=0.90 Af=0.92 Af=0.94 Af=0.96 Af=0.98 Af=1.0 (b) Value of a Figure 4.6: Sweep of Af in the novel topology keeping Af1=0.95, NMOS implementation 4.4 Design of the Operational Amplifier 57 100101102103104105106107108 −30 −20 −10 0 10 20 30 Frequency (Hz) Gain (dB) Af1=0.90 Af1=0.92 Af1=0.94 Af1=0.96 Af1=0.98 Af1=1.0 (a) Gain 100101102103104105106107108 0.88 0.9 0.92 0.94 0.96 0.98 1 1.02 1.04 1.06 1.08 Frequency (Hz) a Af1=0.90 Af1=0.92 Af1=0.94 Af1=0.96 Af1=0.98 Af1=1.0 (b) Value of a Figure 4.7: Sweep of Af1 in the novel topology keeping Af=0.95, NMOS implementation From these results five major conclusions, regarding this topology can be taken: •The value of awill go above one if A f 1>A f ,gm3=gm4and gds3=gds4. This is undesirable because a negative resistance will be introduced in the system, causing stability issues. •The value of Af has more impact in the voltage gain of the topology than that of Af1, because having Af1 higher than Af does not increase gain, but A f >A f 1 does. An effect justified by the fact that Af influences both the factor aand the voltage gain directly while Af1 only affects gain because of its effect in the value of the factor a. •The closer Af and Af1 are to one with A f ≥A f 1 the higher the voltage gain obtained. •If Af=Af1=1 the load impedance will be equal to that of a complementary cascode load, demonstrated in section A.1.3 of appendix A, and the topology presents approximately a square of the intrinsic gain of the driver transistor. •The expressions deduced for the topology are in agreement with the results obtained in simulation. The same analysis was made with the a-GIZO TFT model and the same conclusions are observed. The simulation results of these simulations are depicted in figures 4.8, 4.9 and 4.10. The biasing conditions and aspect ratios of the transistors used in these simulations can be consulted in section A.2.1 of appendix A. Although they seem identical there is a difference between the behaviour of the topology in a-GIZO TFTs and NMOS. Comparing the gain results for the sweep of both the gain factors for NMOS and a-GIZO presented in figures 4.5a and 4.8a, respectively, there is major difference in the ratio between the gain obtained when Af=Af1=1 and Af=Af1=0.9 for both topologies. For NMOS this ratio is 87.51dB while for a-GIZO it is only 32.06dB. This result implies that the voltage gain 58 Development of the a-GIZO TFT Operational Amplifier 100101102103104105106107 −20 −10 0 10 20 30 40 50 60 Frequency (Hz) Gain (dB) Af=0.90 Af=0.92 Af=0.94 Af=0.96 Af=0.98 Af=1.0 (a) Gain 100101102103104105106107 0.9 0.91 0.92 0.93 0.94 0.95 0.96 0.97 0.98 0.99 1 Frequency (Hz) a Af=0.90 Af=0.92 Af=0.94 Af=0.96 Af=0.98 Af=1.0 (b) Value of a Figure 4.8: Sweep of both Af and Af1 in the novel topology, a-GIZO TFT implementation 100101102103104105106107 −20 −10 0 10 20 30 40 50 Frequency (Hz) Gain (dB) Af=0.90 Af=0.92 Af=0.94 Af=0.96 Af=0.98 Af=1.0 (a) Gain 100101102103104105106107 0.9 0.92 0.94 0.96 0.98 1 1.02 Frequency (Hz) a Af=0.90 Af=0.92 Af=0.94 Af=0.96 Af=0.98 Af=1.0 (b) Value of a Figure 4.9: Sweep of Af in the novel topology keeping Af1=0.95, a-GIZO TFT implementation 100101102103104105106107 −15 −10 −5 0 5 10 15 20 25 30 Frequency (Hz) Gain (dB) Af1=0.90 Af1=0.92 Af1=0.94 Af1=0.96 Af1=0.98 Af1=1.0 (a) Gain 100101102103104105106107 0.85 0.9 0.95 1 1.05 Frequency (Hz) a Af1=0.90 Af1=0.92 Af1=0.94 Af1=0.96 Af1=0.98 Af1=1.0 (b) Value of a Figure 4.10: Sweep of Af1 in the novel topology keeping Af=0.95, a-GIZO TFT implementation 4.4 Design of the Operational Amplifier 59 of this topology drops more in NMOS than in a-GIZO with relation to how below 1 is the gain in the feedback networks. The major cause for such result resides on the difference in gm/gds ratio between the two technologies. Recalling that for a-GIZO TFTs the mobility of carries in the channel is several orders of magnitude lower than that of the one obtained in typical NMOS transistors, we already expected that the gm values for the former devices would be significantly lower than the ones of the latter, as would the ratio between gm and gds. Knowing that this ratio represents the difference in magnitude between the values of ro=1/gds and 1/gm and that rois in parallel with 1/(gm(1−A f )) it becomes evident that even for a feedback factor slightly inferior to one, like for example 0.98, the bigger the value of gm in relation to gds the more dominant 1/(gm(1−A f )) will be in the value of the parallel resistance. Consequently, the impedance of the load will be lower as will be the voltage gain. For this reason the proposed topology presents a superior performance in TFT technologies because they possess lower carrier mobility than common silicon based technologies. This finding is very important because a-GIZO TFT is not yet a fully developed technology, therefore, the mismatches expected during fabrication will be superior to those obtained in circuits fabricated in commercial semiconductor technologies. This obliges the designer to give a security margin and therefore not implement the gain very close to unity in the feedback, because the value of this gain in the real circuits can be found to be above one causing stability issues. So, if there was a similar variation of the load impedance when Af is going below one as the one verified for NMOS, the use for this topology would be very limited because the voltage gain would be tremendously reduced when compared to the one that could be theoretically achieved if the gain of both the feedback networks was exactly unitary. In TFTs the reduction in gain will be also verified under the same conditions but it will not be as significant. Also, as the fabrication processes evolves and becomes more accurate there will be the possibility of aiming for values of Af that are very close to unity. To verify that the formulas presented for the gain of the topology were valid, the results obtained for the factor aand for voltage gain when Af=Af1=0.9 and Af=Af1=1 were compared to results calculated with the formulas represented in 4.10. The values gm and gds, which were made the same for every transistor in these simulations, are presented in table 4.1. Comparing the values obtained in simulation, table 4.2, with those calculated through the formulas it can be verified that the expressions can accurately estimate the values of aand of the voltage gain, Aol. Furthermore the gain values measured with Af=Af1=1 are approximately given by 0.5.(gm.(1/gds))2. This expression represents the equivalent gain obtained by a topology presenting a cascode in the drive with n-type transistors and a cascode with complementary devices as the load, assuming that between all transistors both gm and gds era equal. Therefore the topology can theoretically give the same gain as a cascode topology implemented with complementary type transistors. 60 Development of the a-GIZO TFT Operational Amplifier Table 4.1: Transconductance values of the transistors used in the simulations Technology gm (µA/V) gds (nA/V) 0.35µmNMOS 520.90 756.6 a-GIZO TFT 14.41 534.1 Table 4.2: Values of the factor aand of Aol measured in simulation Technology ameasured (mV/V) Aolmeasured (Af=Af1=0.9) (V/V) Aolmeasured (Af=Af1=1) (V/V) 0.35µmNMOS 998.55 -9.985 -237.417k a-GIZO TFT 965.49 -9.414 -377.380 Table 4.3: Values of the factor aand of Aol calculated with the formulas in 4.10 Technology acalculated (mV/V) Aolcalculated (Af=Af1=0.9) (V/V) Aolcalculated (Af=Af1=1) (V/V) 0.35µmNMOS 998.55 -9.985 -237.343k a-GIZO TFT 965.49 -9.414 -377.449 Going back to the differential configuration of the positive feedback networks, it was found that this configuration not only allows the use of less transistors in the system but it also introduces an interesting characteristic regarding common-mode signals. In figure 4.11 a cascade cross-coupled load, also referred as gm cancellation load, implemented with p-type transistors is represented. This type of configuration is used as a complementary active load for differential amplifiers in CMOS, as for example in the switched opamp in [11], because it has a impedance for differential signals that is different from its impedance for common-mode signals, which are calculated by Rloaddi f f =1 2(gm3.ro3.ro4+ro3+ro4)(4.11a) RloadCM =1 2.gm4 1 1−ro3−1/gm4 gm3.ro3.ro4+ro3+ro4 (4.11b) Vdd Vb Vb Vb Vb M3 M3 M4 M4 M3 M3 M4 M4 2.Rload Figure 4.11: Cross-coupled load with p-type transistors 4.4 Design of the Operational Amplifier 61 So, for the cross-coupled load the differential impedance is much higher than the one presented for common-mode, which if gm3.ro3.ro4+ro3+ro4ro3−1/gm4can be approximated as 0.5/gm4. Interestingly the novel topology presents a very similar effect to that of a cross-coupled load due to the differential feedback networks. To arrive at this conclusion consider again the representation of the topology in 4.2b. Since the feedback is implemented using the signal in the other half of the differential pair, positive feedback will be implemented in the case of differential signals. On the other hand for common-mode signals the feedback factors will be negative because the signals in each side of the differential pair are now in phase. Recalling the equivalent single stage model of the topology 4.4a, its equation for load impedance presented in 4.9 and considering the ideal case in which the module of the voltage gain in both feedback networks is exactly one, the load impedances for differential and common-mode signals are respectively given by Rloaddi f f =gm4.ro3.ro4+ro3+ro4(4.12a) RloadCM =ro3 2 1 1−(ro4+ro3/2−gm3.ro3(gm4.ro3.ro4+ro3) gm4.ro3.ro4+ro3+ro4)(4.12b) The differential impedance is considerably high and equal to the one obtained if a cascode configuration with complementary type transistors would be used. The common-mode impedance will be considerably lower than the differential one, although it may appear so at first glance. In fact considering that the term gm3.gm4.r2 o3.ro4(−ro4+ro3(1/2−gm3.ro3)and that gm3ro31, the impedance for common-mode signals can be re-written as RloadCM =1 2.gm3 (4.13) The deduction of the 3 equations presented above is detailed in section A.1.3 of appendix A. The above equations imply that the proposed load topology should operate in a way similar to that of a cascade cross-couple load in complementary devices. Since the value of the load resistance, for differential signals, could already be verified when both of the feedback factors were made equal to 1, figures 4.5a and 4.8a, the same analysis was performed executing a sweep from -1 to -0.9 in both the feedback factors. This simulation was performed for NMOS and in the same conditions of the previous analysis, and the obtained results are presented in figure 4.12. Analysing the results, the effect of having a common-mode resistance equal to 1/(2.gm3)is verified because the gain for Af=Af1=-1 is -6dB, which corresponds to the expected result considering that all the transistors in the topology have the same gm and gds. From this result it is possible to demonstrate that this topology will offer high rejection for common-mode signals, especially when the |Af| and |Af1| are made close to one, because there is not much alteration of the common-mode gain when these values are below one but, on the other hand, there is a considerable drop in the differential gain of the configuration. 62 Development of the a-GIZO TFT Operational Amplifier 100101102103104105106107 −20 −18 −16 −14 −12 −10 −8 −6 −4 −2 0 Frequency (Hz) Gain (dB) Af=−1 Af=−0.98 Af=−0.96 Af=−0.94 Af=−0.92 Af=−0.90 Figure 4.12: Voltage gain of the novel topology when Af and Af1 are swept from -1 to -0.9, NMOS implementation After performing the detailed analysis of the novel topology, the comparative analysis between it and the other topologies previously reported in literature was performed. The objective of this comparison being the selection of which topology would be more appropriate for the input stage. To perform the analysis under the same conditions in all of the topologies this comparative study was performed using the same biasing conditions except for those transistors in the feedback loops. The results obtained from simulations of the various circuits implemented in 0.35µm NMOS process are displayed in figure 4.13, while the results obtained using the a-GIZO TFT model are presented in figure 4.14. The information on the aspect ratios and biasing conditions used for each circuit is presented in A.2.2 of appendix A. In all these simulations the gain of the feedback networks is made lower than one. The topologies here analysed are the ones presented in figures 4.1 and 4.2. In this graphic and in following results the topology in figure 4.2a is designated as Amp1, the one in figure 4.1a is Amp2, and the ones in figures 4.2b and 4.1b are, respectively, Amp3 and Amp4. The first notable finding in these results is that both technologies (NMOS and a-GIZO) are in agreement except for the response of the topologies with capacitive bootstrapping. This difference is due to the fact that there is slight voltage drop in the biasing transistors for the active loads of the ac bootstrap topologies in a-GIZO. This makes the load transistors in the cascode have considerably different rovalues, even for a difference of a few mV between the VDS of both of them. Analysing the results only in terms of voltage gain it is found that the topology using cascade capacitive bootstrap is the one that gives higher gain, which means that it is also the one where the load impedance is higher. Also, between both of the topologies using capacitive bootstrapping, the one with the cascade structure presents approximately 6dB more of gain in the NMOS implementation, a result that is expected considering that the cascade load presents an impedance that is much higher than that of the single load. This happens because for the single bootstrapped load 4.4 Design of the Operational Amplifier 63 100101102103104105106107 −20 −10 0 10 20 30 40 50 60 Frequency (Hz) Gain (dB) Amp1 Amp2 Amp3 Amp4 Figure 4.13: Simulation results of high-gain single-stage differential amplifiers with only n-type enhancement transistors, NMOS implementations 100101102103104105106107 −25 −20 −15 −10 −5 0 5 10 15 20 25 Frequency (Hz) Gain (dB) Amp1 Amp2 Amp3 Amp4 Figure 4.14: Simulation results of high-gain single-stage differential amplifiers with only n-type enhancement transistors, a-GIZO TFT implementations the impedance will be approximately equal to roof the load transistor, while for the cascade structure it will be approximately gm.r2 o+2.ro. Therefore, in the case of the single bootstrapped load the gain will be approximately 0.5.gm.rowhile in cascade structure with bootstrapping it will be gm.roas the output resistance of the driver transistor is much lower than the load impedance. The same 6dB difference in gain between the ac bootstrapping topologies is not verified in a-GIZO because the rofor the transistor at the top of the cascode load was lower than that of transistor in the bottom of the cascode load. Nonetheless, the cascode load with capacitive bootstrapping still exhibits a higher gain than that of the same configuration with a single load transistor. The other two topologies give less voltage gain than the ones using capacitive bootstrapping because the feedback factors were kept below 1 with inferior values than those obtained with capacitive bootstrapping. Comparing both topologies it is possible to verify that the novel topology has an 64 Development of the a-GIZO TFT Operational Amplifier increased gain when both configurations have the same value for the feedback factor Af. Unlike the previous case there is no 6dB difference between the gain obtained with the cascade and single loads which is justified by the fact that for the cascade structure Af1 is also lower than 1. If the comparison is realized only considering bandwidth clearly the capacitive bootstrapped topologies are superior, and the novel topology is the worse of the topologies because extra capacitive loading is added to the output node. Still, it is also necessary to take into account that the capacitive bootstrapped topologies cannot amplify dc while the others can. A relevant factor if the opamp is intended for generic purpose. Finally, if power consumption is taken into account the capacitive bootstrapped topologies are also going to be superior because the feedback networks of the other topologies require extra current for biasing. Also, the novel topology will again be the inferior one in this category because it requires not one but two feedback networks and it also has the biggest number of transistors among the topologies analysed. Table 4.4 shows the results obtained for each topology using NMOS. Table 4.5 presents the comparative analysis of the topologies in terms of the number of components that are necessary for their implementation. Table 4.4: Comparative analysis of the performance high-gain differential stages with n-type enhancement transistors in NMOS Topology Aol(A f =A f 1=1)Aolsim (dB) Bandwidth (kHz) Af Af1 Amp1 ≃0.5.gm.ro42.57 25.64 0.9955 - Amp2 ≃0.5.gm.ro47.64 959.50 0.9988 - Amp3 ≃gm.ro44.45 13.95 0.9955 0.9909 Amp4 ≃gm.ro53.72 616.76 0.9994 0.9983 Table 4.5: Number of components necessary to implement each of the high-gain stages only with n-type enhancement transistors analysed Topology No. transistors No. capacitors Amp1 10 0 Amp2 7 2 Amp3 17 0 Amp4 11 4 After concluding this comparative analysis a decision on the input stage for the opamp had to be made and the decision fell on the novel topology developed. However, the drive of the circuit was altered to a cascode configuration, as represented in figure 4.15, to further increase the voltage gain and at the same time reduce the input capacitance of the opamp. The factors behind this decision were the following: •The possibility of amplifying dc makes the opamp also suited for generic applications. 4.4 Design of the Operational Amplifier 65 •In terms of maximum voltage gain the novel topology is inferior to the ones using capacitive bootstrapping. However, unlike these topologies the one selected does not require the use of extra capacitors, which would increase the overall circuit area considerably. •The behaviour of the novel topologies for common-mode signals makes it so that the rejection of common-mode disturbances in the input stage is significant even when the differential gain has a moderate magnitude. A characteristic not presented in capacitive bootstrapped topologies because the feedback of the output signal to the gate of the load transistors is not differential. Still, there are also some drawbacks associated with the selection of this topology. For example, without using significantly wide transistors for the drive it would be very difficult to achieve a voltage gain close to 60dB with only this stage, especially because a margin has to be given in the feedback factors of the active load to ensure that after fabrication the opamp does not turn out to be unstable. So, avoiding very wide transistors and restricting the aspect ratios of the transistors to the ones that the model is able to simulate, W/L from 40/20µmto 320/20µm, more stages were ultimately necessary in order to increase the overall gain. Other handicaps such as the number of transistors and increase power consumption were considered not significant, because of the limitations in the implementation of high-gain stages in this technology and of the lower currents of a-GIZO TFTs when compared to those of typical silicon based transistors. Vdd M1 M2 VbcascVbcasc M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 Vb2 Vb2 Vb1 VoutVout+ Vin+ VinVb3 M17 M18 M19 Figure 4.15: Input stage of the proposed opamp 72 Development of the a-GIZO TFT Operational Amplifier proximately 150kΩ. In fact, the capacitance value used for C2should have been bigger to increase the gain of the CM loop but since settling and bandwidth must also taken into consideration the trade-off between these characteristics and the gain for the CMFB loop was made. 4.5 Complete Operational Amplifier Topology After the definition of the third and fourth stages and of the CMFB network, the presentation of the core opamp topology is finished. A schematic of the topology before the application of frequency compensation can be seen in figure 4.19 and the aspect ratios of the transistors used in simulation along with the bias voltages are presented in tables 4.6 and 4.7. In terms of aspect ratios note that in the input stage transistors M1 and M2 are made wider in order to increase the voltage gain at this stage. Theses transistors will have a lower VGS than that of the other transistors of this stage where VGS is approximately 3V, which corresponds to about 2.Vth, since Vth for these devices is estimated between 1.5 and 1.6V. This is the same approach used in the OTFT opamp proposed in [7] where the overdrive voltage (VGS −Vth) of all transistors in the input stage are high to account for the shift in Vth overtime but the input transistors of the first stage are biased with lower VGS to increase their gm/iDS ratio and, therefore, increase the gain of the stage. As in this previous work a CMFB network is also used to partially compensate the Vth effect making possible the use of transistors with lower overdrive voltages at the input of the opamp. In terms of the choices for aspect ratios in the other gain stages an emphasis must be given to the first common-source gain stage load transistors. They were made bigger (80µm), thus decreasing the gain of this stage. This choice was made, again, so that none of the transistors would exceed a VGS of 7V. The driver transistor has a width of 320µm, which is the widest TFT supported by the simulation model, to maximize gain. At the output stage TFTs present a width of 320µmin order to decrease the output impedance of the opamp, as much as possible. Regarding the feedback amplifiers used to increase the load impedance in the first stage there must be great care during design so that the gain in any of these amplifiers does not exceed a magnitude of one, in order to avoid negative resistance values. Considering that each differential amplifier that constitutes the feedback network for the active loads is balanced, Af and Af1 can be determined as A f =gm9 gm11 +gds9+gds11 (4.22a) A f 1=gm13 gm15 +gds13 +gds15 (4.22b) Therefore to avoid that neither Af and Af1 go above one, gm9must be lower than gm11 and gm13 as to be lower than gm15. This was accomplished by making M11 and M15 wider than, respectively, M9 and M13 in such a way that the gm for the load transistors would be superior, as gm is proportional to the width of a transistor, equation 2.10. Also, to avoid that any of the transistors would be in the limier of saturation a Vdd of 20V was used in order to have some margin for the 4.5 Complete Operational Amplifier Topology 73 VGS of the input transistors to increase due to the effect of the common-mode feedback network, as a compensation method for the increase of Vth. In the schematic presented the biasing networks that produce the various reference voltages for the opamp are not represented as all of the bias voltages were kept external. In this way adjustments can be to the biasing voltages during circuit testing, if so is required. Vdd Vb2 Vb3 M1 M2 M3 M4 A BB A D D C Vb3 M5 M6 Vb1 Vbcas Vbcas M7 M8 M9 M10 M11 M12 M13 M14 M16M15 M17 M18 C M19 M20 M21 M22 M23 M24 M25 M26 M27 M28 M29 M30 M31 M32 M33 M34 M35 M36 M37 M38 M39 Vout+ VoutVcmfb Vin+ VinFigure 4.19: Schematic of the proposed opamp without frequency compensation From figure 4.19 an approximation for the open loop gain of the topology, considering that (1/gm)||ro≃rocan be determined by Ad=−gm1.((gm1.ro1.ro3+ro1+ro3)||Rload).gm17.(ro38 +1 gm19 ) 1+gm17.(ro38 +1 gm19 ).3.gm21 gm25 .2.gm29 gm31 (4.23) Rload and the value of the factor a, which is necessary for its determination are calculated through the expressions in 4.24, while Af and Af1 are calculated from 4.22. 74 Development of the a-GIZO TFT Operational Amplifier Rload =ro5 1−a−gm5.(A f −1).ro5 (4.24a) a=gm7.A f 1−gm5.A f +gm5+gds5 gm7+gds5+gds7 (4.24b) This topology is intended for Vdd/2=10V as the common-mode level at the input and output. In terms of CM range, the input minimum and maximum voltage levels can be calculated as Vcmin,min =VGS1,2+VDS35,sat (4.25a) Vcmin,max =Vdd −VDS7,8−VDS5,6−VDS3,4+Vth1,2,(4.25b) where VDS35,sat is the minimum drain to source voltage for which transistor M35 is in still saturation. Analysing the output swing, the maximum value is determined when the VGS of both the diode connected transistors that compose the load of the output stage is equal to Vth. On the other hand, the minimum output level corresponds to the situation in which the drive transistor of the output stage is at the limit of saturation. To determine this voltage one must find the maximum VGS for which the transistor is still in saturation, which considering that all the transistors in the output stage have the same aspect ratio and therefore the same VGS, can be determine by the following set of equations Vdd −2.VGS29 ≥VGS29 −Vth29 (4.26a) ⇔VGS29 ≤Vdd +Vth 3(4.26b) VGS29,max =Vdd +Vth 3(4.26c) Finally, Vout,min is caculated as: Vout,min =V dd −2.VGS29,max (4.26d) Vout,max =V dd −2.Vth (4.27) These equations prove that, as expected, the necessity of using two diode connected loads to avoid VGS values superior to 7V, leads to a reduction of the output swing of the topology as both the maximum and minimum voltage levels of the output are reduce when compared to the case of using only one diode connected load. 4.5 Complete Operational Amplifier Topology 75 Table 4.6: Aspect ratios of the transistors Transistor(s) Aspect Ratio(µm/µm) M1,M2,M21,M22,M29,M30,M31,M32,M33,M34 320/20 M3,M4,M5,M6,M7,M8,M11,M12,M15,M16 160/20 M9,M10,M13,M14 90/20 M17,M18,M19,M20,M38,M39 40/20 M23,M24,M25,M26,M27,M28 80/20 Table 4.7: Bias Voltages of the opamp Designation Value(V) Vdd 20.00 Vb1 17.50 Vb2 4.81 Vb3 2.50 Vbcas 13.00 Vbias 3.00 Vcmref 10.00 4.5.1 Frequency Compensation As a multi-stage topology the opamp was at first unstable and therefore required the use of a frequency compensation scheme. However, the compensation of this topology proved to be a complicated task especially due to the source-follower in the second stage. The first frequency compensation scheme applied was a cascode compensation [41] between the nodes highlighted as A and D in figure 4.19. This type of compensation is extensively used in amplifiers using a two-stage configuration that have a cascode in the input stage. The proposed opamp topology for this work is, however, different from those in which this scheme is usually employed, not so much because of the number of stages but because of the source-follower that is connected to the output of the first stage. In fact it is this source-follower that makes it impossible to use this frequency compensation scheme, as pole-zero analysis performed in simulation reported the presence of a right-half plane pole when it was used. After some theoretical analysis, the cause for this unexpected pole was found to be related to the input impedance of the source-follower stage. This impedance can be determined using the simplified schematic for the second stage of the opamp presented in figure 4.20. Using the small-signal equivalent for the transistor the input impedance of this stage is found to be Zin =1 CGS.S+(1+gm CGS.S).(RL RL.CL.S+1)(4.28) 76 Development of the a-GIZO TFT Operational Amplifier Vdd Vin_sf Vout_sf M1 Ix CGS CL RL Figure 4.20: Schematic for the calculation of the input impedance of a source-follower stage Focusing of the term representative of the equivalent load impedance, RL/(RL.CL.S+1), it is clear that as the frequency increases at some point |RL.CL.S+1|1 and the previous term will then simplify to 1/CL.S. Equation 4.28 is then rewritten as Zin =1 CGS.S+1 CL.S+( gm CGS.CL.S2)(4.29) Now if in this last equation s=jω, the impedance will present a negative real part equal to Re(Zin) = −gm CGS.CLω2(4.30) It is this negative resistance that originates the right-half plane pole, because at certain frequencies the resistance presented above will be dominant in node B and the voltage gain across the compensation capacitor would then be positive instead of negative. This situation had not been previously reported for this compensation scheme because it usually applied to two stage opamps in complementary type transistors where the second stage is always a common-source stage. After finding out that cascode compensation was not possible for the proposed topology the compensation of the topology was further analysed in order to come up with a new compensation scheme. The first step of this analysis was to determine in frequency what would be the relative position between all of the main poles of the topology from the analysis of the time constant associated to each node. From this analysis it was found that the dominant and the first nondominant poles of the topology before compensation are the ones associated with nodes B and C, which are the nodes with the highest impedance. The third pole is associated with node D and the fourth with the output node of the topology. The expressions for the calculation of the time constants associated to the nodes of the opamp are presented in section A.3.1 of appendix A. This finding led to the following conclusion, if Miller compensation is attempted by connecting a capacitance between nodes B and D only dominant pole compensation will be possible. This is so because such a compensation scheme would lower the frequency of the pole associated with node B due to the Miller multiplication of the compensation capacitor but the pole splitting effect would be carried out for a pole that is not the first non-dominant pole of the system. If this 4.5 Complete Operational Amplifier Topology 77 topology was used, the opamp would have very low bandwidth because the dominant pole would have to be placed very close to the origin in order for the system to have a phase margin higher than 60o. Since the initial bandwidth before frequency compensation is already not that high due to large parasitic capacitances in a-GIZO TFTs, if the compensation is performed in this way a bandwidth of a couple tens of hertz would be achieved. Ultimately two compensation schemes were used in an approach that was based in the opamp proposed by Young in [3] which from all of the topologies with only n-type enhancement transistors might be the one that is most similar to the one proposed, as it also utilizes a source-follower stage to perform level-shifting. In the compensation scheme used, Miller multiplication was implemented by connecting a compensation capacitor between nodes C and D in order to set the dominant pole of the opamp at node C which has the second highest impedance of the topology, while moving the pole associated node D to higher frequencies. To deal with the right-half plane zero introduced by the feedforward path implemented by the compensation capacitor, a resistance is introduced in series with it in order to move this zero to the left-half plane so as to cancel one of the non-dominant poles of the system. In this case the frequency of the zero will be approximately given by ωz=1 Cc(1 gm21 −Rc),(4.31) where Rzis the resistance in series with the compensation capacitor. This resistance is implemented through a transistor in triode region considering that Ron =1/(µn.Cox.(W/L).(VGS −Vth)). Because the pole at the output node of the input stage is placed in low frequencies and cannot be moved away from the origin, a bypass capacitor was introduced in the source follower. This capacitance will lower the frequency of the left-half plane zero associated with the source follower and will allow the compensation of the opamp with an appropriate phase margin if this zero is placed below the unity gain frequency in order to inject phase in the system. To verify the effect of the bypass capacitor on the source follower consider again figure 4.20. The capacitance CGS provides a feedforward path for the signal at the gate of M1, and since the gain across this capacitance is positive a left half-plane zero at the frequency ωz=gm1/CGS will be originated. By adding capacitance Cbin parallel with Cgs this zero will be shift towards a lower frequency, ωz=gm1/(CGS +Cb). This zero could also be used to cancel the non-dominant pole of the system but in that case the bypass capacitor would have to be considerably big. When compared to the results obtained if the compensation was realized by connecting the compensation capacitor between nodes B and C, the compensation scheme used allows for higher bandwidth and the use of lower values in the compensation capacitor. Still, the method used also has some disadvantages, the first being the necessity of using two extra compensation capacitors. However, the major drawback is related to the fact that the poles associated with the sourcefollower become complex conjugate instead of two different real poles. This means that even with the circuit presenting an appropriate phase margin there will be some overshoot in the opamp’s step response [42, p. 190]. The poles of the source-follower become complex conjugate because 78 Development of the a-GIZO TFT Operational Amplifier of the values of its input and output impedances, which are conditioned by the compensation capacitors and by the capacitive loading introduced in the input of the source-follower stage as a result of the two feedback networks used to increase the load impedance of the first stage. The final schematic for the topology after the compensation scheme is added is presented in figure 4.21. The values of the components used for frequency compensation are •CC=120pF •Cb=25pF •Rc=200kΩ Vdd Vb2 Vb3 M1 M2 M3 M4 A BB A DD C Vb3 M5 M6 Vb1 Vbcas Vbcas M7 M8 M9 M10 M11 M12 M13 M14 M16M15 M17 M18 C M19 M20 M21 M22 M23 M24 M25 M26 M27 M28 M29 M30 M31 M32 M33 M34 M35 M36 M37 M38 M39 Vout+ VoutM40 M41 Vbr Vbr CC CC Cb Cb Vin+ VinSC-CMFB Vcmfb Vbias Vdd/2 Vbias Vcmref VoutVout+ Figure 4.21: Complete schematic of the proposed opamp These values were reached after an iterative process carried out during simulations and they are designed for a 100pF load capacitance. This value of load capacitance was select because this capacitance is required to be much higher than the extra capacitive loading introduced by the CMFB network, which will have a minimum value equal to that of C2which was defined as 5pF. The iterative process started with the definition of a value of CC=100pF which is equal to that of the load capacitance. Then Rzwas selected such that the zero introduced by CC would be 4.6 Simulation Results 79 moved to a frequency close to that of the third pole of the system, which is the one associated with node D. After this the value of Cbwas adjusted so that the opamp would present a phase margin of 45o, followed by a final tuning of the values of CC and Rcin order to ensure a phase margin above 60o. Although the values presented above might seem to be considerably high, one should keep in mind that the values of transconductance for these transistors are in the order of tens of µA/Vand that due to their considerable dimensions they present parasitic capacitances in the order of some units of pF. Also, as there is no data regarding the accuracy of the values that were used for CGS and CGD in the simulations of the opamp, the values presented above are not guaranteed to work in the real circuit. They serve to validate the approach for the frequency compensation of the opamp, however, the components for frequency compensation of the fabricated circuit are expected to be of the same order of magnitude. The results obtained for NMOS are in agreement with the ones presented above which in good extent also validates the approach for frequency compensation of the topology. 4.6 Simulation Results The magnitude and phase of the open loop response of the opamp after frequency compensation are presented in figures 4.22a and 4.22b. In these results a left-half plane zero below the unity-gain frequency is clearly noticeable, as is its effect of increasing the phase of the system. This zero is the one associated with the source-follower, whose frequency was intentionally lowered through the use of a bypass capacitor. In table 4.8 the characteristics of the opamp that can be inferred from the simulated open-loop frequency response are presented. Table 4.8: Characteristics of the opamp’s open loop response Gain 57.26 dB Bandwidth 264.5 Hz Unity-gain frequency 17.81 kHz Phase Margin (100pF load) 68.83o In table 4.9 the small-signal gain of each of the amplifiers stages is presented. As before, the gain of the differential stages used to implement feedback in the active load of the first stage are represented as Af and Af1 and the third and fourth stages are designated as Common-Source 1 and Common-Source 2, respectively. 80 Development of the a-GIZO TFT Operational Amplifier 10−2 10−1 100101102103104105106107 −150 −100 −50 0 50 100 X: 1.738e+005 Y: −21.24 Frequency (Hz) Gain (dB) X: 0.01 Y: 57.26 X: 263 Y: 54.29 X: 1.82e+004 Y: −0.1875 (a) Magnitude 10−2 10−1 100101102103104105106107 −400 −350 −300 −250 −200 −150 −100 −50 0 50 X: 0.01 Y: −0.002738 Frequency (Hz) Phase (º) X: 1.738e+004 Y: −111.4 X: 1.738e+005 Y: −178.6 (b) Phase Figure 4.22: Frequency response of the a-GIZO TFT opamp Table 4.9: Small signal gain of each stage of the opamp Stage Gain (dB) Gain (V/V) Input Stage 33.020 44.7300 Af -0.240 0.9727 Af1 -0.149 0.9830 Source-follower -2.597 0.7416 Common-Source 1 20.140 10.1625 Common-Source 2 6.701 2.1630 Here it is seen that the biggest part of the overall voltage gain is achieved in the input stage, also as expected the source follower introduces some attenuation but the two gain stages that come after it compensates this loss in gain. Besides the analysis of the open-loop frequency response it is also important to analyse the performance of the opamp in terms of the rejection of common-mode signals, rejection of power supply noise and power consumption. The analysis of the common-mode rejection can be accomplished by applying the same signal to both of the opamp’s inputs and measuring the voltage gain 4.6 Simulation Results 81 for this case. Then the CMRR (Common-mode rejection ratio) can be determined by subtracting the obtained result to the differential gain of the opamp, with both gain values expressed in dB. The rejection of power supply noise can be determined by superimposing a signal to the power supply voltage while no signal is applied to the differential inputs of the opamp and then measuring the resulting voltage gain at the output. Then the PSRR (Power Supply Rejection ratio) is found as the difference between the differential gain, expressed in dB, and the gain of the signal applied in the power supply, also expressed in dB. The analysis of power consumption is fairly straight forward as it is directly obtained by the multiplication of Vdd with the total current in the opamp. Currents per stage of the opamp are displayed in table 4.10. From these results it can be seen that the highest current consumption derives from the output stage. This high current is due to wide transistors and to VGS values of 5V. To calculate the power consumption of the opamp all the currents must be added up, remembering that the source-flower and stages Common-Source 1 and Common-Source 2 must be accounted for twice since the opamp is fully-differential. Table 4.10: Current per stage in the proposed opamp Stage Current (µA) Input Stage 10.110 Af 5.465 Af1 5.473 Source-follower 5.558 Common-Source 1 15.010 Common-Source 2 49.490 Table 4.11 presents the results of all of the analysis mentioned above plus the analysis of input common-mode range, output swing and slew rate. Table 4.11: Characteristics of the opamp that are not determined directly from the analysis of the open-loop frequency response CMRR 90.35dB PSRR 75.60dB Supply Voltage 20V Total Current 161.16µA Power Consumed 3.223mW Input Common-mode range 3.6->10.5V (6.9V) Output swing 5V->16.8V (11.8V) Slew rate 0.03365V/µs The values for CMRR and PSRR are high especially taking into account that the differential gain is slightly inferior to 60dB. As for power consumption, it is low, as expected because of the low carrier mobility in the channel of a-GIZO TFTs. The total power consumption could be further reduced as there is margin to reduce supply voltage. Still, in technologies such as this one, biasing transistors with very low overdrive voltages should be avoided due to the increase in Vth as a result of constant bias stress. Also, even with a high supply voltage the proposed amplifier 88 Development of the a-GIZO TFT Operational Amplifier This chip must have a border of 0.2cm all around and alignment marks must be placed along the border, hence the reason for the cross-like marks that can be seen in the figure. 2.5cm 2.5cm 2.1cm 2.1cm 0.2cm Figure 4.28: Example of a chip for fabrication 4.7.2 Layouts Designed The layout of the the complete opamp is displayed in figure 4.29. In this layout there are no compensation components included and the CMFB network as also been left out. As there is no accurate idea on the capacitances values for C1 and C2, because they are dependent on the capacitances of the transistors in the biasing network, the CMFB loop has, therefore, been designed separately and also without any capacitors, instead there are pads that are connected to their respective nodes in order to allow their addition externally during testing. The layout of the CMFB network is presented in 4.30. In the developed layouts the topologies are made completely symmetrical except for the positive feedback networks of the first stage due to inter-crossings. In terms of the area occupied these layouts are relatively big if compared to a layout in current CMOS technologies. Still, the need for a considerable area stems from the necessity of having external connections for the addition of frequency compensation components. All of these interconnections require pads and each one of these pads has an area of 62500µm2(250 ×250µm2), and there should be sufficient spacing between them to allow wire bonding, therefore they are always spaced at least 250µm. Also, all of the pads are placed in the periphery of the circuits so that no internal short circuits are caused during the execution of wire bonding. Table 4.16: Layout areas Layout Area(mm2) OPAMP 14.375 SC-CMFB 10.000 4.7 Layout 89 5.75mm 2.5mm Figure 4.29: Layout of the proposed opamp 4mm 2.5mm Figure 4.30: Layout of the Common-mode feedback network In the layout here presented which corresponds to the final version of the circuits, the transistors are all drawn with direct layout. However, in the first layout produced all transistors presented a fingered structure and the input transistors of the differential stage were designed with an interdigitated configuration. The use of topologies with multiple fingers is commonly used in wide transistor to reduce the gate resistance as well as the total overlap capacitance between gate and 90 Development of the a-GIZO TFT Operational Amplifier source/drain. On the other hand the use of interdigitated structures is commonly used in the layout of differential amplifiers to minimize mismatch, which hinders the performance of analog circuits [27, p. 635]. Figure 4.31 displays a multifinger version of a transistor with a channel width of 320µmand channel length of 20µm. In figure 4.32 an interdigitated layout of two transistors, both with a width of 160µmand a length of 20µm, is represented, a dummy gate is also added in each side of the structure so that both the transistors have the same surrounding environment in order to increase the matching between them. In both configurations the size of each finger is that of the minimum size transistor available is this technology, which has a width of 40µmand a length of 20µm. 4.7.3 Problems when using multifinger structures for the fabricated a-GIZO TFTs The reason for not using interdigitated or multifinger structures in the final layouts is that measures that were carried out during the work on transistors constructed with fingered structure showed that they were behaving as depletion type. Figure 4.33 displays the square root of IDS in relation to VGS of two transistors with W/L=320/20µmboth with and without fingered structure. To preform this analysis both transistors were biased with a VDS of 14.5 V to ensure that when they are conducting they will always be in deep saturation, VGS is swept between 0 and 10V. For the transistor with the multifinger structure it can be seen that the threshold voltage will be below 0V, which is not the case for the one with the direct layout. The threshold voltage is estimated as the intersection of the tangent (represented in green) of characteristic with the x-axis. The reason for this effect has not been completely determined by the team working in the a-GIZO TFT project at FEUP but it is thought that it may be caused by the non-interruption of the semiconductor layer below the source drain overlaps of adjacent fingers. Still, has the developed work is focused only in n-type enhancement transistors and as there is not enough data regarding the performance of the multifinger structures, in the final versions of the layouts all of the transistors have been drawn with the direct layout. However, the first chip was done before these results were known and it has also been sent for fabrication. In either case, individual copies of each transistor used in the circuits have been place near each circuit in order to have an estimation of the behaviour of the transistors used by characterizing these replicas. Figure 4.31: Multifinger layout for an a-GIZO TFT with W/L=320/20µm 4.8 Summary 91 Figure 4.32: Interdigitated layout of two 160/20µma-GIZO TFTs 0 1 2 3 4 5 6 7 8 9 10 0 0.005 0.01 0.015 0.02 0.025 X: 0 Y: 0.0031 Vgs (V) sqrt(Ids) (a) Direct Layout 0 1 2 3 4 5 6 7 8 9 10 −5 0 5 10 15 20 x 10−3 X: 1.557 Y: 1.378e−005 Vgs (V) sqrt(Ids) (b) Multifinger Layout Figure 4.33: √IDS for various values of VGS for 320/20µma-GIZO TFTs with different layout structures, results obtained from physical circuits The layouts of individual stages of the the proposed opamp both with and without multifinger structures as well as the layouts for the other high-gain stages analysed in this chapter are presented in appendix C. The layouts of the other high-gain stages were drawn to preform the comparison of these topologies to the novel topology used in the input stage of the opamp. 4.8 Summary In this chapter the proposed a-GIZO TFT opamp was presented along with the constraints and the methodology associated with its design process. The proposed topology was analysed both theoretically and through the results obtained in simulation. Finally the produced layouts are presented and discussed. The proposed topology is a fully-differential 4-stage opamp implemented with only n-type enhancement transistors. This opamp is directed for application in switched capacitor circuits. As a unique characteristic it employs a novel topology in order to implement a cascode load in the input stage and increase the overall gain. In this way a considerable gain can be achieved without having to use very wide transistors or considerably big differences between the aspect ratios of the 92 Development of the a-GIZO TFT Operational Amplifier transistors used, as the ratio of the W/L between the biggest and smallest transistors used is only 8. This topology was presented, analysed and compared to other topologies that are used to increase the load impedance of gain stages in technologies possessing only a single type of transistor. Although the novel topology for high-gain has the highest power consumption and number of transistors between all of the topologies analysed, it is the one that assures the highest voltage gain while being able to amplify dc signals. However, the use of this topology requires a cascade structure at the input which lowers the input common-mode range and increases the required supply voltage. Another advantage of this novel topology, which is shared by all implementations that use differential feedback in the active load, is that it offers a high rejection of common-mode disturbances. This is characteristic stems from the topology presenting a lower impedance for common-mode than for differential signals. Due to its structure and the use of multiple stages the frequency compensation of the opamp is complex, especially because of the source follower stage. After compensating the opamp with a phase margin above 60o, the existence of low-frequency complex poles associated with the source follower leads to the presence of some overshoot in the closed-loop response of the amplifier. Since the a-GIZO TFT technology presents a shift in Vth overtime due to constant bias stress precautions have been taken to reduce this effect in the topology. Therefore, common-mode feedback was applied to the circuit and very low overdrive voltages were avoided. In terms of the produced layouts care was taken to ensure symmetry in order to increase matching but multifinger and interdigitated structures are avoided in the final versions of the circuits sent for fabrication. The results presented are all taken from measures performed in simulation. In simulations the parasitic capacitances of a-GIZO TFTs were approximated using the Meyer Capacitance Model in order to have a rough estimate on the frequency behaviour of the proposed topology. However, at this time there is no information regarding the accuracy of this model in the estimation of the intrinsic capacitances of a-GIZO TFTs, although it has been reported that for OTFTs the model provides a good approximation. In terms of potential fields of application the opamp proposed can be best suited for use in the domain of photovoltaic panels as the voltage levels in such applications tend to be superior than the supply voltage for which it was designed, 20V. Chapter 5 Switched Operational Amplifier with a-GIZO TFTs Based on the opamp topology presented in the previous chapter there was the idea of changing the biasing scheme so that it would be pulsed. This idea stemmed from results presented for digital a-GIZO TFT circuits, reporting increased circuit lifetime when the transistors would not be constantly on, but switched on and off [17]. Such a concept exists also for operational amplifiers in CMOS technologies which are designated as switched opamps. This concept, previously introduced in chapter 2.6.5 is used in switched capacitor circuits in which low-power consumption and low supply voltages are required. However, in this work this concept is adopted for a-GIZO TFTs in order to guarantee that none of the transistors of the opamp will be constantly biased during the operation of a switched capacitor circuit. In this way the effect of gate bias stress on the transistors is expected to be less significant. This chapter reports the steps involved in the design of a novel switched capacitor with only n-type a-GIZO TFTs. In it the major advantages and limitations of the topology are presented. Also presented are the results obtained in simulation for both this novel topology and a sample-and-hold circuit that was implemented with it. This sample-and-hold circuit is based upon the topology proposed in [11]. As for the previous operational amplifier, for the switched opamp a preliminary set of performance goals was defined to serve as guideline during design. The methodology used was exactly the same as in the design of the previous topology, which is detailed in 4.1. 5.1 Performance Goals The first consideration that must be taken into account is that unlike the switched opamps in CMOS the main objective of making the a-GIZO TFT opamp switched is not to reduce power consumption or the supply voltage. Nonetheless, power consumption will always be reduced as a consequence of switching-off the amplifiers stages. The main purpose is to reduce the effect of bias stress while keeping the same dc gain that was verified in the non-switched version of the opamp. Still, there must also be concern with the maximum allowed switching speed for the 93 94 Switched Operational Amplifier with a-GIZO TFTs opamp, because in switched capacitor circuits using this type of amplifier the circuit is switched at the same frequency as the opamp. Also, in terms of techniques that can be used to increase switching speed, only switching-off the output stage is not an option. This is so because all of the a-GIZO TFTs in the circuit will suffer from gate bias stress if constantly biased. For this reason in this design the biasing of all the stages of the opamp have to be disconnected when the amplifier is switched-off. All things considered the set of goals that was defined maintained the goals of the opamp presented in the previous chapter 4.2 with a single extra addition: •Every transistor in the topology has to be cut-off (VGS =0) in one of the two clock phases. Although not set has a mandatory goal care was also taken to increase the switching speed. 5.2 Design of the Switched Operational Amplifier Topology The core of the proposed switched opamp is the novel topology presented in the previous chapter excluding the common-mode feedback network. This choice was made because the aforementioned topology had already been studied and showed interesting results in simulation. Therefore the work develop aimed at the adaptation of the previously proposed topology rather than designing another opamp topology completely from zero. The first step of this conversion process was the definition of a method to set the bias voltages for the stages of the amplifier to zero during the off phase. This was achieved by using pull-down transistors connected to the biasing networks of the stages. This approach is the same one taken in [8] and it is depicted in figure 5.1. The working principle of this topology is fairly straightforward. When clk is high, Vbias will have a value of some tens of mV due to the pull-down realized by transistor Mpd. This low voltage level when applied to the gate of a transistor will put it in cut-off. On the other hand, when clk is low Vbias will have the desired level to bias the transistor it is applied to because Mpd will act as a very high impedance. In terms of the clock signal the maximum voltage allowed for switches in this configuration is 7V in order to avoid damaging the transistor used as a switch. As the clock signal as a voltage level considerably lower than Vdd all of the pull-down switches were implemented with the biggest transistor that can be simulated by the model, W/L= 320/20µm, to guarantee that the bias voltages will be pulled as closed to 0V as possible during the off-phase of the opamp. Recalling the original topology, depicted in 4.21 it is easy to see that the approach explained above does not suffice to turn-off all of the transistors in the core of the amplifier. The commonsource stages would still be biased with VGS >0 even when the secondary bias voltages are set to zero because Vdd must remain applied to the circuit. Therefore, an additional mechanism must be used to cut-off all of the transistors in the common-source gain stages. The solution developed to solve this problem is depicted in figure 5.2. When Vbias is at the level that adequately biases the second stage clk1 will be high and clk2 will be low. In this way Vbias is applied to the gate M4 through S1 which is in triode and the common-source stage is adequately biased because S2, 5.2 Design of the Switched Operational Amplifier Topology 95 Vdd MbiasMpd clk Vbias Figure 5.1: Generic topology to implement a pulsed biasing scheme which is cut-off, acts as a high-impedance. On the other hand when Vbias is pulled to a level close to ground, the voltage at the source of M2 will be equal to the dc level of Vins f minus a slight drop in M1 and M2 because these are n-type transistors. If this voltage level was applied to the gate of M4 at least this transistor would still be conducting, which is undesired. Therefore when Vbias comes close to 0V clk1 will be low and clk2 will be high. In these circumstances both the stages will have all transistors cut-off but at the cost of using two switches. This switching scheme is also used between the third and fourth stages for the same reasons explained before. In this way all of the stages of the amplifier will be cut-off when the amplifier is switched off. Vdd clk1 clk2Vbias Vout_CS Vin_sf S1 S2 M1 M2 M3 M4 M5 M6 M7 Figure 5.2: Switch-off mechanism for the first common-source stage Already a considerable amount of switches are necessary to cut-off the transistors in the amplifier stages of the opamp, but extra switches are required to rail the output to Vdd when the amplifier is off. Setting the output to Vdd is not actually mandatory for a switched opamp, but it is common practice to either set Vdd or Gnd at the output when the amplifier is off in order to avoid constant offsets. In the case of the proposed topology, just switching-off the biasing for every stage does not impose Vdd at the output, but a level somewhat below this voltage. This happens because the active loads in the output stage are diode connected n-type transistors, therefore even when the drive transistor of this stage is cut-off there will still be a slight voltage drop across the active loads, although the output is still in a high impedance state. To solve this problem and set 96 Switched Operational Amplifier with a-GIZO TFTs Vdd at the output when the amplifier is off, additional switches were added in the output stage as depicted in 5.3. These switches short-circuit the gate and source terminals of each of the diode connected load transistors of this stage and thus the output will be set to Vdd. However, there is a drawback associated with this method, which is, clk3 will have to possess a high voltage level of at least Vdd +Vth or otherwise the topology will not work. This means that to have the complete system-on-chip a charge pump will be required to generate this clock. M1 M2 Vdd M3 Vin_cs2 Vout clk3 clk3 S1 S2 Figure 5.3: Schematic of the output stage of the switched opamp As the switching speed is very important for the performance of circuits with switched opamps additional mechanisms were added in order to decrease the time necessary to complete recovery from the off phase. This time represents how long it takes for the output of the opamp to go from Vdd to Vdd/2 after the biasing is switched-on for all the stages. The aforementioned voltage levels represent, respectively, the voltage level at the output when the amplifier is turned off and the common-mode voltage level at the output during regular operation. To improve the turn-on speed two techniques were used. The first one consisted in switchingoff the transistors in triode which are in series with the compensation capacitors (CC). This is accomplished by pulling close to zero the biasing voltage for these transistors during the off phase of the opamp in the exact same manner as illustrated in figure 5.1. In this way these compensation capacitors remain charged during the off time, therefore reducing the turn-on time [9]. The second technique used for this purpose consisted in altering the number of stages that are included in the CMFB loop. In the previous topology all of the stages of the opamp were included in this loop because of the shift in Vth. However, in this topology the output of the CMFB circuit is applied to the biasing transistors of the source follower rather than those of the input stage. This in turn will increase the speed of the CMFB circuit. Although the CMFB circuit could in fact be excluded since the pulsed biasing of the amplifier is expected to reduce the shift in Vth, it was kept because it is expected to further increase the lifetime of the circuit. The circuit used for the CMFB network had to be specifically adapted for the context of switched opamps, therefore the topology used was that proposed in [10], as it does not require the introduction of extra poles in the CM loop and can adapted to the a-GIZO opamp with only some minor modifications. A representation of the common-mode feedback circuit employed is presented in figure 5.4. Regarding the original topology only three modifications were made. The first one is the 5.2 Design of the Switched Operational Amplifier Topology 97 Vdd C2 C1 C3 C4 Vbias Mbias Vout+ Voutclk2 clk1 clk2 n1 n3 Vdd/4 S19 S20 S21 S22 S23 Vcmfb n2 clk2 clk1 Figure 5.4: CMFB circuit of the proposed switched opamp substitution of all the switches implemented with p-type transistors by n-type transistors, as complementary devices are not available is this technology. The second alteration is related with the relative sizes of capacitors. In the original circuit C1,C2and C3all had the same dimensions and therefore C3was connected to Vdd during the on phase of the opamp. This is not possible with the a-GIZO TFTs used because in the instant when clock would go high S20 would have a VGS value that would damaged the transistor as clk1 would necessarily have a high level above Vdd+Vth and node n1 is set to ground in the instant there is a rising-edge of clk1. Since in all the designs a VGS above 7 is avoided, instead of connecting C3to Vdd it is connected to Vdd/4 which for this topology is 5V. In this way not only can the high level for the clock at the gate of S20 be lower, but also there will be no damage in S20 as this switched can be operated by a clock with a high voltage level of 7V. However, changing the reference voltage from Vdd to Vdd/4 imposes that C3 must have a capacitance four times bigger than those of C1and C2, otherwise the circuit will not function properly. A drawback of increasing the size of C3in relation to that of C1and C2is the reduction of the inherent gain of the topology which is (C1+C2)/(C1+C2+C3). The final alteration preformed is the addition of a pull-down switch to the circuit that is used to precharge C4 during the off phase of the amplifier. In this way no transistor in the amplifier will be conducting in both clock phases. In terms of the clocks represented in figure 5.4 clk1 and clk2 have the same high voltage level but have opposite phases. Designating the high phase of clock clk1 which corresponds to the on as φ1and the high phase of clk2 in which the amplifier is off as φ2, the charge equations for each clock phase are given by Qφ1= (Vout+on −Vn2φ1).C1+(Vout−on −Vn2φ1).C2+(V dd 4−Vn2φ1).C3+(Vn2φ1−Vcm f b).C4 (5.1a) Qφ2= (Vout+o f f −0).C1+(Vout−o f f −0).C2+(0−0).C3+(0−Vbias).C4(5.1b) 104 Switched Operational Amplifier with a-GIZO TFTs 10−2 10−1 100101102103104105106107 −200 −150 −100 −50 0 50 100 X: 1.096e+005 Y: −19.16 Frequency (Hz) Gain (dB) X: 0.01 Y: 57.26 X: 1.445e+004 Y: 0.1578 (a) Magnitude 10−2 10−1 100101102103104105106107 −500 −450 −400 −350 −300 −250 −200 −150 −100 −50 0 X: 1.096e+005 Y: −179.7 Frequency (Hz) Phase (º) X: 1.445e+004 Y: −110.4 X: 0.01 Y: −0.004009 (b) Phase Figure 5.7: Frequency response of the switched opamp in a-GIZO TFT 0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0.045 0.05 0 5 10 15 20 25 30 X: 0.009134 Y: 20 Time (s) Voltage (V) X: 0.01202 Y: 10.37 Figure 5.8: Output voltage of the proposed switched opamp with no signal applied to the input at a switching frequency of 200Hz This graphic not only allows the measurement of the turn-on time but also to take an extra conclusion. The turn on time is measured between 20V and 10.368V because there is a constant offset in the common-mode voltage in the output when the amplifier is on, and this time is 912.65µs. This means that the output of the opamp takes a considerable amount of time to recover from the off mode but this time length cannot be compared to that of switched opamps in CMOS as there are many differences between this topology and the state of the art topologies with complementary devices and besides the technologies themselves are different. There are two main causes for this high turn-on time, the first one is the fact that all of the stages of the opamp are turned-off. The second reason is that the parasitic capacitances for a-GIZO TFTs are in the order of a few pF due to the relatively big dimensions of these transistors. The extra conclusion that can be taken from the verified results is related to the offset present in the common-mode level when the amplifier is 5.5 Simulation Results 105 on. This effect is caused by the small gain of the common-mode feedback loop. Still, since the amplifier is fully-differential the offset will be cancelled as it is constant and exactly the same for both outputs. The output of the CMFB circuit is represented in figure 5.9. In this signal it can be seen that there is an offset between the expected level, which is the level to which C4is precharged in the off period of the opamp, 4.81V, and the value at the output when the amplifier is turned-on, which is 4.697V. This difference is reflected in the constant offset verified in the common-mode level at the output of the opamp when it is turned-on. 0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0.045 0.05 −10 −5 0 5 10 15 X: 0.008919 Y: 4.81 Time (s) Voltage (V) X: 0.0165 Y: 4.697 Figure 5.9: Output signal of the CMFB circuit of the switched opamp Table 5.4 presents the main characteristics of the switched opamp. Table 5.4: Characteristics of the switched opamp Gain 57.26 dB Bandwidth 169.8 Hz Unity-gain frequency 14.749 kHz Phase Margin (100pF load) 69.8o CMRR 90.35dB PSRR 75.60dB Supply Voltage 20V Total Current 161.16µA Power Consumed 3.223mW Input Common-mode range 3.6->10.5V (6.9V) Output swing 5V->16.8V (11.8V) Turn-on time 912.65µs 5.5.2 S/H implemented with the switched Opamp The S/H circuit is to expected have a low maximum operating frequency as the operational amplifier takes 912.65µsto reach the expected common-mode voltage at the output. Therefore the 106 Switched Operational Amplifier with a-GIZO TFTs maximum frequency of operation for this circuit will be approximately: 1 2×912.65 ×10−6≈547.85Hz (5.5) This switching frequency corresponds to a maximum operation of about 273 Samples/s. This means that the circuit will only be suited for low frequency applications as the switching frequency itself is low. To analyse the operation of the sample and hold a differential sinusoidal signal with a frequency of 20Hz and an amplitude of 1V was applied to the inputs of the S/H circuit. To avoid aliasing and have a number of samples for period that would allow the shape of the sine wave to be clearly perceived at the output of the S/H, the circuit was simulated at a switching frequency of 200Hz. Presented in figure 5.10 are the input and output signals for one of the differential paths of the topology. Here the offset at the output is clearly visible as is the shape of the sine wave. Also verified, is that this topology does not function as a normal S/H circuit would, because the output voltage level is not held during the sampling phase, as the amplifier is disconnected and capacitors Ch are reset. 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 0 5 10 15 20 25 Time (s) Voltage (V) Vin+ SH−Vout+ Figure 5.10: Positive phase differential input and output signals of the S/H for a 20Hz sinusoidal signal with an amplitude of 1V, S/H operated at Fs=200Hz If the transient difference between the output signals is analysed and compared to the signal at the input it is verified that the constant offset is eliminated as illustrated in figure 5.11. 5.5 Simulation Results 107 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 −2 −1.5 −1 −0.5 0 0.5 1 1.5 2 Time (s) Voltage (V) Input Signal Differential signal at S/H output Figure 5.11: Differential signals at input and output of S/H circuit. S/H operated at Fs=200Hz To analyse the performance of the circuit further the power spectral density of the output signal from 0 to Fs/2, presented in figure 5.12, was analysed 0 10 20 30 40 50 60 70 80 90 100 0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02 X= 92 Y= 3.288e−005 Frequency (Hz) psd (V2/Hz) X= 68 Y= 1.54e−005 X= 44 Y= 0.0003361 X= 20 Y= 0.01995 Figure 5.12: Power sepctral density of the differential output signal of the S/H circuit. Fundamental frequency 20Hz. Using the power spectral density spectrum the analysis of Spurious-Free Dynamic Range (SFDR) and the Total Harmonic Distortion (THD) can be made. Both of these analysis characterize the dynamic behaviour of the S/H. SFDR is defined as the ratio between the power of the fundamental frequency and that of the of the peak spurious spectral content. This measure is taken over the entire Nyquist zone (dc to fs/2). THD on the other hand is a measurement of the harmonic distortion present in a signal and it is defined as the ratio between the of the power of the harmonics and that of the fundamental frequency. From the plot power spectral density plot presented in figure 5.12 these parameters were measured as: •SFDR= 35.472dB 108 Switched Operational Amplifier with a-GIZO TFTs •THD= -34.299dB These values do not include, however, the contributions from charge injection and clock feedthrough, for this reason the results obtained from real circuits are expected to be worse than the ones obtained in simulation. 5.6 Layout As in the case of the non-switched version of the opamp for the switched opamp stage-by-stage layouts were designed along with the layout of the complete topologies for the switched opamp and for the complete S/H circuit. For these circuits no layouts were designed with interdigitated or multifinger configurations, as the depletion type behaviour of these structures was already known when the layouts for these topologies were designed. The layout of the complete S/H circuit is presented in 5.13. As in the case of the previous layouts for the non-switched opamp, all the components used for compensation are not included because no accurate information regarding the characterization of the parasitic capacitances of aGIZO TFT is yet available. Therefore, all nodes where compensation capacitors and resistors need to be connected are linked to external pads to allow the compensation of the topology externally. For this opamp the CMFB circuit has also been designed separately and also without any capacitors, still, these can be added during circuit testing. The layout for the CMFB circuit is presented in figure 5.14. 8.75mm 3.25mm Figure 5.13: Layout of the complete S/H topology As symmetry is necessary in the design and because only the gate and source-drain layers could be used for signal routing, the circuit requires a considerable number of pads because as clocks used in two different corners of the circuit cannot be routed from one side to the other unless the circuit area would be further increased. In cases such as these it was decided to have 5.7 Summary 109 2.75mm 1.75mm Figure 5.14: Layout of the Common-mode feedback network of the switched opamp (SOCMFB) two pads for the same signal, one in each corner of the circuit, therefore avoiding long routing connections for the clock. In this way it is also ensured that the circuit is completely symmetric except for the stages that implement positive feedback in the active loads of the input stage. The area of each of the layouts displayed are presented in table 5.5. Table 5.5: Layout areas Layout Area(mm2) S/H 28.4375 SOCMFB 4.8125 The layouts of the individual stages of the amplifier are presented in appendix C. 5.7 Summary In this chapter a novel switched operational amplifier with only n-type enhancement transistors is presented. The proposed topology is adapted for the a-GIZO TFT technology that is fabricated at CENIMAT. This switched opamp uses the novel opamp presented in the previous chapter as its core and the transistors that constitute the switched opamp are conducting in only one of the two clock phases. The application of the switched opamp principle in the a-GIZO TFT technology is aimed at reducing the effects of the shift over time in the transistors threshold voltage due to constant biasing, as circuits with pulsed biasing in this technology have been reported to have reduced Vth shift [17]. The proposed switched opamp is used to implement a Sample-and-Hold Circuit based upon a topology proposed in [11]. The complete circuit has the drawback of possessing 7 different clocks and some of them requiring a voltage level above Vdd. The justifications for this high number of 110 Switched Operational Amplifier with a-GIZO TFTs clocks are the various limitations of the technology, namely the lack of complementary device and the impossibility of using a VGS above 7V. This circuit was successfully implemented in simulation without any of the transistors being on in both clock phases. Still, simulations results indicate that the circuit has a long turn-on time. This long turn-on time is a cause of high parasitic capacitances of the a-GIZO TFTs and the turning-off of the bias for all the stages of the opamp, when it is switched-off. The layouts for the proposed circuits are also presented and analysed. Chapter 6 Conclusions and Future Work This chapter presents and overview of all of the work developed in the Master Thesis, along with an analysis of the final state for each of the objectives that were set when the work started and the presentation of potential next steps for the work in the area of analog circuits in a-GIZO TFTs. 6.1 Summary of the work developed The main objective of this work was the development of an operational amplifier topology for a-GIZO TFTs. The topology would have to take into account the various limitations of the technology such as the lack of complementary device, low mobility of carriers in the channel and the shift over time of the threshold voltage of these transistors. In order to achieve this objective various phases were carried out. The work done and the conclusions arrived at in each phase are presented below. •The first phase of the work was a study of all the limitations associated with the a-GIZO TFT technology along with its characteristics. Knowing all the limitations that the technology possesses was instrumental in the development of the proposed opamp topologies because these limitations conditioned the design process considerably. •Secondly a study of previous work on the design of operational amplifiers with only n-type enhancement transistors was done to determine what circuit techniques had already been used in this specific context. This study served as the base for the elaboration of the core of the topologies proposed and from it a novel topology for a high-gain differential stage with only n-type enhancement transistors was developed. •Then a comparative study was realized between the novel topology developed and other high-gain topologies for technologies with only a single type of transistor. In this study not only was the behaviour of the proposed topology extensively analysed but it was also concluded that this topology was going to be used as the input stage of the operational amplifier. This choice was made because the novel topology allows the highest voltage gain between all of the topologies with only a single type of transistor that can also amplify dc 111 112 Conclusions and Future Work signals. The ability to amplify dc signals is important because it makes the opamp suitable for a wider set of applications. Also, with this topology a significant gain can be achieved without using extremely high W/L for the transistors and without using transistors for the drive that are much wider than those used as loads in gain stages. •After this the rest of the stages of the amplifier were designed in order to further increase the overall open-loop gain and be able to use common-mode feedback to reduce the effects of gate bias stress by adapting the biasing voltages for the circuit as the threshold voltage would increase. Simulations results indicate a gain of 57.26dB which is significant in a technology such as this, moreover without the use of bootstrapping implemented through a high-pass filter. •After the main topology was finished the frequency compensation of the circuit was studied, as it initially presented a negative phase margin. Several compensation schemes were experimented but ultimately two compensations schemes were used in order to compensate the topology. Still, because of the atypical structure employed in the amplifier due to the limitations of having only one type of transistor, the dominant-pole of the system is a complex pole pair that is originated by a source-follower stage. This means that even with the circuit having a stable phase margin above 60othere is some overshoot in the response of the amplifier to a voltage step. •Then the developed opamp topology was adapted to work as a switched operational amplifier which is expected to reduce the shift in the threshold voltage of the TFTs used. The main objective here was to create an operational amplifier that was going to be disconnect during one clock phase and in which no transistor would be biased constantly, but instead biased by pulses. This adaptation also required the alteration of the common-mode feedback circuit used in the opamp, and for this circuit an adaptation of a topology presented in [10] was used. The final topology for the switched opamp was successfully implemented in simulation with the objective of not having any transistor constantly biased completed successfully. The topology has however a significant level of complexity especially because of all the limitations that are involved with the design of circuits in a technology such as a-GIZO. Also, if complete system on-chip is to be implemented the use of a charge-pump will be necessary because a clock with a voltage level higher than Vdd is required for the circuit to operate correctly. This topology constitutes the first proposal of the use of the switched opamp to reduce gate bias stress in TFTs and it is also the first switched opamp implemented with only n-type enhancement TFTs. •The proposed switched opamp was then used to implement a Sample-and-Hold circuit. The implemented circuit is adaptation of a circuit proposed in [11] as the characteristics of the a-GIZO TFT technology used had to be taken into account along with the fact that the common-mode voltage levels for the proposed the operational amplifier are different from those of the original circuit. Again the circuit was successfully implemented in simulation 6.2 Concluded Objectives 113 but it was found to have a low maximum switching frequency which is determined by the switched operational amplifier. The causes of the low switching frequency are the need of switching off all of the stages in the amplifier when the opamp is not active during the sampling phase and the magnitude of the intrinsic parasitic capacitances of the a-GIZO TFTs. •Finally both complete and stage-by-stage layouts were developed for both of the proposed amplifiers (switched version and regular version). Along with these layouts, additional layouts of high-gain differential stages with other techniques of increasing the load impedance were also designed. In this way, the novel topology for a single-stage high-gain differential amplifier with only n-type enhancement transistors presented in this work can be compared experimentally to other topologies that achieve high load impedance with a single type of transistor, such as topologies employing capacitive bootstrapping. 6.2 Concluded Objectives The main objectives were completed, as not one but two novel operational amplifiers topologies were developed. This topologies present interesting results in simulation and are expected to have good performance in terms of gain in a technology were high-voltage gain is difficult to achieve especially without using depletion type transistors. A new approach to reduced the effects of the shift in the TFTs Vth is also proposed. The layouts for all of the developed circuits were also developed and in a way that allows the testing of the developed circuits in a very flexible way. However, until the time of this writing no measurements were done in fabricated circuits because these have not yet been fabricated due to factors that are beyond the control of the author. 6.3 Future work In terms of the topology developed there is still the matter of realizing the measures in the circuits after fabrication. The data from the first fabricated chips should prove instrumental in the improvement and optimization of the developed topologies, especially if the transistors display a capacity to work with higher values for VGS, as less transistors could be used in both opamps. The frequency compensation scheme of the presented opamps should be restudied in order to try to find if there is a way of compensating the topology without complex poles associated with the source-follower stage, while still maintaining a bandwidth similar to the one obtained. Also, if accurate ways to simulate the parasitic capacitances of the a-GIZO TFT are found, the layouts for the circuits could be redone without keeping pads to connect compensation capacitors externally. In this way the complete operational amplifier could be implemented on-chip. The simulation model used must also be altered in order to solve the convergence issues that occur during the simulation of circuits where the a-GIZO TFT is used as a switch. 120 Expressions and simulation setups Table A.4: Aspect ratios for the differential amplifier with cascade ac bootstrapped load in NMOS (figure 4.1b) Transistor(s) Aspect ratio (µm/µm) M1,M2,M3,M4 160/20 M7,M8,M9,M10 5/5 M11 320/20 Table A.5: Bias voltages for the differential amplifier with cascade ac bootstrapped load in NMOS (figure 4.1b) Designation Value(V) Vdd 4.4 Vbias 3.2 Vb1 1.0 Table A.6: Aspect ratios for the differential amplifier with single differential feedback in NMOS (figure 4.2a) Transistor(s) Aspect ratio (µm/µm) M1,M2,M3,M4,M7,M8 160/20 M5,M6 159/20 M9,M10 320/20 Table A.7: Bias voltages for the differential amplifier with single differential feedback in NMOS (figure 4.2a) Designation Value(V) Vdd 3.3 Vb1 1.0 Vb2 1.0 Vb3 4.2 Table A.8: Aspect ratios for the differential amplifier with cascade differential feedback in NMOS (figure 4.2b) Transistor(s) Aspect ratio (µm/µm) M1,M2,M3,M4,M5,M6,M9,M10,M13,M14 160/20 M7,M8,M11,M12 159/20 M15,M16,M17 320/20 A.2 Bias and aspect ratios for the simulations of the high-gain topologies with only n-type enhancement transistors 121 Table A.9: Bias voltages for the differential amplifier with cascade differential feedback in NMOS (figure 4.2b) Designation Value(V) Vdd 4.4 Vb1 1.0 Vb2 1.0 Vb3 4.2 Vb4 5.3 A.2.2.2 a-GIZO TFT implementations Table A.10: Aspect ratios for the differential amplifier with single ac bootstrapped load in a-GIZO TFT (figure 4.1a) Transistor(s) Aspect ratio (µm/µm) M1,M2,M3,M4 160/20 M5,M6 40/20 M7 320/20 Table A.11: Bias voltages for the differential amplifier with single ac bootstrapped load in a-GIZO TFT (figure 4.1a) Designation Value(V) Vdd 15 Vb1 5 Table A.12: Aspect ratios for the differential amplifier with cascade ac bootstrapped load in aGIZO TFT (figure 4.1b) Transistor(s) Aspect ratio (µm/µm) M1,M2,M3,M4 160/20 M7,M8,M9,M10 40/20 M11 320/20 Table A.13: Bias voltages for the differential amplifier with cascade ac bootstrapped load in aGIZO TFT (figure 4.1b) Designation Value(V) Vdd 20 Vbias 15 Vb1 5 122 Expressions and simulation setups Table A.14: Aspect ratios for the differential amplifier with single differential feedback in a-GIZO TFT (figure 4.2a) Transistor(s) Aspect ratio (µm/µm) M1,M2,M3,M4,M7,M8 160/20 M5,M6 120/20 M9,M10 320/20 Table A.15: Bias voltages for the differential amplifier with single differential feedback in a-GIZO TFT (figure 4.2a) Designation Value(V) Vdd 15 Vb1 5 Vb2 5 Vb3 20 Table A.16: Aspect ratios for the differential amplifier with cascade differential feedback in aGIZO TFT (figure 4.2b) Transistor(s) Aspect ratio (µm/µm) M1,M2,M3,M4,M5,M6,M9,M10,M13,M14 160/20 M7,M8,M11,M12 120/20 M15,M16,M17 320/20 Table A.17: Bias voltages for the differential amplifier with cascade differential feedback in aGIZO TFT (figure 4.2b) Designation Value(V) Vdd 20 Vb1 5 Vb2 5 Vb3 20 Vb4 25 A.3 Frequency Compensation analysis The expressions shown in this chapter are relative to the schematic of the topology for the novel opamp in a-GIZO TFTs, presented in figure 4.21. A.3.1 Estimation of the time constants associated with each node The estimation of the time constants is obtained by determining the equivalent resistance for each node as well as the total capacitance connected between that node and ground. All of the time A.3 Frequency Compensation analysis 123 constants presented below are determined before the use of compensation. Node A: RA=2/gm3(A.9a) CeqA =CGS3+ (1−Av−1 1).CGD1(A.9b) The value of RAis represented as 2/gm3instead of 1/gm3, because the input impedance value of a common-gate stage will also depend on the resistance at the drain and will be given by [27, p. 80] Rin =RD ro +1 gm,(A.10) where RDis the resistance at the drain of the common-gate stage. In this expressions the terms related to body effect have not been considered. This equation reveals that if the drain resistance is high when compared to the intrinsic resistance of the transistor in the common-gate the input resistance will be higher than 1/gm. In the particular case that RD=ro,Rin =2/gm. In this case the load resistance, which is the equivalent resistance of the novel topology was found to be only slightly superior to roand therefore RA which is the input resistance of M3,4was approximated to 2/gm3 Node B: RB= ((gm1.ro1.ro3+ro1+ro3)||Rload )(A.11a) CeqB =CGD3+CGD17 +CGS13 +CGS9+(1−A f ).CGD9+(1−A f 1).CGD13 (A.11b) Rload is calculated from the expressions presented in 4.24. Node C: RC=ro38 +( 1 gm19 ||ro19)(A.12a) CeqC =CGD38 +(1−Av2).CGD21 +CGS21 (A.12b) Node D: 124 Expressions and simulation setups RD=ro21||(( 1 gm23 ||ro23)+( 1 gm24 ||ro24)+( 1 gm25 ||ro25)) (A.13a) CeqD =CGS29 + (1−Av−1 2).CGD21 +(1−Av3).CGD29 (A.13b) Output node (Node E): RE=ro29||(( 1 gm31 ||ro31)+( 1 gm32 ||ro32)) (A.14a) CeqE =Cload +(1−Av−1 2).CGD29 (A.14b) In the equations presented above Av1=3.451, Av2=10.1625, Av3=2.1627, A f =0.9727, A f 1=0.9784 and a=0.962. Av1is the voltage gain from the input to node A, Av2is the voltage gain of stage Common-Source 1,Av3the gain of the output stage and Af the voltage gain of the differential amplifier that implements positive feedback in the active loads of the input stage. Appendix B Overview of Single Stage Amplifiers In the following subsections the common topologies of amplifying stages are presented and their main characteristics analysed. Only stages compromised of n-type enhancement transistors are considered because there are no complementary transistors available for use in the a-GIZO TFT technology, as previously referred in section 2.5.2. B.1 Common-Source Stage One of the common single stage amplifier topologies is the common source stage, presented in figure B.1. Vdd Vi Vo M1 Rd Figure B.1: Common-Source Stage From the analysis of this configuration through the simplified small-signal model of the transistor it can be shown that the small-signal gain of the configuration for a generic load resistance RDis given by Av=−gm(RD||ro)(B.1) When considering the analysis of the input and output impedances for this topology it can be quickly inferred from the small-signal model of the transistor that the output impedance of this configuration is Rout =RD||ro(B.2) 125 126 Overview of Single Stage Amplifiers And the impedance associated to the input is significantly high considering that the gate of the device is insulated. Due to the characteristics presented above it is easily seen that this topology is ideally suited to achieve high input impedances and it can be used to achieve signal inversion due to the negative gain it presents. In terms of its application for high-gain stages, it is easily observed that in this configuration the overall gain that can be achieved is constrained by the value of the transistors output resistance, rowhich can assume values of some Mega Ohms in the a-GIZO TFT technology, by the load resistance present at the drain, RDand by the transconductance of the drive transistor. Therefore, to achieve a high small-signal gain both resistances need to be high and of a similar magnitude (both resistors are in parallel), which means that if one of the resistors is significantly higher than the other, the value of the output impedance will be closer to the resistor with the lowest value between the two, conditioning the small-signal gain. This means that in order to have high-gain values with a-GIZO TFTs it is necessary to try to achieve load resistances of a similar, or even superior magnitude to that of the internal small-signal output resistance of the transistors used in the drive. B.2 Common-Source Stage with Source Degeneration A variation of the common-source stage is achieved introducing a resistance, RS, at the source of the transistor, as shown in figure B.2. Vdd Vi Vo M1 Rd Rs Figure B.2: Common-Source Stage with Source Degeneration After analysing this topology using the small-signal model of the a-GIZO TFT the small-signal gain is determined after some mathematical manipulation as Av=−gmRD 1+gmRS (B.3) If gmRS1 the gain can be approximated as Av≃−RD RS (B.4) This topology presents similar characteristics to the regular common-source stage for the input impedance. B.3 Source Follower 127 The objective of using this configuration is to have a small-signal gain that is not as dependent of the intrinsic characteristics of the transistor as the gain of the regular common-source stage, avoiding non-linearities associated with the transconductance. As shown by equation B.4, if gmRS is high enough, the magnitude of the small-signal gain is approximately determined by the ratio of drain and source resistors, therefore less sensitive to variations of gm. B.3 Source Follower Another common amplifier stage is the source follower, also designated as common-drain stage, presented in B.3. Vdd Vi M1 Rs Vo Figure B.3: Source Follower Stage The small-signal gain of this topology is Av=gm(RS||ro) 1+gm(RS||ro)(B.5) If gmRS1 the small-signal gain is approximately equal to unity. The input impedance of this stage is very high as with the common-source stages presented previously. The output impedance is given by Rout =1 gm||RS||ro(B.6) Since the resistance 1 gmis typically lower than RSand ro, this stage typically presents a low output impedance when compared with the output impedance of a regular common-source stage. Due to its characteristics, this stage is normally used as a buffer to connect high voltage gain stages that depend on the value of the load impedance, such as the common-source stage, to low impedance loads. In this situations the almost unitary gain of the source follower allows for a very reduced loss of gain relatively to the previous stage and its very high-load impedance assures that the load impedance of the previous stage remains almost unaltered. Nonetheless a factor that must be considered when designing an operational amplifier where one or more source follower stages are employed is that this stage can have a significant impact in the overall frequency response. 128 Overview of Single Stage Amplifiers B.4 Common-Gate Stage Another stage typically employed in signal amplification electronics is the Common-Gate stage, figure B.4. This topology as one main difference regarding the others previously presented, which is related to the terminal of transistor were the input signal is applied. Recall that in both the common-source and the source follower stages the input was applied to the gate of the transistor, however in this stage the input is applied to the source terminal. Rd Vb Vi Vdd M1 Vout Figure B.4: Common-Gate Stage The advantage of applying the input to the source terminal is related to the low-input impedance that the transistor presents seen into the source terminal and to the fact that in this configuration the input signal can be a current. Analysing the small-signal model of the transistor, the input impedance is determined as Rin =1 gm (B.7) This impedance is of course much smaller than the one presented by the gate terminal which is insulated and therefore presents a very high impedance. Also from the analysis of the small-signal model of the transistor, the gain of the stage is found to be Av=gm(RD||ro)(B.8) In terms of frequency behaviour it important to note that unlike the common-source stage in this configuration there is no Miller multiplication of CGD, which is an important advantage of this configuration and constitutes one of the main reasons behind the usage of the cascode topology. B.5 Cascode stage The Cascode Stage, figure B.5, uses a common-gate transistor as the load of the input transistor which is connected as a common-source. In this topology M1 converts the voltage signal at its gate into a current signal which is applied to the source of M2. A set back of this topology is the voltage Vbthat is necessary to bias M2 in saturation and a reduced output voltage swing when compared with the common-source stage. The minimum output level is given in this topology by the minimum level at which both M1 and M2 are in saturation. This level is equal to the sum of the overdrive voltages of both transistors. In comparison in a B.6 Differential Pair 129 Vdd Vi Vo M1 Rd M2 Vb Figure B.5: Cascode Stage common-source stage the minimum output level is only determined by the overdrive voltage of the single drive transistor. From the analysis of the small-signal model of the transistor the gain of the stage is found to be Av=−gm1 gm2 gm2(RD||ro)(B.9) The of gain of the cascode stage can be further simplified to Av≃−gm1(RD||ro)(B.10) Therefore, small-signal gain of the cascode stage is equal to that of a common-source-stage, presented in equation B.1. Until now it seems that this topology presents no advantages relatively to the common-source topology; the gain is the same and it even has a lower output swing. But there are advantages related to the use of this topology, one of which is the very high output impedance of this stage, which is found to be Rout = (1+gm2ro2)ro1+ro2(B.11) Knowing that the intrinsic gain of an amplifying stage, which is the voltage gain an amplifying would present in the presence of an infinite load resistance, is given by Aint =GmRout (B.12) From B.11 and B.12 one can conclude that for this topology the maximum voltage gain is theoretically approximate to the square of the intrinsic gain of a single transistor, because Rrout is proportional to ro1ro2. Nevertheless, the most important advantage is in terms of bandwidth since it reduces the Miller effect on the input transistor. B.6 Differential Pair In terms of the design of operational amplifiers there is one characteristic that must be present in every topology which is the use of a differential input. For this reason the differential becomes