A 0.3-V 98-dB Rail-to-Rail OTA in 0.18 um CMOS

Received January 27, 2020, accepted February 3, 2020, date of publication February 6, 2020, date of current version February 13, 2020. Digital Object Identifier 10.1109/ACCESS.2020.2972067 A 0.3-V 98-dB Rail-to-Rail OTA in 0.18 µm CMOS TOMASZ KULEJ 1AND FABIAN KHATEB 2,3 1Department of Electrical Engineering, Częstochowa University of Technology, 42-201 Częstochowa, Poland 2Department of Microelectronics, Brno University of Technology, 601 90 Brno, Czech Republic 3Faculty of Biomedical Engineering, Czech Technical University in Prague, 272 01 Kladno, Czech Republic Corresponding author: Fabian Khateb ([email protected].cz) This work was supported by the National Sustainability Program under Grant LO1401. ABSTRACT A new solution for an ultra-low-voltage, ultra-low-power operational transconductance amplifier (OTA) is presented in the paper. The design exploits a three-stage structure with a Reversed Miller Compensation Scheme, where the input stage is based on a non-tailed bulk-driven differential pair. Optimization of the structure for very low supply voltage is discussed. The resulting amplifier outperforms other ultra-low-voltage OTAs in terms of a DC voltage gain and power efficiency, expressed by standard figures of merit. Experimental verification using a 0.18 µm CMOS technology, with supply voltage of 0.3-V, showed a dissipation power of 13 nW, a DC voltage gain of 98 dB, a gain-bandwidth product of 3.1 kHz and an average slew-rate of 9.1 V/ms at 30 pF load capacitance. The experimental results agree well with simulations. INDEX TERMS Bulk-driven, operational transconductance amplifier, operational amplifier, low voltage, low power. I. INTRODUCTION The increasing demand for ultra-low-power electronic systems, entails an increasing interest in the design of analog and mixed signal circuits, powered with very low supply voltages, often much lower than 0.5 V. These new designs include operational amplifiers [1]–[8], linear transconductors [9], [10], differential-difference amplifiers [11] hysteretic comparators [12], and many other building blocks. In order to ensure sufficient voltage swing at such extreme supply conditions, a bulk-driven (BD) technique [13], [14] is often considered. Even though the BD transistors suffer from a reduced transconductance, that entails larger input noise and offset, this technique seems to be still attractive in such cases when the supply voltage (VDD) is comparable with the threshold voltage (VTH) of the used MOS transistors and a large input common-mode range (ICMR) is required at the same time. One of the most important analog building blocks in integrated systems is the operational transconductance amplifier (OTA). In recent years a number of deep sub 0.5-V OTAs have been shown in the literature [2], [4], [6]–[8]. It is worth mentioning, that the presented OTAs usually show moderate value of the DC open-loop voltage gain. In most cases it is associated with the use of low-VTH CMOS processes, that entails reduced intrinsic voltage gains of MOS transistors, The associate editor coordinating the review of this manuscript and approving it for publication was Cihun-Siyong Gong . as well as smaller gmb/gmratios [2]. In order to overcome this issue, specific layout design techniques combined with a partial positive feedback [2], three-stage structures [4], [8] or other gain-boosting techniques can be used [6]. Nevertheless, despite special design approaches, the achieved voltage gains in most cases are rather moderate, ranging from 43 dB [4] to 70 dB [8]. Only in some cases a slightly larger voltage gain, exceeding 70 dB, can be achieved, using partial positive feedback or auxiliary current-mode amplifiers [6], but at the cost of a reduced gain-bandwidth product (GBW) and slew-rate (SR). In this work a new solution for a high-gain (ca. 100 dB) deep sub 0.5-V OTA is presented. The design is based on a three-stage structure, where the input differential pair is realized using the idea of non-tailed differential stage [15], that can operate from very low relative supply voltages (VDD/VTH), while offering improved DC voltage gain and SR. Consequently, an ultra-low-voltage (ULV) three-stage amplifier was designed using standard 0.18 µm CMOS process with relatively large intrinsic voltage gains of MOS transistors. The achieved voltage gain of the considered structure approaches 100 dB, while operating from VDD as low as 0.3 V. Moreover, the achieved GBW and SR to supply current ratios are competitive to the ones achieved for other OTAs presented in literature with similar VDD. The three-stage amplifier was frequency compensated using similar approach as presented in [16] for a 1-V gate-driven amplifier. VOLUME 8, 2020 This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see http://creativecommons.org/licenses/by/4.0/ 27459 T. Kulej, F. Khateb: 0.3-V 98-dB Rail-to-Rail OTA in 0.18 µm CMOS FIGURE 1. CMOS schematic of the proposed three-stage OTA. Nevertheless, the ULV design requires larger transistor sizes, that leads to larger parasitic capacitances affecting the circuit performance. Hence, the design constraints associated with an ULV environment as well as the optimization of such a structure under sub-VTH supply are discussed in the paper. The proposed circuit can serve as a general-purpose OTA in ULV amplifiers, active filters, analog to digital converters and other applications requiring high-gain OTAs. The rest of the article is organized as follows. In section II a general description of the OTA is presented. In section III, the design constraints in an ULV environment are discussed. Experimental and simulation results are shown in section IV. Finally, the paper is concluded in section V. II. CIRCUIT DESCRIPTION The structure of the presented OTA is shown in Fig.1. The circuit consists of three stages. Its simplified block diagram is depicted in Fig. 2, where gmi, Roi and Coi are the i-th stage transconductance, resistance and equivalent output capacitance respectively, while gmFF stands for the transconductance of the feedforward path implemented by M10. The overall structure can be considered as a Reversed Nested Miller Compensation (RNMC) topology [17]–[19]. The RNMC structures are often implemented with the use of a special nulling resistor, however, in this design the nulling resistor was removed, since its value would be un-practically large, in the range of tens of mega ohms. The resistorless FIGURE 2. Block diagram of OTA. version of a 3-stage RNMC OTA, devoted to driving large capacitive loads was previously discussed in [16]. The first stage of the presented structure (M1-M4) is based on a non-tailed bulk-driven differential amplifier [15]. Despite the non-tailed architecture, the circuit behaves as a truly differential amplifier, with good common-mode rejection (CMRR) and power supply rejection (PSRR) ratios. Compared to the BD differential pair biased with the same total current and the same sum of transistor channel areas, the circuit offers improved voltage gain (+6 dB), slew-rate and lower minimum VDD, while showing the same input referred noise and offset [7], [15]. The use of such a circuit allows realizing amplifiers with very low VDD (0.5 V) and rail-to-rail ICMR, while using CMOS processes with standard VTH voltages of around 0.4-0.5V, low leakage currents and relatively high intrinsic voltage gains of MOS transistors. All these features allow increasing the overall voltage gain of an ULV OTA. The second stage of the amplifier is formed by the transistor M6, loaded with the current source based on the transistor M5. The output stage (M7-M10) [16], [20] operates in class AB, that increases its current driving capability and SR. The capacitances CC1 and CC2 are used for frequency compensation. Transistors M11-M13 form the biasing circuit. A. SMALL-SIGNAL PERFORMANCE The small-signal analysis of the structure in Fig.2. has been performed in [16]. For simplicity it was assumed that CC1,2, CLCoi and gmiRoi 1, i=1. . .3 (CLbeing the load capacitance of OTA). With the above assumptions the circuit is described by a third order transfer function with two zeros, one located in the left half-plane (LHP) and the other one in the right half-plane (RHP) [16]. The DC voltage gain of the circuit can be approximated as: Avo ≈ −gm1Ro1gm2Ro2gm3Ro3(1) while the dominant pole p1and the gain-bandwidth product (ωGBW) are respectively given by: p1≈ − 1 Ro1gm2Ro2gm3Ro3CC1 (2) ωGBW =gm1 CC1 (3) 27460 VOLUME 8, 2020 T. Kulej, F. Khateb: 0.3-V 98-dB Rail-to-Rail OTA in 0.18 µm CMOS As it was shown in [16], assuming gmFF =gm3, CC2 <gm2gm3CC1/g2 m1 and CLCC1, the phase margin 8can be approximated as: tan φ=gm2gm3C2 C1−g2 m1CC2CL gm1gm2CC1CL (4) From (4), the compensation capacitor CC1 can be calculated using the following formula [16]: CC1=sgm1CC2CL gm3gm1 gm2+tan φ(5) Assuming operation in a weak inversion region and neglecting the second-order effects, the transconductance gm1 in Fig. 2 can be expressed as: gm1∼ =2gmb1=2ηID1 npVT (6) where η=gmb/gmis the bulk to gate transconductance ratio at a given operating point for transistors M1A,B, ID1 is the quiescent drain current of these transistors, npis the subthreshold slope factor for a p-channel MOS and VTis the thermal potential. The transconductances gm2 and gm3 in Fig. 2 are given by: gm2=ID5,6 nnVT (7) gm3=ID8 nnVT·(W/L)9 (W/L)7=ID10 nnVT (8) Note, that the feedforward transconductance gmFF is equal to gm3. B. IMPACT OF STRAY CAPACITANCES Ultra-low-voltage (sub VTH) design entails large transistor sizes to maintain both, low |VGS|voltage drops at the operating point, as well as sufficiently high output resistances of transistors at reduced VDS voltages. The large transistor sizes entail larger parasitic capacitances Coi. Therefore, using the formulas developed in ideal case could lead to large errors. The most critical is the impact of the parasitic capacitance Co2, since outputs of the first and the third stages are shunted with large capacitances CC1, CC2 and CL(in addition, in case of the first stage the capacitances CC1 and CC2 are multiplied by the Miller effect). Non-ideal analysis with a non-zero value of Co2 give the same formulas for tan 8and CC1 as developed for ideal case, however, in (4) and (5) the capacitance CC2 should be replaced with C0 C2 =CC2 +Co2. Note, that Co2 limits the minimum value of C0 C2, which next limits the minimum value of CC1 and consequently lowers the GBW product of OTA. C. SLEW-RATE PERFORMANCE Slew-rate in multi-stage amplifiers is limited by the slowest stage. For the considered structure its value can be expressed by: SR =min Io1max Co1+CC1+CC2;I02max Co2+CC1;I03max Co3+CL(9) where Ioimax (i=1. . .3) is the maximum output current of the i-th stage of the OTA. Assuming that the SR is not constrained by the |VGS|voltage drops across the diode-connected transistors, in the considered design the negative slew-rate (SR-) is limited rather by the first stage and can be estimated as: SR−≈Io1max Co1+CC1+CC2 (10) where Io1max is given by: 2ID1sinh ηVinm npUT(11) where Vinm is the amplitude of the input step and its maximum value is equal to VDD. It is worth noting, that the maximum value of Io1max is achieved only in the first phase of falling of the output signal. As the output voltage (in a voltage follower configuration) decrease, the output current of the first stage decrease as well, which slows down the falling process. Thus, the real SRcan be lower than calculated from (10). The positive slew-rate (SR+) is limited rather by the intermediate stage and can be estimated as: SR+≈ID5 Co2+CC2 (12) As it can be concluded from (10) and (12) in general case one can expect an unsymmetrical large-signal behavior of the amplifier. D. INPUT NOISE AND DYNAMIC RANGE The input noise of the OTA is determined by its input stage. Given that M1is identical with M2(ID1 =ID2), which guarantees optimum noise performance [15], the input-referred thermal and flicker noise densities (¯v2 tand ¯v2 1/frespectively) in a weak inversion region can be expressed as: ¯v2 t=8kT 3gmb1,2gm1,2 gmb1,2+gm3,4 gmb1,2(13) ¯v2 1/f=1 fCOX g2 mb1 Kfpg2 m1,2 W1,2L1,2+Kfng2 m3 2W3L3+Kfng2 m4 2W4L4!(14) where Kfn, Kfp are the flicker noise constants for nand p-channel transistors respectively and the other symbols have their usual meaning. Considering only the thermal noise (which is dominant in most cases due to the low biasing currents) and assuming the maximum amplitude of the input signal equal to VDD/2, the biasing currents of the input stage (ID1 =ID2) for the assumed dynamic range (DR) in a voltage follower configuration can be calculated using the following equation [6]: ID1,2=1 4DR28kT (π 2)fGBW 2npVT2√2 3η2VDD/2√22(15) VOLUME 8, 2020 27461 T. Kulej, F. Khateb: 0.3-V 98-dB Rail-to-Rail OTA in 0.18 µm CMOS Thus, the required biasing current ID1,2is proportional to the GBW product of the amplifier and to the square of the DR. On the other hand, the current ID1,2is inversely proportional to the square of the parameter η, so maintaining the same DR and GBW using the BD approach entails worse power effectiveness of the overall structure as compared with the gate-driven (GD) approach. III. OTA DESIGN Due to the ULV operation of the considered structure, where the input noise and DR are one of the main concerns, the design has been started with calculating the value of the required biasing currents of the input stage, using eqn. (15). This determined also the value of the input transconductance gm1 [see (6)]. Assuming DR =60 dB (η=0.36, np=1.35,)), from (15) the current ID1 was found to be 2.5 nA for VDD =0.3V. As it was shown in [16], to achieve power optimization, the transconductance gm3 should be equal to 2gm1 +gm2, while it is suggested to choose the gm2/gm1 ratio between 4 and 7. Taking the above into account, from (6)-(8), we achieve: ID5,6=(4. . . 7)·2ηID1 np nn (16) ID9,10 =4ηnn np ID1+ID5,6(17) Thus, with nn/np≈1, assuming gm2/gm1 =5.56 we set the value of ID5,6to 10 nA. Consequently, from (17) the value of ID9,10 was calculated to be 13.6 nA, which was rounded up to 15 nA, to achieve the ID9,10/ID1 ratio to be an integer number. For the given biasing currents of OTA the circuit was dimensioned during the simulation phase. The channel lengths of transistors (L) were chosen relatively large to increase their output resistances, and hence their intrinsic voltage gains. Only for M7and M9the channel lengths were lower, to decrease their Cgs capacitances, and consequently increase the frequency of the parasitic pole pp, associated with the drain/gate node of M7, which should be located well above the GBW product of OTA. The current ID7,8 was chosen to be ID9,10/4. This value was also a result of a compromise between the total dissipation power and the frequency of pp. For the assumed L, the channel widths (W) of all transistors were adjusted to achieve |VGS|≈VDD/2, which results in a maximum voltage headroom for possible changes of |VGS|, caused by the process and temperature variations. It is also worth noting, that minimum channel areas for transistors in the input stage are constrained by the required offset of OTA and flicker noise. Once the circuit was dimensioned, the parasitic capacitance Co2 was estimated to be 0.31 pF. The capacitance CC2 was then assumed to be 0.6 pF, i.e. the capacitance Co2 was around 1/3 of the sum CC2 +Co2, and the nonlinear capacitors Cbd5 +Cbd6 were around 10 % of this sum. Next, from (5), replacing CC2 with CC2’ and assuming CL=20pF, 8=68◦, the capacitance CC1 was calculated to be 2.4 pF. Thus, the anticipated GBW was 3.45 kHz. IV. RESULTS AND COMPARISON A. IMPLEMENTATION The circuit has been implemented in a 0.18 µm CMOS process from TSMC, with threshold voltages of around ±0.5V. The supply voltage was 0.3 V (±0.15 V during measurement) and the biasing current IBwas 2.5 nA (provided externally). The circuit performance was also tested for VDD = 0.5V/IB=40nA. The transistor aspect ratios are shown in Table 1. The circuit was dimensioned as described in section III. The small-signal parameters of the design are summarized in Table 2, while Fig.3 shows the microphotograph of the fabricated OTA. TABLE 1. Transistor aspect ratios. TABLE 2. Small-Signal Parameters of OTA for VDD =0.3V, IB=2.5 nA. FIGURE 3. Microphotograph of the fabricated OTA. B. EXPERIMENTAL RESULTS Below, the measured performance of the test chip is presented. Since the parasitic load capacitance of our printed circuit board exceeded 20 pF, the test chip was measured for CL=30pF. This capacitance was fine-tuned and measured with a precise RLC meter E498A from Agilent. Fig.4 shows the open-loop frequency responses of OTA, measured for two supply voltages (0.3 V and 0.5 V) and two 27462 VOLUME 8, 2020 T. Kulej, F. Khateb: 0.3-V 98-dB Rail-to-Rail OTA in 0.18 µm CMOS FIGURE 4. Open-loop frequency characteristics of OTA for (a) VDD =0.3 V, IB=2.5 nA, (b) VDD =0.5V, IB=40 nA. corresponding biasing currents IB(2.5nA and 40 nA). Due to the limitations of our vector network analyzer (Bode 100), the characteristics were measured for f >1Hz. The voltage gains at 1 Hz were 71.4 and 93 dB for the 0.3 and 0.5-V version respectively. The value of a DC voltage gain was found to be 98.1 dB and 103.6 dB for a 0.3-V and 0.5-V version respectively. Figs. 5 and 6 show the selected small-signal parameters (GBW, 8, Avo) against the input common-mode voltage Vicm for VDD =0.3V. The quiescent output level of Vout was equal to Vicm. The measured Avo remained larger than 85 dB for Vicm ranging from 50 mV to 250 mV, i.e. 50 mV for each supply rail. The measured variations of GBW and 8remained relatively small (±4.5 % for GBW) with Vicm ranging from 50 mV to 250 mV, that proves small variation of the input transconductance of the OTA. Due to the limited voltage swing, and operation with VBS <0 in the whole input range, FIGURE 5. GBW and phase margin of OTA against the input common-mode voltage, VDD =0.3V, IB=2.5nA, CL=30pF. FIGURE 6. DC voltage gain of OTA against the input common-mode voltage, VDD =0.3V, IB=2.5nA. the relative variations of the input transconductance were lower than observed for other BD input stages supplied with larger VDD [21]. Fig. 7 shows the large-signal step responses of the OTA for an input step of VDD-50 mV peak-to-peak. The overshoots and oscillations of the responses are on acceptable level. Both responses showed SR+>SR−, that was in agreement with theoretical expectations (see (10) and (12)). FIGURE 7. Step responses of OTA for (a) VDD =0.3 V, IB=2.5 nA f=100 Hz, horiz: 1ms/div, vert: 50 mV/div, (b) VDD =0.5V, IB=40 nA, f=1kHz, horiz: 100 µs/div, vert: 75 mV/div. In Fig. 8 the sine-wave responses for rail-to-rail input are presented, showing, that the input and output VOLUME 8, 2020 27463 T. Kulej, F. Khateb: 0.3-V 98-dB Rail-to-Rail OTA in 0.18 µm CMOS TABLE 3. Performance summary of the 3-stage OTA. common-mode ranges are both rail-to-rail. The Total Harmonic Distortion (THD) for a 0.3-V version was 0.49 % for Vin =250 mVpp and f=10 Hz. Table 3 summarizes the simulated and measured performances of the OTA for two supply voltages. The circuit was simulated for CL=20 pF (value used in design) and CL= 30 pF (used in measurements). The simulated value of 8for CL=20 pF was 63.7◦, and was quite close to the value predicted theoretically (68◦). The small difference between the theoretical and simulated values may be attributed to the second order effects, mainly the impact of the parasitic pole pp, associated with M7. Note, that neglecting the Co2 in the design leads to a phase error exceeding 10◦. The values of the measured Avo, GBW and other parameters were in good agreement with simulations. Larger differences were observed only for CMRR and PSRR, however, both parameters remain on acceptable levels. The simulated DC voltage gains for VDD =0.5V were larger than for VDD =0.3V due to the larger VDS voltages of MOS transistors at the operating point, that entailed slightly larger output resistances of the devices. The input referred noise was only simulated because of the lack of the proper noise meter. The corner frequency for flicker noise was relatively low (32 Hz) due to the low biasing currents (larger thermal noise) and large transistor channel areas. The total input noise integrated from 0.1 Hz to GBW was 109 µV and was dominated by thermal noise. The measured input current of OTA was lower than 100 pA for VDD =0.3V and Vicm =0 (i.e. −0.15 V during measurement, where ±0.15 V supply was used). They are equal to the currents of the forward-biased bulk-source junctions of the input transistors M1/M2and decrease exponentially with Vicm. Table 4 shows the results of Monte Carlo (MC) analysis for VDD =0.3V. As it can be concluded from the results, the design is robust against transistor mismatch. In order to show the circuit sensitivity against process and temperature (P/T), the simulated results of corner and temperature analysis for VDD =0.3 V are shown in Table 5. The results of the simulations prove, that the circuit is robust also against P/T variations. Larger changes were observed only for SR, which may be attributed mainly to the variations of |VGS| voltages of transistors, that affected the maximum output currents of the amplifier gain stages in an ULV environment. C. PERFORMANCE COMPARISON Table 6 presents a comparison of the proposed OTA with other fabricated ultra-low-voltage OTAs (VDD ≤0.7 V). As it can be concluded, the proposed design offers the best DC voltage gain, much higher than achieved in other designs 27464 VOLUME 8, 2020 T. Kulej, F. Khateb: 0.3-V 98-dB Rail-to-Rail OTA in 0.18 µm CMOS FIGURE 8. Sine wave responses of OTA for rail to rail input; (a) 0.3V/2.5 nA, (10 Hz), horiz: 20ms/div, vert: 50 mV/div, (b) 0.5V/40 nA (100 Hz), horiz: 2 ms/div, vert: 60 mV/div. and one of the lowest relative supply voltages (VDD/VTH), the same as achieved in the best so far designs [6], [7]. The noise properties of the compared circuits differ significantly, since the input noise highly depends on the biasing currents (GBW product of OTA), and the type of the input stage (BD or GD). In general, the solutions based on the GD approach show lower input noise, at the cost of a lower ICMR. The design proposed here show similar noise as other deep sub 0.5-V amplifiers with similar bandwidth and rail-to-rail input. In order to compare small-signal and large-signal power effectiveness of the OTAs in Table 6, the following standard figures of merit (FOMs) have been adopted: IFOMS=GBW ·CL IDD (18) IFOML=SRa·CL IDD (19) where SRa=(SR++SR−)/2 is the average slew-rate and IDD is the total supply current. In order to better compare the low voltage capabilities of the OTAs in Table 6, the next two FOMs have been used, which refer the small-signal bandwidth and SR to the total dissipation power Pdiss rather than IDD: FOMS=GBW ·CL Pdiss (20) FOML=SRa·CL Pdiss (21) TABLE 4. Results of Monte Carlo Analysis, for VDD =0.3 V, IB=2.5 nA, CL=30 pF, (200 runs). TABLE 5. Simulated Main Performance Parameters over Process and Temperature Variations for VDD =0.3 V, IB=2.5 nA, CL=30 pF. As it is can be concluded from Table 6, the proposed circuit outperforms all other designs in terms of IFOMLand FOML, and offers one of the highest values of IFOMs and FOMs. Only the design in [3] offers better FOMs, since it was optimized for particular value of CL. Nevertheless, the OTA in [3] does not provide a rail-to-rail input range. As compared with other similar OTAs published recently, [6], [7], the proposed OTA offers larger DC voltage gain and large-signal FOMs (FOMLand IFOML). The most important advantage of the structure in [7] is high CMRR and simple topology, while the circuit in [6] offers symmetrical SR. VOLUME 8, 2020 27465 T. Kulej, F. Khateb: 0.3-V 98-dB Rail-to-Rail OTA in 0.18 µm CMOS TABLE 6. Performance comparison of sub 0.7-V Amplifiers. It is also worth noting, that the 1-V OTA in [16], where similar frequency compensation method was used, showed IFOMs of 20513 MHz ·pF/mA at CL=200pF. However, this IFOMs was proportional to the square root of CL. Therefore, for CL=30 pF one could expect the IFOMs of around 8000 MHz ·pF/mA. Nevertheless, the above OTA was realized with larger VDD and much lower transistor sizes, that allowed decreasing CC2 to 0.15 pF, thus improving the GBW product of OTA. In the design discussed here, the GBW product was constrained by the parasitic capacitances of transistors. The other factors affecting IFOMs in this design were: larger biasing current of the BD input stage for the same transconductance and additional power consumed by the biasing circuit, which was included in the total dissipation power. Nevertheless, the OTA described in this work showed the best performance among all sub 0.5-V OTAs in terms of the DC voltage gain and standard FOMs. V. CONCLUSION The paper presents a design of a 0.3-V ultra-low-power OTA. The circuit is based on a three-stage structure with an RNMC compensation scheme and an input stage based on a non-tailed BD differential pair. Design restrictions in an ULV supply conditions are discussed. Experimental verification showed superior performance in terms of standard FOMs and DC voltage gain, as compared with other similar OTAs with sub 0.5-V supply and rail-to-rail input common-mode range. ACKNOWLEDGMENT For the research, infrastructure of the SIX Center was used. REFERENCES [1] S. Chatterjee, Y. Tsividis, and P. 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TOMASZ KULEJ received the M.Sc. and Ph.D. degrees (Hons.) from the Gdańsk University of Technology, Gdańsk, Poland, in 1990 and 1996, respectively. He was a Senior Design Analysis Engineer at Polish Branch of Chipworks Inc., Ottawa, Canada. He is currently an Associate Professor with the Department of Electrical Engineering, Częstochowa University of Technology, Poland, where he conducts lectures on electronics fundamentals, analog circuits, and computer-aided design. He has authored or coauthored over 70 publications in peer-reviewed journals and conferences. He holds three patents. His current research interests include analog integrated circuits in CMOS technology, with emphasis to low voltage and low power solutions. He serves as an Associate Editor of the Circuits, Systems, and Signal Processing and IET Circuits, Devices &Systems. He was also a Guest Editor of the special issues on Low Voltage Integrated Circuits on Circuits, Systems, and Signal Processing, in 2017, IET Circuits, Devices & Systems, in 2018, and Microelectronics Journal, in 2019. FABIAN KHATEB received the M.Sc. and Ph.D. degrees in electrical engineering and communication and also in business and management from the Brno University of Technology, Czech Republic, in 2002, 2005, 2003, and 2007, respectively. He is currently an Associate Professor with the Department of Microelectronics, Faculty of Electrical Engineering and Communication, Brno University of Technology, and also with the Department of Information and Communication Technology in Medicine, Faculty of Biomedical Engineering, Czech Technical University in Prague. He holds five patents. He has authored or coauthored over 100 publications in journals and proceedings of international conferences. He has expertise in new principles of designing low-voltage low-power analog circuits, particularly in biomedical applications. He is a member of the Editorial Board of Microelectronics Journal. He is an Associate Editor of the Circuits, Systems, and Signal Processing,IET Circuits, Devices & Systems, and International Journal of Electronics. He was a Lead Guest Editor for the special issues on Low Voltage Integrated Circuits and Systems on Circuits, Systems, and Signal Processing, in 2017, IET Circuits, Devices & Systems, in 2018, and Microelectronics Journal, in 2019. He was also a Guest Editor of the special issue on Current-Mode Circuits and Systems; Recent Advances, Design and Applications on International Journal of Electronics and Communications, in 2017. VOLUME 8, 2020 27467