Methods for Extension of Tunability Range in Synthetic Inductance Simulators

ELEKTRONIKA IR ELEKTROTECHNIKA, ISSN 1392-1215, VOL. 24, NO. 3, 2018 1Abstract—Presented work focuses on methods for the extended electronic control in the designs of inductance simulators based on single-loop feedback topology. Implementation is based on diamond transistors as voltage-tocurrent converters and two voltage-mode multipliers connected to different positions in topology (providing amplification or control of equivalent resistance). Presented solutions achieve significantly extended adjustability of equivalent inductance value in comparison to standard approaches based on CMOS differential pair-based operational transconductances amplifiers. Proposed designs of synthetic inductors are based on utilization of integer-order as well as fractional-order (constant phase element) capacitor. Their features are verified both via PSpice simulations and experimental measurements. Results confirmed intended purposes of designs implementing discussed methods. Index Terms—Adjustability extension; Constant phase element; Diamond transistor; Electronic control; Fractionalorder inductance simulator; Integer-order inductance simulator; Tunability extension; Voltage-mode multiplier. I. INTRODUCTION Inductance simulators are very useful active building blocks for many various analogue systems [1], [2]. Their utilization is welcomed because they can replace standard metallic coils (heavy, bulky, expensive, unsuitable for lowfrequency applications) in signal processing circuits as well as due to their simple electronic controllability (that is practically impossible in metallic form). Various active elements [1], [3] are used in the design of inductance simulator. Operational transconductance amplifiers (OTAs) [1]–[6] are very beneficial in applications of immittance conversion [5], [7] and multiplication [7]. As we know, diamond transistor (DT) OPA860 [8] is frequently used as OTA, when base (B) serves as high-impedance input and collector (C) as high-impedance current output, and emitter (E) is connected to ground through so-called degradation Manuscript received 3 January, 2017; accepted 7 April, 2018. Research described in this paper was financed by Czech Ministry of Education in frame of National Sustainability Program under grant LO1401. For research, infrastructure of the SIX Center was used. Research described in the paper was supported by Czech Science Foundation projects under No. 16-11460Y. resistor, which sets value of transconductance (gm = 1/Rdeg) [9]. This connection can be also explained by an alternative way as second-generation current conveyor (CCII) [1] having connected current input terminal X to ground through resistor Rdeg, high-impedance voltage input Y serves as input and high-impedance terminal Z represents current output (typical inter-terminal relations are: IY = 0, VX = VY, IZ = IX) [9]. However, lack of electronic adjustability of commercially available CCIIs (AD844 for example) results in logical question: How circuits consisting these active elements should be electronically controlled? This is very important, because electronic controllability is one of the emerging issue expected from modern electronic circuits as subparts of communication systems. Several possible integrated OTAs, controllable by bias current, are available on the market (LM13700, LT1228). However, their dynamics and linearity as well as frequency features are not favorable for designs operating at hundreds of kHz and beyond in comparison to DT and high-speed multiplier (MLT), for example AD835 [10]. In this work, electronic control of immittance converter/inductance simulator based on two diamond transistors in single loop are analysed. Controllability of the parameters of the device is based on control of parameters of two voltage-mode multipliers included to the topology in several places. These two multipliers are employed in order to extend the tunability range. Extended range of control is observed in three cases. The following section explains the reasons and motivation for this work. Afterwards, all circuits are analysed in case of integer-order operational mode and also example of fractional-order operation is shown. The conclusion summarizes gained findings and suggests further works on this topic. II. MOTIVATION Figure 1 shows standard topology serving for impedance transformation and inversion, i.e. for design of synthetic inductance simulator as discussed for example in [5], where OTAs were employed as active elements in the loop. However, effectivity of gm driving by bias current (Ibias) in controllable applications is quite limited because of the Methods for Extension of Tunability Range in Synthetic Inductance Simulators Roman Sotner1, Jan Jerabek1, Norbert Herencsar1, Lukas Langhammer1, Jiri Petrzela1, Tomas Dostal2 1SIX Research Center, Faculty of Electrical Engineering and Communication, Brno University of Technology, Technicka 12, Brno, 616 00, Czech Republic 2Department of Technical Studies, College of Polytechnics Jihlava, Tolsteho 16, Jihlava 586 01, Czech Republic [email protected]z http://dx.doi.org/10.5755/j01.eie.24.3.20976 41 ELEKTRONIKA IR ELEKTROTECHNIKA, ISSN 1392-1215, VOL. 24, NO. 3, 2018 nonlinear (square root) dependence of gm on Ibias [4]–[5] (valid for CMOS solution). Bipolar solution of OTA has linear dependence of gm on Ibias [11], which extends tunability range, theoretically. However, in both cases (bipolar or CMOS), input dynamics and linearity is very limited. Therefore, better active elements (linear and having wider dynamics) than differential pair based OTAs should be considered for these purposes. Moreover, more effective methods of controllability can be developed and introduced for purposes of tunability extension. In CMOS implementation of OTAs, considering solution shown in Fig. 1, equivalent inductance value Leq is given by 12 12 12 () , bias bias bias inp mm bias bias bias I I I sC sC Zsgg k I I sC kI      (1) where Leq depends on both bias currents. C + -OTA 1 Ibias2 gm2 + - OTA 2 gm1 Ibias1 Zinp(s) B E C DT Rdeg1 1 gm1,2 @ 1/Rdeg1,2 B E C DT Rdeg2 2 1 diamond buffer Fig. 1. Standard topology of synthetic inductance simulator based on two OTAs [5] or diamond transistors (alternative realization). III. METHODS FOR TUNABILITY RANGE EXTENSION The following text deals with three investigated methods of tunability extension (targeted on special cases of dependence of Leq value on driving force) in feedback topology of two diamond transistors. In comparison to differential pair-based OTAs, diamond transistors do not allow electronic control of transconductance value (gm). Fortunately, other possibilities of electronic control in the topology (Fig. 1) can be added and bring certain advantages for designers as presented below. A. Single Adjustable Voltage Gain in the Loop Driven by Square of Control Voltage The first proposed solution shown in Fig. 2 includes two diamond transistors and two multipliers. The first multiplier serves as amplifier and the second as a squarer of DC driving voltage Vset. The square of driving voltage Vset serves as part of multiplication constant directly creating the gain of the block between C of DT1 and B of DT2. Voltage gain created by MLT1 has definition |A1| = 4∙Vy2 (explanation of MLT operation is provided later). Then the gain reaches dependence on Vset as: |A1| = 4∙(4∙Vset2) as clear from interconnection in Fig. 2. The relation for input impedance has a form (valid for integer-order capacitor)   12 22 12 2 11 ( ) . 16 inp set R R R sCR R sCR sCR Zs AA V    @ (2) Polarity of Leq can be easily modified by interchange of terminals y1, y2 of MLT1. However, special attention must be given to possible risk of instability and output saturation when polarity of the closed loop is positive. Advantage of presented approach consists in minimized negative impact of increasing number of active elements on the circuitry (MLT2 is not influencing frequency features, it operates with DC signal). B E C x2 x1 y1 y2 out MLT B E C DT DT C or CPE R1 R2 x1 x2 y1 y2 out MLT Vset Zinp(s) 1 2 1 2 Fig. 2. The first solution of the synthetic inductance simulator with extended control of Leq by Vset. B. Cascade of Two Adjustable Voltage Gains in the Loop Another solution is to cascade two MLTs in operation of controllable amplifiers, see Fig. 3. It creates very similar effect when compared to solution from Fig. 2. However, both MLTs are members of feedback loop, therefore their frequency features influence overall behaviour of the circuit. Both voltage gains A1 and A2 depend on Vset as shown in previous text (|A1,2| = 4∙Vset1,2), therefore, also final equation for input impedance depending on Vset is   12 12 22 12 22 12 ( ) . 16 inp R R R set A A A sCR R sCR sCR Zs AA AV     @ (3) The polarity of Leq can be turned by interchange of y1 and y2 connection in MLT1 or MLT2 (DC control by Vset) or by swap of input terminals x1, x2 of MLT2. Again, special attention must be given to stability issues when loop transfer turns to positive. B E C x1 x2 y1 y2 out MLT B E C DT DT C or CPE R1 R2 Zinp(s) x1 x2 y1 y2 out MLT Vset 12 1 2 Fig. 3. The second solution of the synthetic inductance simulator with extended control of Leq by Vset. C. Inversely Proportional Adjustable Resistors The last studied solution (Fig. 4) supposes two adjustable resistors, but dependence of equivalent resistances on DC control voltage Vset is now inversely proportional: 42 ELEKTRONIKA IR ELEKTROTECHNIKA, ISSN 1392-1215, VOL. 24, NO. 3, 2018 Req1,2 = R1,2/(1 ‒ A1,2) @ R1,2/(1 ‒ 4∙Vset1,2). In addition, clear restriction A1,2 < 1 (0  Vset1,2 < 0.25 V) arises from definition of this concept. Input impedance is defined as follows        12 12 12 12 22 22 () 11 . 114 inp R R R set A A A sCR R Zs AA sCR sCR AV     @  (4) B E C B E C DT DT C or CPE R1R2 Zinp(s) Vset 12 x1 x2 y1 y2 out MLT 1 x1 x2 y1 y2 out MLT 2 Fig. 4. The third solution of the synthetic inductance simulator with extended control of Leq by Vset (controllable resistances). IV. VERIFICATION We verified basic features of all previously presented concepts by PSpice simulations. Solution in Fig. 2 was also tested experimentally. Verification focuses on integer-order (implementation of standard capacitor) as well as fractionalorder behaviour (implementation of constant phase element (CPE) as discussed later). The voltage-mode multiplier AD835 [10] arranged for intended purposes in developed topologies is shown in Fig. 5. Note that the value of multiplication constant m = (Rf1 + Rf2)/Rf2 has been set to 4 in order to achieve |Amax| = 4. All cases of inductance simulators having extended tunability of parameters were tested by PSpice simulations when the following parameters were set as constant: R1 = R2 = R = 91  (overall value RΣ1,2 = R1,2 + Re1,2 = 102 i.e. sum of external R1,2 and internal Re1,2 resistance 11  of DT at E terminal [8]). x1 x2 y1 y2 out MLT x1+ - - + x2 y1 y2 x1-x2 = x y1-y2 = yz w 1 xy + z Rf1 Rf2 Vx1 Vout 100 Ω 300 Ω Vout = (Vx1 Vx2)·(Vy1 Vy2)·(Rf1+Rf2)/Rf2 Vx2 Vy1 Vy2 AD835 a) b) Fig. 5. Voltage-mode multiplier AD835 implemented in proposed designs: a) symbol, b) circuit solution and key relation. A. Integer-Order Behaviour All discussed topologies were tested with standard integer-order capacitor C = 1 nF. Ideal range of Leq tunability 250 H → 2.5 H was expected for Vset adjusted from 0.05 V to 0.50 V in case of the first and second solution (Fig. 2 and Fig. 3). Magnitude and phase responses of input impedance for first (Fig. 2) solution are shown in Fig. 6. Simulations yield Leq tunability 247 H → 3.0 H. Certain and common lossy resistive part (low value – below 5 ) of input impedance occurs in simulated results. (a) (b) Fig. 6. AC analysis of input impedance for the first solution (Fig. 2): a) magnitude responses; b) phase responses. Measurements were performed with vector network analyser (VNA) E5071C. Experimental results are presented by the red colour in figures and all measured traces start from 9 kHz due to frequency limitation of used VNA (9 kHz–4.5 GHz). However, it sufficiently confirms expected behaviour. AC analysis of the second solution (Fig. 3) yields very similar results (302 H → 3.0 H). The third (last) studied topology (Fig. 4) was tested in reduced range (0.02 → 0.2 V) of Vset due to above mentioned restriction (0  Vset1,2 < 0.25 V). It results in ideal Leq adjustability 12 H → 250 H. Simulations provided range 14 H → 237 H. Figure 7 and Table I introduce comparison of tunability of all solutions in comparison with standard method (proportional to 1/A, where A is controlled by Vset linearly). TABLE I. COMPARISON OF PROPOSED METHODS. Solution Range of Vset [V] Range of Leq [H] standard 0.05→0.50 (10:1) ideal: 50→5 (10:1) Fig. 2 (solution 1) 0.05→0.50 (10:1) ideal: 250→2.5 (100:1) simulated: 247→3.0 (82:1) measured: 136→3.3 (41:1) Fig. 3 (solution 2) 0.05→0.50 (10:1) ideal: 250→2.5 (100:1) simulated: 302→3.0 (101:1) Fig. 4 (solution 3) 0.02→0.20 (10:1) ideal: 12→250 (21:1) simulated: 14→237 (17:1) Solutions in Fig. 2 and Fig. 3 offer the largest adjustability of Leq. The solution from Fig. 4 is not as beneficial as obvious from comparison. On the other hand, utilization of equivalent resistance in form as in case of Fig. 4 brings also 43 ELEKTRONIKA IR ELEKTROTECHNIKA, ISSN 1392-1215, VOL. 24, NO. 3, 2018 improvement in comparison to standard method. Sensitivity and uncertainty of setting given by real behaviour causes differences of simulated and measured Leq, for Vset < 0.1 V especially. (a) (b) Fig. 7. Dependence of Leq on Vset: a) comparison of solutions 1, 2 (Fig. 2, Fig. 3); b) solution 3 (Fig. 4). B. Fractional-Order Behaviour We tested presented circuit in Fig. 2 also with so-called CPE implemented instead of standard integer-order capacitor. We used ladder structure RC designed and presented in [12] for α = 1/3 (  = 30°). Impedance of CPE (capacitance) from [12] has character ZCPE(s) = 1/(sαCα), where ǀZCPE(s)ǀ = 118 (@ 100 kHz). Then Cα can be calculated as Cα = 1/[(2f)α∙ǀZCPE(f)ǀ]. Our value reaches C1/3 = 1/[(2∙100∙103)1/3∙118] = 99 F/sec2/3. Equivalent inductance can be calculated as Leqα = Cα∙R2/(16∙Vset2) [sec1+α/F]. Simulated results are shown in Fig. 8, Table II, and Table III (values ǀZeqǀ were obtained at 100 kHz). The purple trace indicates magnitude for standard C = 1 nF (Vset = 0.25 V) for comparison purposes. TABLE II. CALCULATED AND SIMULATED EQ. INDUCTANCES. Vset [V] ǀZeqαǀ [] Leqα = Cα∙R2/(16∙Vset2) [sec4/3/F] (calculated theory) Leqα = Zeqα/(2∙f)1/3 [sec4/3/F] (simulated) 0.05 2240 25.7 26.2 0.10 624 6.4 7.3 0.25 103 1.0 1.2 0.50 26 0.26 0.3 TABLE III. COMPARISON OF SIMULATIONS AND EXPERIMENTS. Vset [V] ǀZeqαǀ [] (simulated) ǀZeqαǀ [] (measured) Leqα [sec4/3/F] (simulated) Leqα [sec4/3/F] (measured) 0.05 2240 1152 26.2 13.5 0.10 624 704 7.3 8.2 0.25 103 114 1.2 1.3 0.50 26 27 0.3 0.3 TABLE IV. COMPARISON WITH EXISTING SOLUTIONS. Reference Type of electronic control No. of passive/active elements Adjustability extension Type of Leq dependence on driving force [5] gm 1/2 No ~1/Ibias hyperbolic [13] N/A N/A No N/A N/A [14] gm 2/1 No ~1/√(Ibias) 1/square root [15] gm 2/1 No ~1/√(Ibias) 1/square root Fig. 2 A 3/4 Yes ~1/Vset2 1/quadratic Fig. 3 A 3/4 Yes ~1/Vset2 1/quadratic Fig. 4 A 3/4 Yes ~1/(1–4Vset)2 - N/A – not available, gm – transconductance, A – voltage gain a) b) Fig. 8. Simulated and measured a) magnitude, b) phase responses of solution in Fig. 2 utilizing fractional-order CPE. V. COMPARISON WITH STATE-OF-THE-ART Standard inductance simulator based on two OTAs has been introduced in [5] (Leq controlled by two gms in Fig. 1). However, issues [16] with linearity and dynamics remain (implementation of standard OTAs). Topologies focused on complex immittance synthesis were presented in [16]. However, synthesis does not suppose electronic control. Works [14], [15] introduce solutions based on single active element. The controllability of Leq is possible only by single gm. It highly reduces adjustability (gm driven by square root of Ibias), 0.25→1 mH (4:1) in [14] for example (our cases at least 17:1 in Table I). Therefore, presented methods offer solution extending limited tunability range, see Table IV. VI. CONCLUSIONS Three different circuitries serving for inductance simulation allowing advanced electronic control of Leq have been presented. Operational range of proposed circuits in this particular configuration belongs to hundreds of Hz up to 44 ELEKTRONIKA IR ELEKTROTECHNIKA, ISSN 1392-1215, VOL. 24, NO. 3, 2018 hundreds of kHz (max. units of MHz). The first and the second solution (Fig. 2, Fig. 3) seem to be the most beneficial, but also solution from Fig. 4 offers useful extension of tunability range in comparison to standard methods. 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