On Systematic Design of Fractional-Order Element Series

Article On Systematic Design of Fractional-Order Element Series Jaroslav Koton *,† , David Kubanek †, Jan Dvorak and Norbert Herencsar   Citation: Koton, J.; Kubanek, D.; Dvorak, J.; Herencsar, N. On Systematic Design of Fractional-Order Element Series. Sensors 2021,21, 1203. https://doi.org/10.3390/s21041203 Academic Editor: Pak Kwong Chan Received: 11 January 2021 Accepted: 5 February 2021 Published: 9 February 2021 Publisher’s Note: MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations. Copyright: c 2021 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/). Department of Telecommunications, Faculty of Electrical Engineering and Communication, Brno University of Technology, Technicka 12, 616 00 Brno, Czech Republic; [email protected] (D.K.); [email protected] (J.D.); [email protected] (N.H.) *Correspondence: [email protected]; Tel.: +420-541-146-971 † These authors contributed equally to this work. Abstract: In this paper a concept for the efficient design of a series of floating fractional-order elements (FOEs) is proposed. Using even single or a very limited number of so-called “seed” FOEs it is possible to obtain a wide set of new FOEs featuring fractional order α being in the range [−n , n] , where n is an arbitrary integer number, and hence enables to overcome the lack of commercial unavailability of FOEs. The systematic design stems from the utilization of a general immittance converter (GIC), whereas the concept is further developed by proposing a general circuit structure of the GIC that employs operational transconductance amplifiers (OTAs) as active elements. To show the efficiency of the presented approach, the use of only up to two “seed” FOEs with a properly selected fractional order αseed as passive elements results in the design of a series of 51 FOEs with different α being in the range [− 2, 2 ] that may find their utilization in sensor applications and the design of analog signal processing blocks. Comprehensive analysis of the proposed GIC is given, whereas the effect of parasitic properties of the assumed active elements is determined and the optimization process described to improve the overall performance of the GIC. Using OTAs designed in 0.18 µ m TSMC CMOS technology, Cadence Virtuoso post-layout simulation results of the GIC are presented that prove its operability, performance optimization, and robustness of the proposed design concept. Keywords: fractor; fractional-order element; generalized immittance converter; series design of fractors; “seed” FOE 1. Introduction In fractional calculus [ 1 – 5 ], generalizing derivatives with integer order to derivatives with non-integer or fractional order, has tremendously gained attention as it is applied in many and various engineering and research disciplines and areas, spanning biology [6–9] , food [ 10 – 12 ], cybersecurity [ 13 , 14 ], modeling and control [ 15 – 21 ], signal processing [ 22 – 24 ], electrical engineering [ 25 – 30 ], and other. The reason for the increased interest in fractionalorder calculus and system design may be seen in the fact that the presence of fractional order represents another degree of freedom to mathematically describe the behavior of a function block. This enables one to provide characteristics in between integer–orders in comparison to standard (integer-order) systems, which may become beneficial while more accurate signal generation and measurement, and/or system modeling and control is required. Dealing mainly in the areas of signal processing, modeling and control, and electrical engineering, the implementation of required fractional-order function block relies on the presence of elements with fractional-order immittance, i.e., fractional-order elements (FOEs) or simply fractors. To design a FOE with required fractional order α (generally α∈IR ), one of the direct implementations as recently summarized in [ 31 ] may be used, however all these techniques are still at the level of laboratory experiments. Hence, they do not provide readily available FOEs as discrete elements and mainly are suitable for capacitive Sensors 2021,21, 1203. https://doi.org/10.3390/s21041203 https://www.mdpi.com/journal/sensors Sensors 2021,21, 1203 2 of 23 FOE design only, i.e., 0 <α< 1. Additionally, the implementations as described in [31] enable one to obtain FOEs that are operable in a limited frequency band and with a narrow range of available α . To overcome the current obstacles in the unavailability of FOEs, they are commonly approximated by an RC network for the purpose of performance analysis and design verification by means of simulations or experimental measurements [32] . To approximate a FOE using an RC network, different approaches are described in the open literature, see e.g., [ 33 – 35 ]. However, for each different FOE, the RC network must be redesigned. This further limits the interest of the broader research community in fractionalorder circuits and systems, as individual research groups use their “tuned” FOE that is mainly specified with its fix fractional order α. To obtain FOEs featuring new values of fractional order α without re-designing the “tuned” FOE, the generalized immittance converter (GIC) may be efficiently utilized. Originally, the GIC was and still is used to emulate a classic inductor (and to obtain so called synthetic inductor) using resistors, capacitors, and selected types of active elements, e.g., operational amplifiers [ 36 ], current conveyors [ 37 ], current feedback operational amplifiers [38] , etc. The utilization of GIC in designing factional-order elements was also discussed e.g., in [ 39 – 43 ], where Antoniou’s GIC employing operational amplifiers is used. The approach presented in [ 39 ] enables one to design new FOE with a fractional order between − 2 and 2, but always requires a unique fractional-order element with specific α (i.e., 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8). A comprehensive analysis of opamp-based Antoniou’s GIC, however limited to fractional-order inductor synthesis only, is provided in [ 40 ], similarly as in [ 41 , 42 ] the fractional-order inductor design and its utilization in the frequency filter design is discussed. First in [ 43 ], a more general approach to design FOEs is discussed, where both inductive and capacitive FOEs are used to design a set of new FOEs with a fractional order between − 4 and 4. Note that as the Antoniou’s GIC is always used, the newly obtained FOEs are always grounded. In this paper, we elaborate the efficient utilization of so called “seed” fractionalorder elements featuring fractional order αseed that are employed in a general immittance converter to design a series of fractional-order elements. We partially presented this concept in [ 44 ], where the design of a series of grounded FOEs with fractional order [− 2, 2 ] was presented. Here, we further develop the theory and the design approach to obtain arbitrary and floating FOEs. The structure of the paper is as follows. In Section 2, the theory on fractional-order elements is shortly described. In Section 3, we present the concept of designing a FOE with fractional order α being from the arbitrary range [−n , n] , where n is a positive integer number. Using operational transconductance amplifiers (OTAs) as active elements, we also propose possible implementation of the general immittance converter and use it to design a wide series of floating FOEs. In Section 4, the behavior of the proposed GIC is further analyzed. Taking into account the non-ideal behavior of the active elements, the design rules are discussed to optimize the overall performance of the GIC. Section 5provides post-layout simulations of new FOEs obtained by employing the proposed GIC, whereas the optimization recommendations are also advantageously utilized to broaden the operational frequency band and increase dynamic. To show a practical utilization of the GIC and the design of fractional band-pass filter is also discussed as an example. Finally, Section 6concludes this paper. 2. Theory on Fractional-Order Elements Fractional-order elements are understood to be the simplest electrical elements whose impedance function follows fractional order differential equations and are used as basic building blocks for other fractional-order circuits and systems design. In the open literature, FOEs are also refereed to as constant-phase elements (CPEs) [ 45 ], elements with fractional impedance (EFIs) [ 46 ], or generally fractors [ 39 ] whose impedance in s -domain is defined as: ZF(s) = 1 sα·F, (1) Sensors 2021,21, 1203 3 of 23 where F , called as fractance, is the coefficient of the fractor, and α is generally a real number, called the fractional-order. In frequency domain, the magnitude of a fractor is |ZF|= 1 /(ωαF ) Ω . For positive/negative values of α the magnitude |ZF| is monotonically decreasing/increasing with frequency by 20 ·α dB Ω /dec, whereas the phase angle remains always constant ϕ=−α·90 deg. If 0 <α< 1, the phase angle of the fractor is negative and the fractor is called the fractional-order capacitor (also fractional capacitor, capacitive FOE, or capacitive fractor): ZCα(s) = 1 sα·Cα , (2) where Cα=Fis referred to as pseudo-capacitance or fractional capacitance. For − 1 <α< 0, the phase angle of the fractor is positive and the fractor is called the fractional-order inductor, also referred to as the fractional inductor, inductive FOE, or inductive fractor. The fractional order of the inductive fractor is commonly labeled as β , whereas it may be evident that β=−α: ZLβ(s) = sβ·Lβ, (3) where Lβ=1/Fis the pseudo-inductance or fractional inductance. As presented in [ 33 , 47 ], the fractional capacitor and its pseudo-capacitance Cα may be represented as the equivalent capacitor with capacitance C that features the same impedance at frequency ω0: C=Cα ω1−α 0 , (4) and similarly for the fractional inductor with its pseudo-inductance Lβ , an equivalent inductor with its inductance Lfeaturing the same impedance at frequency ω0can be specified: L=Lβ ω1−β 0 . (5) It may be noted that for α= 0, 1, or − 1, the fractor defined by (1) becomes resistor, capacitor, or inductor, respectively. For |α|> 1, the fractor (1) can be used to describe higher-order immittances, e.g., the frequency dependent negative resistor (FDNR), finding their application in a higher-order frequency filter design [48,49]. 3. General Immittance Converter in FOEs’ Series Design As already discussed in Section 1, it is not necessary to limit the utilization of GIC to design synthetic inductors. The general immittance converter may also be efficiently used in fractional-order element design as shown e.g., in [ 39 ], where the known operational amplifier-based Antoniou’s GIC was employed. Here we further extend the idea of transforming FOEs and provide a concept of efficient design of a series in fractional order α of fractional-order elements by using even single or very a limited number of “seed” FOEs. 3.1. General Immittance Converter Behavior Definition Assume a general function block as shown in Figure 1that is represented by general active/passive network to which general admittances Y i ( i= 1, ..., n ; n being even number) are connected. The general active/passive network may represent arbitrary interconnection of an arbitrary type of active and passive elements and is determined by its parameter g , a Sensors 2021,21, 1203 4 of 23 transcondustance specific for this active/passive network. Let the input admittance ( YIN ) of such a general function block be defined as: [YIN]=1−1 −1 1  n/2 ∏ i=1 Y(2i) n/2 ∏ i=1 Y(2i−1) g. (6) The general admittances Y i ( i= 1, ..., n ) may be represented by any type of passive element, such as conductor (G), inductor (L), capacitor (C), or fractional-order element (FOE), whereas adopting the nomenclature as defined in Section 2, for each passive element, i.e., conductor, inductor, capacitor, and FOE it is possible to claim that its fractional order αi equals to 0, − 1, 1, and αFOE ( − 1 <αFOE < 0 or 0 <αFOE < 1), respectively. Under these assumptions, for the fractional order α defining the phase angle of the input admittance (6) can be written: α= n/2 ∑ i=1 α(2i)− n/2 ∑ i=1 α(2i−1), (7) and the feasible range of fractional order αis defined as [−n,n]. Active/passive network g Y1Y2Y2i-1 Y2iYn-1 Yn YIN ... ... Figure 1. View on general immittance converter as a function block. To better demonstrate the advantageous features of the proposed concept of designing a series in fractional order α of fractional-order elements, let n= 4. Then (6) and (7) simplify to: [YIN]=1−1 −1 1 Y2Y4 Y1Y3 g, (8) and α=α2+α4−α1−α3, (9) respectively. As in practical analog circuit design, classic inductors, and/or inductive fractors are not commonly used, in the further text it is assumed that the general admittances Y i ( i= 1, ..., 4) may be replaced only by conductors ( αi= 0), capacitors ( αi= 1), and/or capacitive FOEs ( αi=αFOE , 0 <αFOE < 1). Now replacing the general admittance Y i ( i= 1, ..., 4) by one of the three assumed types of passive elements, the following set of passive (synthetic) elements observed at the input of the immittance converter and specific with their fractional order αcan be described: •Frequency dependent negative resistor - type I (FDNR-I), α=2, •Fractional FDNR-I, 1 <α<2, •Capacitor C, α=1, •Capacitive FOE, 0 <α<1, •Resistor R, α=0, •Inductive FOE, −1<α<0, •Inductor L, α=−1 •Fractional frequency dependent negative resistor-type II (FDNR-II), −2<α<−1, •FDNR-II, α=−2. Sensors 2021,21, 1203 5 of 23 Note that the feasible range of fractional order α is now [− 2, 2 ] only, which is caused by the fact that neither classic nor fractional inductors are assumed to replace one or more general admittances Yi(i=1, ..., 4). The frequency dependent negative resistor-type I (FDNR-I) is also referred to as the D element (or double capacitor) and features purely real negative resistance that decreases in magnitude with increasing frequency [ 36 ], whereas FDNR-II also exhibits purely real negative resistance, however, its magnitude increases for increasing frequency. Additionally, comparing with [ 39 ], the inductive FOE, fractional FDNR-II, fractional FDNRI, and capacitive FOE, may be referred to as Type-I fractor, Type-II fractor, Type-III fractor, and Type-IV fractor, respectively. Using a general immittance converter allows one to obtain a wide series of new FOEs using a very limited set of “seed” FOEs and their fractional order αseed . As an example, assume a “seed” FOE with its fractional order αseed = 0.2. Using always at most two identical “seed” FOEs and two capacitors together with conductors to replace external admittances Y i ( i= 1, ..., 4) in (8) , then according to (9) 19 unique values of fractional order αfrom the range [−2, 2]are obtained. The specific combinations of external passive elements, i.e., of the conductors, capacitors, and “seed” FOEs, are listed in Table A1. To better comprehend the advantage in utilizing “seed” FOEs, even 51 different values of fractional order α , still from the range [− 2, 2 ] , can be obtained by assuming αseed1 = 0.25 and αseed2 = 0.0625. As a result, for each α , the input admittance YIN (8) features a phase angle from the range [− 180, 180 ] deg as illustrated in Figure 2. The specific combinations of external admittances types defined by their αi is summarized in Table A2. Hence, it may be obvious that using a very limited set of “seed” FOEs, a broad series of new fractional order elements primarily with different fractional order α may be obtained. Furthermore, by adjusting the values of external capacitors ( C ), conductors ( G ), and most preferably also the transcondustance g of the active/passive network it is possible to obtain a generally arbitrary value of the fractance being observed at the input of the GIC. ‒ 180 ‒ 135 ‒ 90 ‒ 45 0 45 90 135 180 arg(YIN)[deg] FDNR-I FDNR-I-1.5 capacitor capFOE-0.5 resistor/conductor indFOE-0.5 inductor FDNR-II-1.5 FDNR-II Figure 2. Feasible phase angles of YIN (8) using up to two seed fractional-order elements (FOEs) with αseed1 =0.25 and αseed2 =0.0625. 3.2. Proposed Implementation of General Immittance Converter To prove our theoretical concept in designing a series of floating fractional-order elements, we also propose possible circuit implementation, whose performance is analyzed in detail in Section 4. To implement the required GIC, the well-known OTAs are used as active elements. Sensors 2021,21, 1203 6 of 23 The OTA, whose circuit symbol is shown in Figure 3, specified with its transcondutance gmis a source of current iOUT controlled by a difference of input voltages v+and v−[50]: iOUT1 =iOUT2 =gm(v+−v−), (10) whereas gmmay commonly be adjusted by an external dc voltage VSET or current ISET. gm + _ OTA ISET/VSET iOUT1 v+ v‒ iOUT2 Figure 3. Schematic symbol of operational transconductance amplifier (OTA). In Figure 4, the novel configuration of a general immittance converter is shown. Taking into account the basic terminal relationship of OTA (10) and performing routine algebraic analysis, the input admittance is determined as: [YIN]=1−1 −1 1  n/2 ∏ i=1 Y(2i) n/2 ∏ i=1 Y(2i−1) n/2+2 ∏ i=1 gm(2i−1) n/2+1 ∏ i=1 gm(2i) . (11) Comparing (11) with (6) , it may be observed that the proposed circuit from Figure 4 fully follows the behavior of a general immittance converter as defined in Section 3.1, whereas for the transconductance git holds: g= n/2+2 ∏ i=1 gm(2i−1) n/2+1 ∏ i=1 gm(2i) . (12) The following beneficial features of the proposed general immittance converter are identified: •Floating fractional-order elements are designed, •Only grounded external admittances are employed, • Electronic tunability of |YIN| is possible by proper adjustment of the transcondutances gmof the active elements, • There is no restriction concerning matching between passive (external) or active elements . gm1 + _ OTA1 gm3 + _ OTA3 gm5 + _ OTA5 gm(2i+3) + _ OTA2i+3 gm2 + _ OTA2 gm4 + _ OTA4 gm(2i+2) + _ OTA2i+2 Y1 Y2 YIN gm(n+3) + _ OTAn+3 gm(n+2) + _ OTAn+2 Yn-1 Yn Y2i-1 Y2i Figure 4. Proposed OTA-based general immittance converter. Sensors 2021,21, 1203 7 of 23 4. Performance Analysis of the Proposed Immittance Converter In theory, using the proposed OTA-based general immittance converter from Figure 4, the feasible range of the fractional order α is [−n , n] , whereas n is generally an arbitrary even integer number. For a more practical design of a series of fractional-order elements, let n= 4. The general immittance converter from Figure 4simplifies to a circuit as shown in Figure 5, whose input admittance according to (11) is specified as: [YIN]=1−1 −1 1 Y2Y4 Y1Y3 gm1gm3gm5gm7 gm2gm4gm6 . (13) For the same reasons as already discussed in Section 3.1, assuming the external admittanaces to be suitably replaced by conductors, capacitors, and capacitive-type “seed” FOEs, the immittance converter from Figure 5is capable of designing a series of fractionalorder elements with the fractional order α in the range [− 2, 2 ] . Once the inductors and fractional inductors are used to replace one or more external admittances, the fractional order range of αwill be [−4, 4]. gm1 + _ OTA1 gm3 + _ OTA3 gm5 + _ OTA5 gm7 + _ OTA7 gm2 + _ OTA2 gm4 + _ OTA4 gm6 + _ OTA6 Y1 Y2 Y3 Y4 YIN Figure 5. Proposed OTA-based general immittance converter for n=4. 4.1. Properties of Used OTA For the purpose of analysis of the real behavior of the proposed GIC from Figure 5, the OTA element designed in the 0.18 µ m TSMC complementary metal-oxide semiconductor (CMOS) process as presented in [ 51 ] is used. As shown in Figure 6, the assumed OTA consists of two differential voltage summation blocks, whereas the inputs of the first one serve as differential voltage inputs of OTA and the inputs of the second summation block are used to apply the control voltage VSET . The outputs of the summation blocks are multiplied mutually and amplified with the constant k resulting in two output currents with the same magnitude but shifted in phase by 180 deg. Σ + _ Σ + _ × VSET k OTA v+ v‒ iOUT2 iOUT1 Figure 6. Behavioral structure of the used OTA. Sensors 2021,21, 1203 8 of 23 Hence, the following relation is valid for the output currents of the OTA from Figure 6 : iOUT1 =iOUT2 =k·VSET(v+−v−), (14) where k=2·10−3A/V2and defines the transmission of the block kin Figure 6. In accordance with (10), the relation between gmand VSET is given by: gm=k·VSET. (15) The dependence of gm on VSET of the OTA from Figure 6obtained by Cadence simulations is given in Figure 7(solid red line). It may be observed that (15) is valid for VSET in the range 0 to 0.5 V and proves the possibility to electronically set gm between 0 and 1 mS, whereas the maximum absolute error is 0.02 mS (Figure 7; dashed blue line). Detailed analysis of the OTA and discussion of its parameters is given in [ 51 ]. Here we further aim to analyze the influence of real properties of OTAs on the overall performance of the proposed GIC. ‒ 0.16 ‒ 0.12 ‒ 0.08 ‒ 0.04 0 0.04 0.08 0.12 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 0.1 0.2 0.3 0.4 0.5 0.6 Absolute error of gm[mS] gm[mS] VSET [V] gm(Vset) - theory (15) gm(Vset) - simulation Δgm - absolute error of gm gm(VSET)–theory (15) gm(VSET)–simulation Δgm–absolute error of gm Figure 7. Dependence of the transconductance gm on VSET (solid red line) of the OTA element and its absolute error (dashed blue line). In an ideal case the internal impedance of OTA input and output terminals is infinity. Considering a real OTA, its properties are commonly modeled by resistances and capacitances connected between each of the terminals and ground. Considering these OTA parasitic properties the proposed GIC from Figure 5can be redrawn as seen in Figure 8 . Assuming that all OTAs in the circuit are the same, the parasitic conductors G P symbolize a parallel combination of the input and output internal resistances of OTA. Similarly, the parasitic capacitors C P represent a parallel combination of OTA input and output internal capacitances. Based on [ 51 ], their approximate values used in this analysis are GP≈ 1 /( 346 k Ω) = 2.89 µ S and CP≈ 0.28 pF. Note that the parasitic elements in the node E express the properties of twice the number of OTAs, thus their conductance and capacitance are double compared to the other parasitic elements, i.e., 2 GP and 2 CP . As the overall input port of the GIC labeled as F is differential, the terminal parasitic elements G P and C P are connected in series here (through ground) and thus these parasitics are considered to be GP/ 2 and CP/ 2. If the GIC is connected as single-ended, i.e., one of its input terminals is grounded, the values of the parasitic elements of the input node should be considered to be GPand CP. Sensors 2021,21, 1203 9 of 23 gm1 + _ OTA1 gm3 + _ OTA3 gm5 + _ OTA5 gm7 + _ OTA7 gm2 + _ OTA2 gm4 + _ OTA4 gm6 + _ OTA6 YIN Y1 GP CP Y2 GP CP Y3 GP CP Y4 GP CP2GP 2CP GP/2 CP/2 A B C DE F Figure 8. Proposed general immittance converter with OTA parasitic properties. 4.2. Influence of OTA Parasitics and Optimization of GIC Performance To solely evaluate the influence of OTA parasitic properties, as well as FOEs, resistors, and capacitors used to replace the admittances Y1, Y2, Y3, and Y4are assumed to be ideal. For clarity, the nodes and input port, where the modeled parasitics are present are labeled by circled letters A to F in Figure 8. 4.2.1. Nodes A, B, C, D As already mentioned in Section 3.1, the external admittances Y 1 , Y 2 , Y 3 , and Y 4 connected to these nodes are expected to be replaced by conductors (i.e., resistors), classic capacitors, or capacitive FOEs. In case of conductors, the parallel parasitic conductance GP is added, but it is usually very small and can be neglected. The capacitance CP is also in parallel and considering operational conductance of the order of milisiemens (mS), the parasitic effect of CP becomes significant at a very high frequency (above approx. 500 MHz), and thus can also be neglected. On the other hand, the replacement of external admittances by capacitors or capacitive FOEs is worth analyzing. At low frequencies these elements have a very low admittance magnitude and the parasitic conductance GP may prevail. In case of fractor with fractional order αand fractance Fthis happens below the frequency: ωGP ≈GP F1 α, (16) as illustrated by asymptotic admittance magnitude plot in Figure 9. ω |Y| GP ωαF ωGP Figure 9. Magnitude frequency characteristics of the working and parasitic admittances of the nodes A to D. Note that (16) is also valid for a classic capacitor when considering α= 1 and a capacitance equal to F . It follows that for a higher value of F correct operating range is extended to lower frequencies. Once for a specific F sufficiently low ωGP is not provided, the parasitic conductance GP can be reduced, e.g., by connecting in parallel a negative conductance as described in Section 4.3 in detail. Using this approach, i.e., the negative conductance, the frequency ωGP can theoretically be shifted to very low values. However, Sensors 2021,21, 1203 16 of 23 1E-08 0.0000001 0.000001 0.00001 0.0001 0.001 0.01 0.1 10 100 1 10 100 1000 10,000 100,000 1,000,000 |YIN| [mS] Frequency [Hz] FDNR-I FDNR-I_1.75 FDNR-I_1.5 FDNR-I_1.25 capacitor capFOE_0.75 capFOE_0.5 capFOE_0.25 indFOE_0.25 indFOE_0.5 indFOE_0.75 inductor FDNR-II_1.25 FDNR-II_1.5 FDNR-II_1.75 FDNR-II Ideal results 100,000 10,000 1000 100 10 1 0.1 0.01 0.001 0.0001 0.00001 (a) ‒ 180 ‒ 135 ‒ 90 ‒ 45 0 45 90 135 180 1 10 100 1000 10,000 100,000 1,000,000 arg (Y IN ) [deg] Frequency [Hz] FDNR-I FDNR-I_1.75 FDNR-I_1.5 FDNR-I_1.25 capacitor capFOE_0.75 capFOE_0.5 capFOE_0.25 indFOE_0.25 indFOE_0.5 indFOE_0.75 inductor FDNR-II_1.25 FDNR-II_1.5 FDNR-II_1.75 FDNR-II Ideal results (b) Figure 16. Simulation results of proposed GIC with OTA parasitics: ( a ) Magnitude responses and ( b ) phase responses. 5.3.1. Optimization Example for α=1.75 In this case, the fractional FDNR-I is obtained at the input of the GIC, i.e., port F, whose fractance is FIN = 22.55 nFs 0.75 . Decreasing frequency the admittance magnitude also decreases until the parasitic conductance GP/ 2 starts to prevail. This happens at a lower cut-off frequency at approximately 23.8 Hz (Figure 16a) generally determined by (16) , where GP was substituted by GP/ 2 (note that (16) is originally valid for nodes A, B, C, D where parasitic conductance GPis present). Within optimization, using the circuit from Figure 12b to compensate the parasitic conductance at port F, the lower cut-off frequency is decreased down to 1 Hz to maintain a sufficient margin to frequency 10 Hz due to soft admittance phase transition (Figure 16b) . To reach this new lower cut-off frequency, the input conductance GCOMP was set to − 1.439 µ S, whereas according to (23) compensation transconductance gmC equals to 2.885 µS. Sensors 2021,21, 1203 17 of 23 The upper cut-off frequency is determined by the parasitics of the node E as described in Section 4.2.2. To increase this upper cut-off frequency it is necessary either to increase the product gm2gm4gm6 or to decrease F2F4 (in this case capacitances C2 and C4 as α2=α4= 1). Since the transconductances gm of all OTAs are already set to 1 mS (maximum according to Figure 7), the product gm2gm4gm6 cannot be further increased. Hence, having selected the upper cut-off frequency to be 100 kHz, using (19) new capacitances C2 and C4 (considering them equal) were determined to be 20.9 nF. Note that here the margin from the required 100 kHz was not considered, as the damping in the node E is low and the admittance phase shows the transition in a narrow band. Moreover, the excessive increase of the upper cut-off frequency in node E would lead to lower capacitances C2 and C4 and undesirable deterioration of the cut-off frequency in nodes B and D. Within the optimization of the upper cut-off frequency, the ratio gm2gm4gm6/(F2F4) was increased. Hence, to keep the original value of the input fractance FIN unaffected, according to general formula (13) , the ratio G1Fseed1/(gm1gm3gm5gm7) must decrease. As again the transconductances gm of all OTAs are already set to their maximum values (i.e., 1 mS) and the “seed” FOE is not expected to be modified, the only possibility is to decrease G1to 17.3 µS. 5.3.2. Optimization Example for α=−1.75 For this case, the fractional FDNR-II with fractance 4434 Fs −2.75 is obtained at the input of the GIC. The admittance magnitude decreases with increasing frequency, where the parasitics at port F define the upper cut-off frequency of approximately 42 kHz (Figure 16a) generally determined by (16) , where again GP was substituted by GP/ 2. The only solution to increase the upper cut-off frequency is to reduce the parasitic conductance of the port F by using the compensation circuit from Figure 12b. In this case it is possible to decrease the port F parasitic conductance almost to zero, thus the transconductance of the compensation circuit is set slightly lower than GP, i.e., gmC =2.888 µS. To reduce the lower cut-off frequency, it is necessary to increase capacitances C1 and C3 in the nodes A and C according to (16) . The optimized lower cut-off frequency is set to 1 Hz to have again sufficient margin to 10 Hz due to soft phase transition. Hence, the new value of capacitances C1and C3is 460 nF. Within the optimization of the lower cut-off frequency the product C1C3 was increased. Hence, the ratio gm2gm4gm6/(G2Fseed1gm1gm3gm5gm7) must decrease according to general formula (13) to keep the original value of the input fractance FIN unchanged. For this purpose, the transconductances gm2 , gm4 , and gm6 were set to 0.493 mS, whereas gm1 , gm3 , gm5 , gm7 , G2 , and mainly Fseed1 are kept the same. As transconductances gm2 , gm4 , and gm6 were changed, it is necessary to check the upper cut-off frequency of the node E if it is large enough. According to (20) the value of f2CP is 4.2 MHz, which is much more than the required upper cut-off frequency of 100 kHz. Hence no further optimization is needed. For the both optimized examples as described in Sections 5.3.1 and 5.3.2, the resulting admittance magnitude and phase frequency characteristics are shown in Figure 17 along with the characteristics of the non-optimized GIC taken from Figure 16. It is evident that the optimized circuit provides a higher frequency bandwidth of the admittance characteristics covering the required 4 decades. The fractional FDNR-I (blue lines) reaches an upper cut-off frequency almost equal 100 kHz as considered during the optimization. The lower cut-off frequency reached approximately 5 Hz, which is higher than the projected value of 1 Hz, however, here the GIC function is affected by parasitics of multiple nodes and also the “seed” FOE shows a higher error (see Figure 14). The fractional FDNR-II (red lines) has also been optimized successfully. Its upper cut-off frequency is around 100 kHz and lower cut-off frequency is 0.9 Hz. Additionally, as seen from Figure 17a, the dynamic range of the admittance magnitude has also increased thanks to the optimization. Sensors 2021,21, 1203 18 of 23 1E-08 0.0000001 0.000001 0.00001 0.0001 0.001 0.01 0.1 10 100 1 10 100 1000 10,000 100,000 1,000,000 |Y IN | [mS] Frequency [Hz] FDNR-I_1.75 FDNR-I_1.75-compensated FDNR-II_1.75 FDNR-II_1.75-compensated Ideal results 100,000 10,000 1000 100 10 1 0.1 0.01 0.001 0.0001 0.00001 (a) ‒ 225 ‒ 180 ‒ 135 ‒ 90 ‒ 45 0 45 90 135 180 225 270 315 1 10 100 1000 10,000 100,000 1,000,000 arg (Y IN ) [deg] Frequency [Hz] FDNR-I_1.75 FDNR-I_1.75-compensated FDNR-II_1.75 FDNR-II_1.75-compensated Ideal results (b) Figure 17. Simulation results of proposed GIC with compensated OTA parasitics: ( a ) Magnitude responses and (b) phase responses. 5.4. Fractional Band-Pass Filter Design To also show the practical utilization of the proposed GIC and the fractional-order element that are being obtained at its input, a fractional band-pass filter as presented in Figure 18 is designed, as an example. C FOFDNR-I R V1V2 Figure 18. Passive band-pass filter using fractional FDNR-I element. The transfer function of the filter from Figure 18 is determined as: TFFBP(s) = asα−1 sα+asα−1+b, (24) where a= 1 /(CR) and b= 1 /(FR) , whereas F is the fractance of fractional FDNR-I (FOFDNR-I) with its fractional order being in the range 1 <α<2. Sensors 2021,21, 1203 19 of 23 According to (24) , the band-pass filter features stop-band attenuation of + 20 α dB/dec and −20 dB/dec for frequencies lower and higher than the pole frequency, respectively. For Butterworth approximation of fractional-order band-pass filters, based on [ 55 ] the coefficients aand bare determined as: a=ω0(0.7141 −1.1632α+0.7516α2), (25) and b=ωα 0(1.5464 −1.3562α+0.5357α2), (26) where ω0is the angular pole frequency of the filter. Assuming the FOFDNR-I with its fractance F= 22.55 nFs 0.75 and fractional order α= 1.75, as is obtained at the input of GIC and using (24) – (26) , the values of resistor and capacitor of the filter from Figure 18 can be determined as R= 21.88 Ω and C= 742 nF for pole frequency f0=10 kHz. ‒ 80 ‒ 70 ‒ 60 ‒ 50 ‒ 40 ‒ 30 ‒ 20 ‒ 10 0 1 10 100 1000 10,000 100,000 1,000,000 Magnitude [dB] Frequency [Hz] BP filter with order 1.75 BP filter with order 1.75-compensated Ideal results (a) ‒ 180 ‒ 90 0 90 180 1 10 100 1000 10,000 100,000 1,000,000 Phase shift [deg] Frequency [Hz] BP filter with order 1.75 BP filter with order 1.75-compensated Ideal results (b) Figure 19. Simulation results of fractional band-pass filter from Figure 18: ( a ) Magnitude responses, and (b) phase responses. The magnitude and phase frequency responses of the band-pass filter reached by simulations are shown in Figure 19 and compared to ideal behavior. Within simulations, the FOFDNR-I was assumed to be implemented prior and after the GIC performance optimization as discussed in Section 5.3.1. From the simulation results it can be seen that Sensors 2021,21, 1203 20 of 23 the filter follows the ideal behavior very well, mainly for the optimized design of the required FOFDNR-I (solid lines). The proper behavior of the filter may be observed in four decades, which corresponds to optimized GIC performance and even the bandwidth of the initial “seed” FOEs. The most significant differences can be seen in the results of the non-optimized circuit above pole frequency, where a greater slope of attenuation was achieved. This is caused by parasitics in node E of the GIC used, which manifest themselves at a frequency of 10 kHz, as described before in Section 5.3.1. 6. Conclusions In this paper we presented the concept of an efficient design of fractional-order element series in fractional order α using a very limited count of initial FOEs, here referred to as “seed” FOEs. The proposed concept is powerful and significantly helps to overcome the current obstacle of commercial unavailability of FOEs and was based on the utilization of general immittance converter, in addition a novel general OTA-based implementation was also proposed. To show the advantageous features of the proposed concept, as an example two “seed” FOEs with fractional orders 0.25 and 0.0625 were implemented to design a series of new 51 FOEs with unique fractional order in the range [− 2, 2 ] . The “seed” FOEs were approximated using the Valsa RC network in four decades featuring a very low absolute error. Comprehensive analysis of the designed circuit was given to enable its performance optimization. Using OTAs designed in 0.18 µ m TSMC CMOS technology, Cadence Virtuoso post-layout simulation results were presented which prove the operability of the proposed GIC, whereas the performance optimization was also shown on two examples to extend the operational frequency range. Finally, a fractional-order band-pass filter was also designed, which successfully utilizes the floating fractional FDNR-I with its fractional order α= 1.75. Author Contributions: Conceptualization, J.K. and D.K.; methodology, J.K., D.K., and J.D.; validation, N.H.; formal analysis, D.K., J.D., and J.K.; writing—original draft preparation, J.K., D.K., J.D., N.H.; writing—review and editing, J.K., D.K., J.D., and N.H.; project administration, J.K.; funding acquisition, J.K. All authors have read and agreed to the published version of the manuscript. Funding: The research results described in this paper are funded by the Czech Science Foundation, project No. 19-24585S. Institutional Review Board Statement: Not applicable. Informed Consent Statement: Not applicable. Acknowledgments: The research results described in this paper are supported by the Czech Science Foundation, project No. 19-24585S. For the research, the infrastructure of the SIX Research Center was used. Conflicts of Interest: The authors declare no conflict of interest. Abbreviations The following abbreviations are used in this manuscript: CMOS Complementary metal-oxide semiconductor CPE Constant-phase element EFI Elements with fractional impedance FDNR Frequency dependent negative resistor FOE Fractional-order element FOFDNR Fractional order frequency dependent negative resistor GIC General immittance converter OTA Operational transconductance amplifier RC resistor-capacitor TSMC Taiwan semiconductor manufacturing company Sensors 2021,21, 1203 21 of 23 Appendix A. Variant Combinations of Admittances Yiand Their αi(i=1, ..., 4) vs. Final Fractional Order αof ZIN Table A1. Combinations of admittances Yi, their αiand the unique fractional order αof ZIN for αseed =0.2. α1α2α3α4α 0 1 0 1 2.0 0.2 1 0 1 1.8 0.2 1 0.2 1 1.6 0 1 0 0.2 1.2 0 1 0 0 1.0 0.2 1 0 0 0.8 0.2 1 0.2 0 0.6 0 0.2 0 0.2 0.4 0 0.2 0 0 0.2 0 0 0 0 0.0 0.2 0 0 0 −0.2 0.2 0 0.2 0 −0.4 1 0.2 0 0.2 −0.6 1 0.2 0 0 −0.8 1000−1.0 1 0 0.2 0 −1.2 1 0.2 1 0.2 −1.6 1 0.2 1 0 −1.8 1010−2.0 Table A2. Combinations of admittances Yi , their αi and the unique fractional order α of YIN for αseed1 = 0.25 and αseed2 =0.0625. α1α2α3α4α α1α2α3α4α 0 1 0 1 2.00 0.0625 0 0 0 −0.0625 0 1 0.0625 1 1.9375 0.0625 0 0.0625 0 −0.125 0.0625 1 0.0625 1 1.875 0.25 0 0 0.0625 −0.1875 0 1 0.25 1 1.75 0.25 0 0 0 −0.25 0.0625 1 0.25 1 1.6875 0.25 0 0.0625 0 −0.3125 0.25 1 0.25 1 1.50 0.25 0.0625 0.25 0.0625 −0.375 0 1 0 0.25 1.25 0.25 0 0.25 0.0625 −0.4375 0 1 0.0625 0.25 1.1875 0.25 0 0.25 0 −0.50 0.0625 1 0.0625 0.25 1.125 1 0.25 0.0625 0.25 −0.5625 0 1 0 0.0625 1.0625 1 0.0625 0 0.25 −0.68705 0 1 0 0 1.00 1 0 0 0.25 −0.75 0 1 0.0625 0 0.9375 1 0 0.0625 0.25 −0.8125 0.0625 1 0.0625 0 0.875 1 0.0625 0 0.0625 −0.875 0 1 0.25 0.0625 0.8125 1 0 0 0.0625 −0.9375 0 1 0.25 0 0.75 1 0 0 0 −1.00 0.0625 1 0.25 0 0.6875 1 0 0.0625 0 −1.0625 0.25 1 0.25 0.0625 0.5625 1 0.0625 0.25 0.0625 −1.125 0 0.25 0 0.25 0.50 1 0 0.25 0.0625 −1.1875 0 0.25 0.0625 0.25 0.4375 1 0 0.25 0 −1.25 0.0625 0.25 0.0625 0.25 0.375 1 0.25 1 0.25 −1.50 0 0.25 0 0.0625 0.3125 1 0.0625 1 0.25 −1.6875 0 0.25 0 0 0.25 1 0 1 0.25 −1.75 0 0.25 0.0625 0 0.1875 1 0.0625 1 0.0625 −1.875 0 0.0625 0 0.0625 0.125 1 0 1 0.0625 −1.9375 0 0.0625 0 0 0.0625 1 0 1 0 −2.00 0 0 0 0 0.00 Sensors 2021,21, 1203 22 of 23 References 1. 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