Reliability of Logic-in-Memory Circuits in Resistive Memory Arrays

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. XX, NO. XX, XXXX 2020 1 Reliability of Logic-in-Memory Circuits in Resistive Memory Arrays Tommaso Zanotti, Student Member, IEEE, Cristian Zambelli, Member, IEEE, Francesco Maria Puglisi, Member, IEEE, Valerio Milo, Member, IEEE, Eduardo P´ erez, Mamathamba K. Mahadevaiah, Oscar G. Ossorio, Christian Wenger, Paolo Pavan, Senior Member, IEEE, Piero Olivo, and Daniele Ielmini, Fellow, IEEE Abstract—Logic-in-Memory (LiM) circuits based on RRAM devices and the material implication logic are promising candidates for the development of low-power computing devices, that could fulfill the growing demand of distributed computing systems. However, these circuits are affected by many reliability challenges that arise from device non-idealities (e.g., variability) and the characteristics of the employed circuit architecture. Thus, an accurate investigation of the variability at the array level is needed to evaluate the reliability and performance of such circuit architectures. In this work, we explore the reliability and performance of SIMPLY (i.e., a recently proposed LiM architecture with improved reliability and performance) on two 4 kbits RRAM arrays based on different resistive switching oxides integrated in the BEOL of the 0.25 µm BiCMOS process. We analyze the trade-off between reliability and energy consumption of SIMPLY architecture by exploiting the results of an extensive array-level variability characterization of the two technologies. Finally, we study the worst-case performance of a full adder implemented with the SIMPLY architecture and benchmark it on the analogous CMOS implementation. Index Terms—RRAM, BEOL, SIMPLY, Logic-in-Memory, Full adder. I. INTRODUCTION Today, there are roughly 17 billion devices at the edge, which causes massive and ever-growing data exchange over communication networks. In this context, edge computing has been identified as a promising solution to relax data transfer and energy consumption limitations, providing advantages for Internet of Things (IoT) applications, smart cities and smart industries, Artificial Intelligence (AI), 5G/6G communications. However, todays ultra-low power hardware solutions are still affected by the von Neumann bottleneck (VNB) [1]–[3]. Specifically, VNB is the time- and energy-demanding process of data transfer between CPU and memory chips, and is the main showstopper for edge computing solutions. As recently suggested in [2], [4], [5], Logic-in-Memory (LiM) circuits that merge together data storage and computation could bypass VNB, thus minimizing the energy and time needed to execute logic functions. Among the most promising solutions, LiM circuits based on resistive random access memory (RRAM) and on the material implication logic (IMPLY) This work was supported in part by the European Research Council (ERC) under the European Union’s Horizon 2020 research and innovation programme (Grant Agreement No. 648635) and in part by the German Research Foundation (DFG) in the frame of research group FOR2093. T. Zanotti, F.M. Puglisi and P. Pavan are with Dipartimento di Ingegneria ”Enzo Ferrari”, Universit´ a di Modena e Reggio Emilia, 41125 Modena, Italy. (e-mail: [email protected]) C. Zambelli and P. Olivo are with Dipartimento di Ingegneria, Universit´ a degli Studi di Ferrara, 44122 Ferrara, Italy. V. Milo and D. Ielmini are with Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano and IU.NET, 20133 Milano, Italy. E. Perez, M. K. Mahadevaiah, and Ch. Wenger are with IHP-Leibniz- Institut f¨ur innovative Mikroelektronik, 15236 Frankfurt (Oder), Germany. Ch. Wenger is also with BTU Cottbus-Senftenberg, 01968 Cottbus, Germany. O. G. Ossorio is with Dpto. Electricidad y Electronica, Universidad de Valladolid, 47011 Valladolid, Spain. offer significant advantages by leveraging on the small footprint of RRAMs, on their BEOL integration potential, and on the fact that implication logic is complete, i.e., all possible logic functions can be defined by a sequence of few core operations [2], [4]–[6], namely IMPLY and FALSE operations. However, the reliability of such operations and of the material implication logic circuit tightly depends on the non-idealities of the devices, especially variability [5], [6], and on the characteristics of the employed circuit architecture [5], [6]. Thus, evaluating the benefit of introducing the LiM paradigm in edge computing requires an accurate investigation of the variability at the array level. Yet, a clear array-level analysis and demonstration of functionality of RRAM-based LiM solutions is still missing. In this work, we study the performance and feasibility of a recently proposed smart IMPLY (SIMPLY) [2], [5] LiM paradigm on two 4 kbits RRAM arrays with different resistive switching oxides integrated in the BEOL of the 0.25 µm BiCMOS process. Previous works [2], [5], restricted the evaluation of the performance of SIMPLY to RRAM technologies taken from the literature for which only little information regarding cycle-to-cycle (C2C) and device-to-device (D2D) variability is available. Here we exploit the extensive arraylevel variability characterization of the two RRAM technologies to study the performance of the SIMPLY architecture by evaluating the trade-off between reliability and energy consumption. In addition, we estimate the worst-case energy consumption of a 1-bit full adder (FA) implemented in the SIMPLY architecture, and benchmark it against CMOS implementations. Results show the SIMPLY implementation of the 1-bit FA outperforms the CMOS one by more than two orders of magnitude, when the VNB is considered, with significant improvement margins left. II. SIMPLY LOGIC-IN-MEMORY ARCHITECTURE The revived interest in RRAM technology arises from the possibility of storing and manipulating the information in the same place, by realizing LiM paradigms in which information is not stored as voltage at circuit nodes (like in CMOS logic) but as the resistance value of RRAM devices (HRS = logic 0 and LRS = logic 1). Specifically, the paradigm based on the material implication logic is among the most effective since it is ”complete”, thus all the possible logic operations can be implemented as a sequence of two operations, namely the FALSE (i.e., the reset of a single device) and the IMPLY. In the typical arrangement, the IMPLY operation is executed by simultaneously pulsing two devices (Pand Q, holding the input bits) with two different voltages (labeled VSET and VCOND)in such a way that Pholds its state and Qchanges state according to the truth table in Fig.1a. However, as thoroughly analyzed in [4], [6], this arrangement suffers from several issues, such as high energy consumption, the degradation of the logic states stored in the devices, and a strong sensitivity to driving voltage variations [6]. Recently, the SIMPLY architecture was introduced to overcome the aforementioned issues [2], [5]. The SIMPLY architecture is sketched in Fig.1b, and can be easily implemented in a 1T-1R array by shunting together the bottom electrodes of a group of RRAM devices. The © 2020 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other work 2 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. XX, NO. XX, XXXX 2020 Fig. 1. (a) Truth table of the PIMPLY Qoperation. The blue rectangle highlights that the state of Qchanges (Q′) only when the input combination is P=Q=0. (b) Schematic of SIMPLY architecture on a RRAM array. (c) Read margin (RM) definition considering ideal devices. series transistor is appropriately biased to act as the resistor RG. The IMPLY operation is performed by: i) applying a small Vread voltage pulse (200 mV in this work) to both Pand Q[2], [5]; ii) comparing the voltage at node N(VNin Fig.1b) against a threshold (VT H ) to determine if P=Q=0; iii) pulse VSET on Qkeeping the driver of Pat high impedance only if P=Q=0. In principle, the condition P=Q=0 is easy to detect since VNis lower in this case than in all other cases, ensuring a sufficient read margin (RM), defined as in Fig.1c. When considering ideal devices, RM is a deterministic quantity dependent on the memory window (i.e., the ratio of HRS to LRS resistance), Vread, and RG. However, the combined effect of D2D and C2C variability, Random Telegraph Noise (RTN), driving voltage variations, and process tolerances results in a relatively wide distribution of RM, potentially impairing the circuit functionality. Therefore, the circuit reliability is tightly coupled to the intrinsic variability of the RRAM technology exploited in its integration, and its statistical characterization allows verifying the reliability level that can be achieved by the proposed LiM circuit when implemented in the RRAM technologies under study. III. VARIABILITY CHARACTERIZATION ON RRAM ARRAYS To statistically assess both the D2D and the C2C variability, we performed electrical characterization measurements on the 4 kbits 1T-1R arrays whose architecture is described in [7]. We remind that the array is based on the 0.25 µm BiCMOS process from IHP and that the select transistor in the 1T-1R cells is an n-MOS with W = 1.14 µm and L = 0.24 µm. The transistor allows modulating the compliance current ICby tuning VGduring operations, thus enabling a tight control of the cell conductance and enhanced power-control features in LiM circuits. Fig. 2 shows the IDS -VDS characteristics of a transistor in the array exposing the different IC. The memristive element is integrated during BEOL on top of the second metal level (M2 - in series with drain) featuring a 600 ×600 nm2 area. To provide an exploration of the RRAM technology impact on the LiM circuit, we considered two different memristive stacks integrated in separated arrays, namely a TiN/Ti/HfOx/TiN and a TiN/Ti/Hf1−xAlxOy/TiN structure. Their process characteristics can be retrieved in [8]. Resistive switching of the memristive element is enabled for all the cells in the array through a Forming operation which consists of the application of the ISPVA algorithm for best yield [9] with duration tp= 1 µs and a top electrode voltage VT E from 2 V to 5 V in steps of 10 mV. Reset operation is then performed to reach HRS by using a single pulse gate voltage VG= 2.8 V to minimize transistor resistance and a source voltage VS= 1.8 V. Same pulse duration is considered. We would like to point that such tpis chosen to simplify the requirements of the measurement setup, although the functionality of the two RRAM technologies was also proven with tp= 50 ns RRAM VG VS VTE VD IDS 1T 1R Fig. 2. 1T-1R cell’s architecture (left) and IDS -VDS characteristics of the transistor exploited for ICextraction at different VG(right). Fig. 3. (a) Demonstration of the functionality of an RRAM array based on Hf1−xAlxOywhen tP= 50 ns. Similar results can be obtained for HfOxarrays. Adapted from [10]. (b) CDF of the HRS extracted from the 4 kb arrays evidencing the bound for LiM application at 40 kΩ. [10] (see Fig. 3a). The result of the Reset operation on the 4 kbits array allows extracting the HRS bound dictated by the chosen RRAM technology for the LiM target application. As shown in Fig. 3b, we consider 40 kΩfor both memristive stacks. It is worth to mention that a higher HRS resistance results in a lower power consumption of LiM circuit, so we consider the former value as a worst-case condition that allows speculating on the performance and reliability limits. Concerning the Set operation, we used a VT E = 1.2 V and a single pulse duration tp= 1 µs associated with four different VGvalues from 1 V to 1.6 V in 200 mV steps. This allows a tuning of the LRS on four levels (L1to L4) devising the ICset by the transistor, while providing a strategy for power consumption reduction policies to be applied on LiM circuits. The LRS read currents (Iread) measured with a VT E = 200 mV for L1-L4correspond approximately to 10 µA, 20 µA, 30 µA, and 40 µA. Different LRS levels come with different variability characteristics. Fig. 4 shows a characterization study of the variability for levels L1- L4of both RRAM technologies. In the figure, the standard deviation σRfor the C2C and D2D distributions is plotted as a function of the median device resistance indicated as R. Variability data were collected for a subset of 1024 1T-1R devices (i.e., a block of 16 wordlines set with the same LRS level) integrated in the 4 kbits test vehicles and for 1000 consecutive Set/Reset cycles. The cycling routine is performed considering the proper VGfor the Set operation in each subset. As it can be seen, the C2C variability dominates over the D2D for all LRS levels following the universal trend for σRwhich is proportional to R2, as in [11], [12]. However, the D2D variability is the one with the highest σRabsolute values, thus being critical for the performance of the LiM circuits like those in this work. Overall, Hf1−xAlxOymaterial displays a better control of the D2D and C2C variability as demonstrated by the lower scatter of the < σR;R > points in the plots. LRS level L1has however a higher C2C σR compared to that of HfOx. IV. RELIABILITY OF SIMPLY IN RRAM ARRAYS The results of the variability characterization in Section III are exploited to verify the reliability and the energy efficiency of the ZANOTTI et al.: RELIABILITY OF LOGIC-IN-MEMORY CIRCUITS IN RESISTIVE MEMORY ARRAYS 3 Fig. 4. Standard deviation σRof the resistance as a function of the median resistance Rfor HfOx(left) and Hf1−xAlxOyRRAM technologies (right), respectively. SIMPLY architecture. Note that: i) the only requirement for a reliable circuit operation of the SIMPLY architecture is that a sufficient RM is available at the input of the comparator in all cases, even in the presence of variability; ii) the variability characterization in Section III is performed at the array level, natively including contributions from the device (C2C, D2D and RTN) and from the non-idealities of the peripheral circuits (e.g., possible variations of Vread). This makes RM a comprehensive metric of the circuit reliability. Indeed, circuit implementations that result in higher RMs are more reliable and allow using simpler comparator or sense amplifier designs, though more complex designs can be used for smaller RMs. To estimate the RM and compare the performance of the two RRAM technologies, we used the C2C and D2D joint variability data to compute the distributions of VNwhen P=Q=0 and when P6=Qfor both the technologies and each LRS level (see Fig.5). The joint probability distribution of LRS for each technology and Iread was estimated by combining together 100 random samples for each < σR;R > pair of Fig.4. To identify the worst-case RM that allows evaluating the performance and reliability limits, we assume HRS fixed at the worstcase of the HRS distribution (RHRS = 40 kΩfor both technologies, Fig.3) and thus VN(P=Q=0) is constant for each technology and LRS level and determined by the value of RG(see Fig.1a). The optimal RGvalue maximizing RM for each technology and LRS level was chosen as: RG=rR−1 LRS,MAX +R−1 HRS,MAX −1·RHRS,MIN 2(1) where RLRS,MAX is the µ+3σvalue of the joint LRS distribution, and RHRS,MIN and RHRS,MAX are the µ±3σvalues of the HRS distribution, respectively (RHRS,MIN =RHRS,MAX = 40 kΩin this case). As shown in Figs. 5 and 6a, RM grows with Iread and the two RRAM technologies show comparable reliability at the same LRS level, except at Iread = 10 µA where HfOxdevices guarantee a quite larger RM than Hf1−xAlxOydevices. This stems from the lower C2C variability of HfOxdevices at low Iread, which leads to a smaller tail of L1as shown in Fig.4. To compare the reliability metric in Fig.6a to the energy efficiency performance, we report in Fig.6b the worst-case energy consumption of the read step of SIMPLY operation (averaged over the four possible input configurations) at different Iread. As expected, the energy per operation increases with Iread, establishing a trade-off between energy efficiency and reliability. No relevant differences between the two technologies are observed. V. LIMFULL ADDER IMPLEMENTATION To benchmark the performance of the SIMPLY architecture on more complex operations, we designed a 1-bit ripple carry full adder (FA) with the two RRAM technologies and estimated the worst-case performance. The FA was implemented with 8 RRAM devices performing the sequence of operations reported in [2], which TABLE I 1-BIT FULL ADDER ENERGY PER OPERATION (INDICATING MIN - MAX RANGE)VS Iread WITH tp= 1 µs Iread Read Write FA 10 µA (2.4 - 2.6) ·10−11 J (5.1 - 5.6) ·10−10 J (5.3 - 5.8) ·10−10 J 20 µA (3.2 - 3.5) ·10−11 J (1.0 - 1.1) ·10−9J (1.1 - 1.2) ·10−9J 30 µA (3.9 - 4.2) ·10−11 J (1.7 - 1.8) ·10−9J (1.7 - 1.9) ·10−9J 40 µA (4.4 - 4.8) ·10−11 J (2.3 - 2.5) ·10−9J (2.4 - 2.6) ·10−9J Fig. 5. (a)-(b) Distribution of VNdue to C2C and D2D variability, when P=Q=0 (blue area) and P6=Q(orange area) for the SIMPLY operation for different Iread and RRAM technology. Only the worst-case (i.e., lowest resistance value due to variability) HRS resistance is considered. The read margins (RM black arrows) and the threshold voltages (VT H dashed red) for the comparator are evidenced. Black whiskers indicate the extreme points of the distributions. Red crosses indicate outliers. VNwhen P=Q=1 is always much higher than in all other cases (thus is not reported in these box plots). Fig. 6. (a) Worst-case RM (-3σdeviation from the mean of the RM distribution due to variability) for the two different RRAM technologies and different Iread values. The inset shows the relative difference between the RM obtained with HfOxand Hf1−xAlxOydevices. (b) Worst-case energy consumption of the read operation during SIMPLY operation for HfOxand Hf1−xAlxOyRRAM technologies at different Iread values. It is computed as the average of the worst-case energy consumption (+3σdeviation from the mean of the energy distribution due to variability) of each input configuration. includes 28 steps of core operations (18 IMPLY and 10 FALSE). During a FA cycle, the energy consumption will also depend on the configuration of input bits, since it dictates the number of reset (during FALSE), set (during IMPLY when P=Q=0), and read (during IMPLY in all cases) operations that are executed. Here we consider the worst-case energy consumption during set and reset operations E=VP·IC·tP, where VPand tPare the applied voltage magnitude and width. We consider the worst-case energy for each input combination also for the read operation. The minimum and maximum worst-case energies per FA cycle are proportional to IC (see Table I). Values on the order of nJ are obtained for a tPof 1 µs as the one used in Section III (tIMP LY = 4 ·tP,tF ALSE = 2 ·tP, tF A = 10 ·tF ALSE + 18 ·tIMP LY ). These estimates include the comparator energy overhead. For the comparator we used the sense amplifier design from [2]. With a power supply voltage of 1.6 V the comparator dissipates around 70 fJ/comparison when tPis 1 µs, which is far less than the worst-case energy per read operation, 4 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. XX, NO. XX, XXXX 2020 TABLE II COMPARISON BETWEEN THE PROPOSED FA AND A CMOS FA WHEN EXECUTING 32 PARALLEL 32-BIT FA OPERATIONS (ON A 4KB ARRAY) # Devices Energy Delay EDP Norm. EDP$EDP Improvement$ CMOS w/ VNB∗8192 - 28672 FET ≈9.4 µJ≈284 µs≈2.7 ·10−9J·s 1 1 CMOS w/o VNB∗∗ 8192 - 28672 FET ≈9.7 ·10−4- 7.4 pJ ≈5.6 ·10−2- 4.8 µs ≈1.7 ·10−24 - 3.6 ·10−17 J·s 6.3 ·10−16 - 1.3 ·10−8 7.5 ·107- 1.6 ·1015 This work∗∗∗ tP= 1 µs 3232 RRAM ≈594 nJ ≈2.9 ms ≈1.7 ·10−9J·s 0.6 1.57 This work∗∗∗ tP= 50 ns 3232 RRAM ≈30 nJ ≈147 µs≈4.4 ·10−12 J·s 1.6·10−3607 ∗,∗∗ estimates with (w/) and without (w/o) VNB are performed considering energy and delay overhead for reading 2 kbits of data from a NAND flash memory with a 4kB memory page size [13]. CMOS FA performances were estimated projecting the time and energies for different 1-bit FA schemes taken from [3], [14], [15] where 0.18 µm, 45 nm, and 10 nm CMOS technology are used. ∗∗∗ Iread = 10 µA $w.r.t. to CMOS w/ VNB. shown in Fig.6b. To show the advantages offered by the proposed LiM scheme in terms of energy efficiency, we compare the performance of the proposed architecture against CMOS FA implementations from [3], [14], [15] with and without considering the VNB [13]). The VNB overhead was computed considering the latency and energy required to read data from a flash memory considering a typical page size of 4kB [13]. We consider flash memory technology as it is currently the state of the art for non-volatile memories. We estimate the delay and energy required to compute 32 parallel 32-bits FA operations (simple ripple carry) which require slightly less (3132) than the available 4096 devices in the array. To show the potential energy efficiency improvement over CMOS we consider the case Iread = 10 µA. For both SIMPLY and CMOS implementations, the peripheral circuitry needed to decode instructions is comparable, and thus its overhead is neglected in both cases. As shown in Table II, the largest share of energy consumption and delay for CMOS logic comes from the VNB data exchange overhead [3], [13]–[15]. With the technologies explored in this work, when tP= 1 µs (i.e., the pulse duration used in the characterization in Section III) the energy delay product (EDP) of SIMPLY is only slightly better than its CMOS counterpart when the VNB effect is included. However, the functionality of the RRAM devices used in this work was proven also with tP= 50 ns (see Fig.3a), and energy projections with such a tPshow that the proposed LiM scheme outperforms CMOS (when including the VNB overhead) by more than two orders of magnitude (worst-case projection) in energy efficiency with similar computing time, as shown in Table II. In addition, the number of required devices is reduced as compared to CMOS, thus achieving higher integration density. VI. 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