Incremental sigma delta ADC modulator and digital filter co-design

Incremental sigma-delta ADC modulator and digital filter codesign Master Thesis submitted to the Faculty of the Escola T`ecnica d’Enginyeria de Telecomunicaci´o de Barcelona Universitat Polit`ecnica de Catalunya by Juan Jos´e Baudino Forte In partial fulfillment of the requirements for the master in Electronic Engineering Advisor: Xavier Aragones Barcelona, Date February 1, 2024 Contents List of Figures 4 List of Tables 5 1 Introduction 8 1.1 Li-Ion battery operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.2 BMS systems and measurement subsystem . . . . . . . . . . . . . . . . . . 9 1.3 ADCselection.................................. 13 1.4 Examples of commercial BMS measurement system . . . . . . . . . . . . . 14 1.4.1 TI-BQ769x0.............................. 14 1.4.2 MPS-MP2797 ............................. 15 1.5 Objectives.................................... 16 1.5.1 Design Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.5.2 Methodology .............................. 17 1.5.3 Mixed-signal database management and simulators . . . . . . . . . 18 2 Fundamental operation and filtering of the Incremental SDM 20 2.1 First-OrderOperation ............................. 20 2.2 Second-Order Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3 Digitalfiltering ................................. 23 2.3.1 Cascade of integrators filter . . . . . . . . . . . . . . . . . . . . . . 23 2.3.2 Cascaded integrator-comb filter . . . . . . . . . . . . . . . . . . . . 24 3 High-level analysis and modelling 26 3.1 Modulatorsynthesis .............................. 26 3.1.1 Filtermodelling............................. 29 3.1.2 System integration . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.2 Realnumbermodelling............................. 35 3.2.1 Modulatormodels............................ 36 3.2.2 Filtermodels .............................. 36 3.2.3 Performance evaluation . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.3 Electrical modeling of modulator sub blocks . . . . . . . . . . . . . . . . . 38 3.3.1 OTAmodelling ............................. 38 3.3.2 Switchmodel .............................. 41 3.3.3 Feedback network model . . . . . . . . . . . . . . . . . . . . . . . . 42 3.3.4 Comparatormodel ........................... 43 3.3.5 Clockscheduling ............................ 43 4 System integration 45 4.1 Buildingthemodulator............................. 45 4.1.1 Sizing the capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.1.2 Finalintegration ............................ 46 4.2 Synthesizingthefilter.............................. 46 4.3 Model vs Schematic validation . . . . . . . . . . . . . . . . . . . . . . . . . 47 2 4.4 Performanceevaluation............................. 49 4.4.1 Evaluating the effect of OTA offset . . . . . . . . . . . . . . . . . . 50 4.4.2 Evaluating the effect of finite OTA gain . . . . . . . . . . . . . . . . 52 4.4.3 Evaluating the effect of OTA gain-bandwidth product . . . . . . . 54 5 Conclusions 56 5.1 Results...................................... 56 References 57 3 List of Figures 1 Li-Ion charging profile [18] . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 BMS ADC measurement subsystem . . . . . . . . . . . . . . . . . . . . . . 11 3 OCV vs SOC for Li-Ion cells from [1] . . . . . . . . . . . . . . . . . . . . . 12 4 Comparison of ADC architectures . . . . . . . . . . . . . . . . . . . . . . . 13 5 TI BQ769x0 Block Diagram extracted from [7] . . . . . . . . . . . . . . . . 15 6 TI BQ769x0 ADC Specs extracted from [7] . . . . . . . . . . . . . . . . . . 15 7 MPS MP2797 ADC Specs extracted from [6] . . . . . . . . . . . . . . . . . 16 8 Projectstructure ................................ 19 9 FirstorderIADC................................ 20 10 Normalized first order IADC with linear quantizer . . . . . . . . . . . . . . 20 11 CIFB Modulator Variants . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 12 COI2 filter architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 13 COI2 approximated architecture . . . . . . . . . . . . . . . . . . . . . . . . 24 14 CIC3architecture................................ 25 15 CIC3Bodediagram............................... 25 16 NTFSNRSimulations ............................. 28 17 Modulator pole/zero map . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 18 CICTemporalResponse ............................ 31 19 COITemporalResponse ............................ 31 20 COI2Bodediagram .............................. 32 21 Measurement error pre-trim . . . . . . . . . . . . . . . . . . . . . . . . . . 33 22 Measurement error post-trim . . . . . . . . . . . . . . . . . . . . . . . . . . 34 23 Integrator output swing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 24 Modulator architecture real number model . . . . . . . . . . . . . . . . . . 36 25 COI2filtercircuit................................ 37 26 Real number performance . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 27 OTAmacromodel................................ 39 28 OTAtestbench ................................. 40 29 Simulation results for OTA model . . . . . . . . . . . . . . . . . . . . . . . 40 30 Simulation results for OTA model . . . . . . . . . . . . . . . . . . . . . . . 41 31 Switch resistance simulation . . . . . . . . . . . . . . . . . . . . . . . . . . 42 32 Feedback mux schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 33 Completemodulator .............................. 46 34 Filter RTL synthesis flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 35 Validationtestbench .............................. 48 36 Detail of validation waveforms . . . . . . . . . . . . . . . . . . . . . . . . . 48 37 ADCtrimmingflow............................... 49 38 Effect of offset on error performance . . . . . . . . . . . . . . . . . . . . . . 50 39 Effect of offset on error performance after trimming . . . . . . . . . . . . . 51 40 Effect of finite gain on error performance . . . . . . . . . . . . . . . . . . . 52 41 Effect of finite gain on error performance after trimming . . . . . . . . . . 53 42 Effect of GBP on error performance . . . . . . . . . . . . . . . . . . . . . . 54 43 Effect of GBP on error performance after trimming . . . . . . . . . . . . . 55 4 Listings 1 Modulatorsynthesiscode............................ 26 2 Filter transfer functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3 Modulator behavioral model . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4 COI2filterRTL................................. 37 5 Noise and offset contribution verilogA code . . . . . . . . . . . . . . . . . . 39 6 SwitchverilogAcode.............................. 42 7 Comparator verilogAMS code . . . . . . . . . . . . . . . . . . . . . . . . . 43 8 adcclkctrlverilogcode ............................ 44 9 CapacitorSizingCode ............................. 45 10 COI2 gate utilization report . . . . . . . . . . . . . . . . . . . . . . . . . . 47 11 CIC3 gate utilization report . . . . . . . . . . . . . . . . . . . . . . . . . . 47 List of Tables 1 Relationship between measurements Accuracy, Resolution and Tolerance . 13 2 Systemrequirements .............................. 17 3 PolelocationofNTF.............................. 29 4 Offset and gain trim coefficients . . . . . . . . . . . . . . . . . . . . . . . . 33 5 OTA modulator parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6 Switch verilogA parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7 Valuesofthecapacitors ............................ 46 8 Calculated trim coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 9 Calculated trim coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 10 Calculated trim coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5 Abstract This thesis presents a mixed signal methodology for the design and verification of an incremental ADC and digital filter to be used in Li-Ion battery management systems. Incremental ADCs are a type of Nyquist rate converters based on sigma delta modulation, which exploits oversampling to achieve high resolution with relaxed matching requirements for passive components. These converters are specially suited for multiplexed systems since modulator and filter are periodically reset, making them ideal for battery management systems where several channels are measured. The design in this thesis will be based on a pre-existing ADC system. The digital filter architecture will be changed to enable a faster conversion rate, while maintaining the error specification. 6 List of Acronyms  SOA : Safe operating area  SOC : State of charge  DOD : Depth of discharge  BMS : Battery management systems  SDM : Sigma-delta modulator  MCU : Microcontroller unit  NTC : Negative temperature coefficient  OCV : Open-circuit voltage  CIC : Cascaded Integrator Comb  COI : Cascade of Integrators  SNR : Signal-to-noise ratio  STF : Signal transfer function  NTF : Noise transfer function  CIFB : Cascaded integrators with feedback summation 7 1 Introduction The advent of Li-Ion batteries has significantly increased the number of devices and applications that now have batteries, either in small portable applications, or large formats. The improved energy density, power capability and durability has greatly enabled electric and hybrid vehicles, grid tied energy storage systems and backup systems. We will begin this chapter by explaining the basics of Li-Ion batteries, and analyzing what are the limits of their safe operation. Once these limits have been identified, we will define the functions that a battery management system (BMS) needs to perform to ensure a safe operation. We will discuss how monitoring plays a fundamental role for BMS, and estimate the requirements for the measurement subsystem of the BMS. Taking all of this into account, we will explain the reason behind the selection of an incremental analog-to-digital converter, and analyze how they perform in two different commercial products. After this introduction, we will state the objectives of this thesis, we will define the requirements for our design, and give an overview of the methodology and tools we will use along the project. 1.1 Li-Ion battery operation Li-Ion batteriess are a collection of cells providing between 3 V to 4 V, which can be connected in series to provide a higher voltage. They come in several different formats and chemistries, with the standard one being LiCoO2: Lithium-Cobalt-Oxide [1]. The charging profile of Li-Ion batteries describes the current and voltage conditions during charging, and is divided into two phases, constant current (CC) and constant voltage (CV). Each of these regions also divided into subregions, as we can see in Fig. 1. Figure 1: Li-Ion charging profile [18] The state of a battery can be expressed with the state of charge (SOC), which is a measure of the total charge available at any given moment with respect to the nominal battery capacity. It is expressed in percentage and it is 0% when the battery is fully discharged 8 and 100% when is fully charged. Estimating the state of charge is known as fuel gauging. The depth of discharge (DOD) is a measure of the amount of charge removed from a battery, it is measured in Ah. If the DOD is expressed in percentage, it is possible for it to be over 100%, the reason behind this is that the actual capacity of the battery might be above the nominal value. For example, a battery which has a nominal capacity of 50Ah, but a real capacity of 55Ah might have a DOD higher than 100% [1] Li-Ion batteries are susceptible to a variety of operating conditions related to the voltage, current and temperatures. Large battery packs with several cells in series are more prone to be charged or discharged unevenly. The following scenarios are particularly important to take care.  Overcharge: Occurs when a cell or battery pack state of charge is greater that 100%. Overcharging might cause irreversible degradation within the cell, such as thermal runaway, cell swelling, or venting. These degradations might produce energetic failures leading to a safety hazard. Li-Ion cells begin overcharging when the cell voltage exceeds between 3.75 V and 4.2 V.  Over-discharge: Occurs when a cell or battery pack is beyond 100% Depth of Discharge. As with overcharging, over-discharging might produce irreversible damage to the battery pack, such as the dissolution of the anode foil. Trying to recharge a cell that has been over-discharged might lead to safety risks. Self-discharge rate also makes the control of over-discharging more complicated. Minimum allowable discharge voltages are between 1.8 V to 2.5 V per cell.  High Temperature: Temperatures above the safe operating area could induce thermal runaway, in which exothermic reactions will degrade the cell, with a sudden release of energy. The range of acceptable temperature varies, but between 45 ° C and 55 ° C the cell experiences accelerated degradation, and the safety limits are within 60 ° C to 100 ° C.  Low Temperature: Charging capabilities are limited at low temperatures, and might induce internal short circuit failure modes. Cells should be inhibited from charging below 0 ° C.  Over-current: Excessive charge or discharge currents could lead to same failure modes as overcharge and over-discharge. Excessive current could also lead to over temperatures. 1.2 BMS systems and measurement subsystem As with any source of stored energy, it is of utmost importance to have an effective management system to ensure that no uncontrolled release of energy occurs. Thus, battery systems must be protected from a variety of situations which might become dangerous. Battery management systems (BMS) need to ensure that the batteries and cells in the system are operated within their safe operating area (SOA) with respect to charge, voltage levels, currents and temperatures. BMS system features may provide the following functions. 9 The measurement subsystem block diagram can be seen in figure Fig. 2. As for the specs, we can see in Fig. 7 that the measurement range is [1 V, 5 V], it has an accuracy of ±15 mV over the full measurement and temperature range, and it has a measurement rate of 2 ms. Again, all this specifications are aligned with the performance we defined in section 1.2. Figure 7: MPS MP2797 ADC Specs extracted from [6] 1.5 Objectives During this thesis we will focus on the analysis and redesign of an Incremental ADM measurement system, composed of a second-order sigma-delta modulator together with the associated digital filter, to be used in next generation products for BMS. We will start from a pre-existing architecture based on a second-order modulator with a thirdorder CIC3 filter. This architecture has acceptable error performance, but conversion time needs to be improved for next generation of BMS products, therefore we will analyze a new filter architecture in order to improve the measurement time. For this task, we will develop a mixed-signal design and verification methodology with a model-based approach. This methodology and design environment can later be used to design incremental ADCs with different requirements, it will be easily expandable to cover more filter and modulator architectures, and can be reused to port the ADC circuit between different fabrication processes and quickly validate new implementations. We will begin by defining the design requirements, based on our previous analysis and product requirements. Then we will develop high-level scripts for the analysis and design of the modulator and digital filters to be considered. After high level analysis and design is done, we will move on to the modelling of the system, beginning with real numbers models to quickly evaluate the architecture, and then electrical models that we can use to explore the non ideal effects of the sub-circuits. 16 Once all the models are developed, we will integrate the complete system, using the information from the high-level synthesis and modelling to obtain a set of capacitor values for the modulator, an the gate-level implementation of the digital filter. We will finish the analysis by running performance simulations on the complete system, and evaluating the effects of different non-idealities in the overall measurement error. 1.5.1 Design Requirements In this section we will present the requirements for the ADC system to be developed, we will specify the system-level requirements and design constraints that will guide the following mixed-signal methodology. Parameter Value Modulator architecture and order CIFB 2nd order VDD 5 V VCM 2.5 V VREF 3.3 V Measurement range [0 V ; 5 V] Resolution 16bits Accuracy +/- 2mV max error @ 25 ° C Clock frequency 2 MHz Conversion time 150 µs Table 2: System requirements  Modulator Architecture - In order to reduce the analog design and layout effort, it was decided to keep the same modulator architecture used currently.  VDD, VCM, VREF - Supply voltage is provided by an internal regulator, VCM is obtained by dividing VDD, VREF is provided by an internal reference supply already available.  Measurment range - Measurement of cell voltages.  Resolution and accuracy - System-level constraints for battery management applications.  Frequency and conversion time - System clock provided by internal oscillator, maximum conversion time determined by system-level constraint of measuring 20 cells in 3 ms. This requirement sets our maximum allowable OSR to 256. 1.5.2 Methodology The first step of the development will be performing analysis and high-level modeling using Octave [19] together with the sigma-delta toolbox [4]. The goal of the first step is to obtain modulator coefficients which we will later on implement with a switched-capacitor circuit, together with evaluating the performance of the ideal mathematical model and verifying 17 it meets our requirements. We will focus on the feasibility and ease of implementation when we analyze the obtained coefficients. After analyzing the ideal modulator and filter behavior, we will then develop real number models using systemVerilog [17], which will be used to evaluate the performance of the selected modulator. The benefit of using this type of models is that they can be integrated within the mixed-signal simulation environment, thus we will be able to validate our proposed circuits by using ideal models which simulate considerably faster than the schematic representations. The next step will be developing electrical models for the sub-blocks of the modulator. These electrical macromodels will include the parameters which will affect the overall performance of the system, thus we will be able to see the impact of circuit non-idealities on the accuracy of the complete system. Effects such as thermal noise, limited bandwidth and gain, offset and slew rate will be considered. Finally, we will perform synthesis on the two available filters, to see the area impact of changing the CIC3 filter architecture for a COI2 implementation. 1.5.3 Mixed-signal database management and simulators In this section we will discuss how to properly integrate two different revision control systems in order to have a unified mixed-signal design database. The complete system design will consist of an analog database which will contain the modulator schematics, the electrical models and the mixed signal test benches to evaluate performance. This design will be done using Virtuoso, Spectre and Xcelium from the Cadence design suite [20]. For revision control, we will use Cliosoft-SOS [21], which can be used within the Cadence GUI or as a standalone application. The digital database will consist of real number models for both modulator and filters, the filter RTL design, and digital based test benches to verify the architecture. All of these design components will be implemented in systemVerilog, edited using VisualStudio Code [22]. The revision control system used for the digital database will be based in git, using gitlab [23] as the development platform. Both of these databases will be integrated within the same design environment, that means we will have a unified project structure containing the complete design. For a robust mixed-signal methodology, it is important that we keep the database consistent and up to date, this will enable the collaboration between multiple designers across different design sites, and will prevent errors due to integration incompatibilities, since the digital and analog databases will always be synchronized, giving a unified design representation. 18 Figure 8: Project structure 19 2 Fundamental operation and filtering of the Incremental SDM After analyzing the specific needs for the ADC converter in BMS systems, this chapter will focus in the theory and operation of incremental ADC converters, starting from the oversampling modulators, going over some of the digital filtering techniques associated with them, and the mixed-signal modelling and simlation methodology implemented for optimization. 2.1 First-Order Operation A first-order incremental ADC, as can be seen in Fig. 9 is a Nyquist-rate converter that employs the oversampling and noise shaping of the sigma-delta modulator to achieve high resolution. This converter is capable of converting input signals within a ±Vref range, with a resolution of nbits. The operation is as follows: First, all memory elements are reset, then the system is run for a set number of clock periods N= 2nbits , in each clock period, the comparator outputs a value equal to Vcmp =±V ref, which is fed back to the input of the loop. Figure 9: First order IADC For the analysis of the first order IADC, we will start by normalizing all values by Vref , and we will model the comparator used as a quantizer by an adder with quantization error ϵ[i]. We will follow the same analysis done in reference [11]. Figure 10: Normalized first order IADC with linear quantizer 20 At the output of the integrator, after n steps, we have y[n] = n−1 X i=0 {u[i]−v[i]}(1) After normalization we have u∈[−1,1], v∈ {−1,1}, and we are going to assume that the output of the integrator is bounded, so y∈[−1,1]. With this into consideration, we are going to divide equation (1) by N, and split the summation. y[n] N=1 N· n−1 X i=0 u[i]−1 N· n−1 X i=0 v[i] (2) The first summation of the right hand side corresponds to the average value of the input, ¯u, and since y[n] is bounded to ±1 we can rewrite equation (2) as: 1 N= ¯u−1 N· n−1 X i=0 v[i] (3) Equation (3) tells us that we can estimate the average value of the normalized input, by running the average of the output bitstream v[i]. The error of this estimation is bounded by the amount of clock cycles we run the system. This implementation is really simple, has low sensitivity to circuit components and can be implemented in low power and low area. The digital filter is specially simple, being implemented with a simple counter. One of the main drawbacks of this implementation, is that it is very slow, requiring N= 2nbits clock periods to obtain nbits of resolution. Some implementations introduce an extended counting approach, in which the information of the output of the integrator is also digitalized to reduce the error of the conversion. Another way of improving the conversion speed, is using higher order converters. 2.2 Second-Order Operation We will now analyze the operation of a second-order modulator following the same approach as the previous section. There are multiple second-order architectures [4], in this work, we will focus on a pre-existing architecture based on Cascaded Integrators with Feedback Summation (CIFB) The second order CIFB modulator can be seen in Fig. 11. The complete architecture is represented in Fig 11a, however, since we are using a two-level quantizer, we are only interested in the sign of the sign y2, thus we can disregard the coefficient c2as seen in Fig. 11b We will now analyze the difference equations in order to obtain a general expression that will allow us to implement the estimation of the input signal. 21 (a) CIFB Modulator (b) CIFB modulator with C2removed Figure 11: CIFB Modulator Variants At the start of the conversion period, both integrators have been reset, giving the initial conditions for our modulator y1[0] = 0, y2[0] = 0 Now, writing the difference equation for the output of the first delaying integrator, we obtain: y1[k] = n·b1·u−a1· k−1 X i=0 v[i] (4) Similarly, for the second delaying integrator y2[n] = c1· n−1 X j=1 y1[j]−a2· n−1 X j=0 v[i] (5) Now, replacing (4) into (5) and distributing the summation we obtain y2[n] = c1·k·(k−1) 2·b1·u−c1·a1· n−1 X j=1 j−1 X i=0 v[i]−a2· n−1 X j=0 v[j] (6) Now, solving (6) for uwe obtain 22 u=2 n(n−1) "a1 b1 n−1 X j=1 j−1 X i=0 v[i] + a2 c1b1 n−1 X j=0 v[j] + y2[n] c1b1#(7) From (7) we can observe how to obtain an estimation of the input signal. The first two terms of the left hand side represent the integration of the bitstream v. The third term contains the information of the output of the second integrator of the modulator y2. This information is not digitalized, so it will be part of the measurement error. As with the first order modulator, extended counting techniques such as the one reported in [14] can be implemented. In our case, we are going to disregard this term and just focus on the two integrators of the bitstream. u≃2 n(n−1) "a1 b1 n−1 X j=1 j−1 X i=0 v[i] + a2 c1b1 n−1 X j=0 v[j]#(8) Equation (8) can be implemented with a Cascade of Integrators digital filter. 2.3 Digital filtering 2.3.1 Cascade of integrators filter In a the general case, the simplest filter to estimate the input value for an incremental ADC is a cascade of integrators of the same order as the modulator together with a scaling factor [4]. In the case of a first order modulator, a simple up-down counter is enough. For higher order, the first stage can be implemented as an up-down counter, while the following stages must be implemented with integrators with register widths enough for the dynamic range. The size of these registers can be further optimized by simulation. Following equation (8), we observe that we can implement the filter by using a COI2 filter, and doing the weighted sum of the outputs of the first and second stage of COI, according to the modulator coefficients. Since we are interested in the digital code represented as a 16bit digital value, we will rewrite equation (8). Considering n= 28 ¯u=Vin Vref (9) Vlsb =Vfs 216 =Vref 215 (10) From equations (9) (10) we get ¯u=Vin Vlsb ·215 =code 215 (11) 23 Considering n= 28from our OSR requirement, approximating n·(n−1) ≃n2, we replace equation (12) into (8), and we obtain code =a1 b1 n−1 X j=1 j−1 X i=0 v[i] + a2 c1b1 n−1 X j=0 v[j] (12) Which is implemented by the block diagram represented in Fig. 12 Figure 12: COI2 filter architecture The final approximation we will consider for the COI architecture, is dropping the term depending on the output of the first integrator. This approximation is going to produce a linear error that can later be trimmed with a gain coefficient, as we will see in the following chapter. Figure 13: COI2 approximated architecture 2.3.2 Cascaded integrator-comb filter In a COI filter, the bitstream goes through an accumulate and dump process. The final output can be calculated as the weighted sum of the samples of the loop bitstream. This type of filtering does not produce notches in the response, and thus cannot provide suppresion of periodic noise. In case we need periodic noise suppression, we can use a cascaded integrator-comb filter (CIC), as the one depicted in Fig. 14. For a decimating filter, the input signal first goes through N integrator stages, followed by a down sampler ↓Rand then N comb stages. We can observe the normalized frequency response in Fig. 15, where we can see the periodic notches. 24 Figure 14: CIC3 architecture Figure 15: CIC3 Bode diagram In typical Sigma-Delta ADC systems, the order of the CIC filter is chosen to be one order above the modulator order. This is to provide sufficient attenuation at higher frequencies, so that the shaped quantization noise that gets foldback back to base band after decimation does not degrade the conversion performance. It is also important to note that the CIC filter has a zero/pole cancelation at zero frequency, this means that the modulator will produce a bounded output for DC inputs, which is particularly important for sigma-delta modulators, to avoid saturation of the filter due to an unwanted DC input component (such as an offset component). For incremental ADCs we do not have this limitation since we are going to periodically reset the filter, so we will avoid any saturation. [3] The transfer function for a N stage CIC filter, with decimation factor R, is given by Hcic =1−zR 1−z−1N This has a DC gain of RN[5]. 25 in time scales between the COI2 and CIC3 filter, for the COI2 filter we expect to run the conversion for 128 µs, while the CIC3 filter takes 384 µs to settle, thus justifying the need to change the filter architecture. Looking now into the two COI2, we see that both implementations have two poles at zero frequency, but the exact filter from the diagram in Fig. 12 has an additional zero. Figure 20: COI2 Bode diagram Looking into the Bode diagrams, we see that the approximated COI2 filter has more attenuation at higher frequencies. 3.1.2 System integration Finally, we are going to integrate the synthesized modulator together with the digital filters to evaluate the performance of the whole system. For that, we are going to simulate the system over the whole measurement range and measure the error. We will analyze the raw output of the filter, and we will also perform trimming of offset and gain errors. For offset error, we are going to measure the output of the filter with zero input. After subtracting, we will perform a gain trimming at 5 V. outtrim = (outraw −offsettrim)·gaintrim (14) 32 Figure 21: Measurement error pre-trim Filter offsettrim gaintrim COI2exact 0 1 COI2approx 0 1.034 CIC3 0 1.0094 Table 4: Offset and gain trim coefficients 33 Figure 22: Measurement error post-trim In Fig. 21 we can observe the pre-trim error performance. Utilizing the trimming coefficients from Table 4 we obtain the post-trim performance from Fig. 22. We can observe that the COI2 filter implemented with equation (12) has the best performance before trim, while both the aproximated COI2 and CIC3 have gain error. After trim, we can observe that the CIC3 filter has the best error performance, which is expected since it has a higher order and is measured over a longer time. From the two COI2 implementations, we can see that after trim, the approximated COI2 filter has a better performance than the exact one, the reason for this can be seen from the previous bode plot from Fig. 20, where we observed that the exact filter has worse attenuation at high frequencies. Finally, we are going to evaluate the maximum output of the integrators. 34 Figure 23: Integrator output swing We can see that neither of the integrators reach the 5 V which is our supply rail, at the worst case with 5 V of input, we still have around 1 V of headroom for the amplifiers, thus we do not need to rescale the coefficients of the modulator. 3.2 Real number modelling After high-level synthesis and simulation, we move down to modeling in an environment closer to the actual circuit implementation. These models run fast in the digital simulator, so we can gain a lot of simulation performance when we use them later for validation of models vs schematic. The goal of this step is to map the modulator behavior into an actual architecture that we can later on implement with a switched-capacitor circuit. This is going to allow us to quickly evaluate the dynamic range of the selected architecture, the behavior of the modulator with each clock phase, and identify if there is any unwanted DC component in the inputs of the modulator which would cause the integrators to saturate. This is going to be done in systemVerilog and simulated in Cadence Xcelium and later on AMS environments.  Modulator models  Filter models  Performance evaluation 35 3.2.1 Modulator models We are going to use two different real number models for the modulator. One implementing just the mathematical description of the modulator, and one representing the actual switched cap architecture implemented. This last one is going to be useful to quickly validate the effect of coefficient scaling. always@(posedge clk or negedge rstn ) begin i f ( ! rstn ) begin // Reset behavior int1 <= 0; int2 <= 0; end else begin // Modulator behavior int1 <= int1 + b1 * vin = a1 * vre f * cmp; int2 <= int2 + c1 * int1 = a2 * vre f * cmp; end end // Output assignment assign cmp = ( int2 >0) ? 1 : = 1; assign dout = (cmp==1)? 1 : 0 ; Listing 3: Modulator behavioral model Figure 24: Modulator architecture real number model 3.2.2 Filter models For the COI2 filter we are going to use the RTL implementation, which is later going to be synthesized for the final system performance simulations. The filter is going to be implemented with two registers for the integrators, together with two signed integrators. It is important to use a signed arithmethic in order to be consistent with the equations used for the synthesis and the analysis. There is some extra logic to match the logic values of the bitstream into their 2’s complement representation. [15] 36 Figure 25: COI2 filter circuit assign d bitmatch [ 1 : 0 ] = ! dout sdm ? 2 ’ b11 : 2 ’ b01 ; always@(posedge clk or negedge rstn ) begin i f ( ! rstn ) begin int1 <= 0; int2 <= 0; end else begin int1 <= $ signed ( int1 ) + $ signed ( d bitmatch ) ; int2 <= $ signed ( int2 ) + $ signed ( int1 ) ; end end Listing 4: COI2 filter RTL 3.2.3 Performance evaluation To evaluate the performance of the system, we will run conversions for the whole measurement range and measure the maximum error. After running a simulation with the full set of inputs, we can observe that we obtain the same performance as the one we simulated with the high level models in Octave in Fig. ??, which validates our architecture implementation. 37 Figure 26: Real number performance 3.3 Electrical modeling of modulator sub blocks In this section we will implement the mixed-signal models for all the modulator subblocks. As previously mentioned we will implement a switched-capacitor CIFB modulator.  Modeling the OTA  Modeling the switches  Modeling the feedback DAC  Modeling the comparator 3.3.1 OTA modelling We begin by doing an electrical macromodel of the OTA, we are going to implement a two pole system with slew rate limiting, flicker and thermal noise. 38 Figure 27: OTA macromodel We are going to use the following parameters to describe the model. Parameter Name Sim value DC Gain gain 1e6 Gain Bandwidth Product GBP 100 MHz Tail current of first stage It 1 µA Slew Rate SR 100 MV/s Frequency of non dominant pole fp2 300 MHz Offset voltage voff 0 Thermal noise power density thrml pwr 0 Flicker noise power density @1Hz flkr pwr 0 Table 5: OTA modulator parameters With this set of parameters, we size the components of the macromodel from Fig. 27 G0 = 2π·It SR ·GBP , R0 = gain·SR 2π·It·GBP , C0 = It SR G1 = −1, R1 = 1 , C1 = 1 2π·fp2 (15) Noise and offset are added with the following verilogA contribution in the input block of the macromodel. V(a , b) <+ VOFF + f l i c k e r n o i s e (FLKR PWR, 1.0 , ” f l i c k e r ” ) + wh it e n ois e (THRML PWR, ”thermal ” ) ; Listing 5: Noise and offset contribution verilogA code We run an open loop AC simulation, and a closed loop transient simulation, with the OTA connected as a buffer, and we check the frequency and slew rate behavior. 39 Figure 28: OTA testbench Figure 29: Simulation results for OTA model 40 Figure 30: Simulation results for OTA model 3.3.2 Switch model For the switches, we are going to use a verilogA model, which is going to implement a non linear resistor with a cubic spline. This model is also going to include thermal noise related with the resistance value. The dependence of the switch resistance with input voltage, and the charge injection effect, are not going to be considered in this model. The reason behind this, is that we want to keep the models simple enough to capture the behavior of the parameter we use for design, in this case the Ron. At the transistor-level implementation stage of the design, this model will be replaced by an ideal circuit, and the impact of the second-order effects will be seen with the performance simulation. A further design optimization step will seek to decrease the impact of this nonlinearity and charge injection. On resistance ron Off resistance roff Enable thermal noise noise on Control threshold vth Table 6: Switch verilogA parameters 41 Figure 35: Validation testbench In Fig. 35 we can observe the testbench used for validation. It is the same as the one used for performance evaluation, but we are running two instances of the modulator in parallel under the same stimuli. One of them is the modulator schematic built up with the electrical models we developed represented in Fig. 33. The other modulator is the systemVerilog model represented in Fig. 24. We will compare the output bitstream and the value of the second integrator to validate that the schematic modulator is correctly implementing the difference equations we desire. Figure 36: Detail of validation waveforms The results are presented in Fig. 36. Observing the beginning of the conversion, we can see that both modulators have the same behavior, but there is a slight difference between the real number model and the electrical circuit, since the integrators and components 48 are no longer ideal. This slight difference is integrated in each cycle, until we can see that both modulators produce a difference in the bitstream. 4.4 Performance evaluation Finally, we will evaluate the complete performance of the system, using both the modulator and the filter implementations, and we will analyze the effect of different parameters on the overall performance of the system. The test procedure is as follows, we run a set of 16 equally spaced inputs from 0 V to 5 V, we extract offset and gain trim values, and then we run the full set of inputs again to verify that we meet the conversion error spec. We will run this test flow changing the parameters for DC gain, unity gain frequency, and offset of the operational amplifiers to see the impact on the error performance, and check whether the trimming can get the error into spec. Figure 37: ADC trimming flow 49 4.4.1 Evaluating the effect of OTA offset Figure 38: Effect of offset on error performance We begin our analysis by studying the effect of OTA offset in the overall error performance. We inject independently 1mV of offset in the first stage and second stage OTAs. In Fig. 38 we can observe that the offset in the first amplifier produces an an offset in the overall conversion, which can be successfully removed after trimming as seen in Fig. 39. In comparison, offset in the second amplifier, does not produce offset in the conversion result. The reason for this is that the feedback loop suppresses the offset of the second stage. This indicates that the amplifier of the second stage will have more relaxed requirements for offset, allowing the a reduction in the area of the input stage when compared to the first stage amplifier. Even if offset of the first stage can be removed after trimming, when we consider the overall performance over temperature, it might become difficult to successfully trim the offset to maintain the error performance over the complete temperature range. In order to reduce the effect of offset, we can implement either a chopping or auto-zeroing technique, 50 this will also help in reducing the low frequency flicker noise. Figure 39: Effect of offset on error performance after trimming offsettrim gaintrim voff1= 1 mV -28 1.025870 voff2= 1 mV 0 1.025785 Table 8: Calculated trim coefficients 51 4.4.2 Evaluating the effect of finite OTA gain Figure 40: Effect of finite gain on error performance Now we consider the effect of OTA DC gain, in Fig. 40 can observe that as we reduce the gain of the amplifiers, the gain error of the conversion increases. This gain error can be successfully trimmed out as seen in Fig. 41. However, there are additional considerations we should keep in mind when sizing the gain of the amplifiers. A reduced amplifier gain will decrease the loop gain of the overall system, this will degrade the noise and linearity performance since the loop will not be able to successfully suppress non linearity and noise/offset of the second stage. 52 Figure 41: Effect of finite gain on error performance after trimming OTA DC Gain offsettrim gaintrim 100 dB 0 1.025785 80 dB 0 1.025955 60 dB 0 1.027058 40 dB 0 1.038227 Table 9: Calculated trim coefficients 53 4.4.3 Evaluating the effect of OTA gain-bandwidth product Figure 42: Effect of GBP on error performance Finally, we evaluate the effect of the GBP in Fig. 42. After trimming, in Fig 43 we can observe that for values significantly above the system frequency (GBP > 10 ∗fs), the performance of the system is not degraded and after trimming and the error specification can be met. In the case of low GBP (GBP = 2 ∗fs) we observe a significant degradation on the error performance, which is non linear in nature, and cannot be trimmed out. 54 Figure 43: Effect of GBP on error performance after trimming GBP offsettrim gaintrim 4 MHz 0 1.025785 20 MHz 0 1.025785 100 MHz 0 1.025785 Table 10: Calculated trim coefficients 55 5 Conclusions 5.1 Results The need for this thesis originated in the requirement to change a pre-existing circuit and architecture to meet a more strict conversion time requirement, thus the need to analyze new filter architecture that perform the measurement in a shorter amount of time, while remaining within the measurement error specification. In this thesis we have developed a mixed signal design and verification methodology with a model based approach, used to redesign an incremental ADC system to meet the requirements for the next generation of battery management systems. Beginning from system level requirements, and based on a pre-existing design, we have implemented high level synthesis using Octave with the sigma-delta design toolbox. From this synthesis, we obtained modulator coefficients, which we were able to simulate together with the filter to quickly evaluate the performance of the system. The next step involved real number modeling of the modulator and filter architectures, this enabled us to run the simulation in the same design environment as the schematic, allowing us to validate the actual modulator schematic together with the ideal real number model. After real number modeling, we developed several mixed signal block models to build the actual modulator architecture. Careful consideration was taken while modeling in capturing parameters which will be representative of the modeled circuits and which might affect the performance of the overall system. The filter RTL was then synthesized into a generic technology, to run the modulator schematic with an netlist of the implemented filter. Finally, we integrated the complete design and run performance simulation to analyze the impact of different circuit parameters into the performance of the complete system. This methodology, and design and verification environments, can be used to quickly evaluate the effects of high level parameters in the overall performance of the system, provides models at different abstraction levels that can be used to evaluate the performance of the different sub-blocks of the design, and can be easily expanded to cover more modulator and filter architectures. It can be used for new designs as well as porting a specific ADC implementation to different fabrication processes. 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