Impact of intrinsic parameter fluctuations on the performance of In0.75Ga0.25As implant free MOSFETs

Impact of intrinsic parameter fluctuations on the performance of In0.75Ga0.25As implant free MOSFETs N. Seoane1, A. Garcia–Loureiro1, M. Aldegunde1, K. Kalna2 and A. Asenov2 1Dept. of Electronics & Computer Science, Univ. of Santiago de Compostela,15782 Santiago de Compostela, Spain 2Dept. of Electronics & Electrical Engineering, Univ. of Glasgow, Glasgow G12 8LT, Scotland, United Kingdom E-mail: [email protected]s Abstract. We investigate the level of statistical variability in implant free (IF) MOSFETs, which are one of the most promising candidates III–V channels implementation. We report results for the threshold voltage (VT) fluctuations in aggressively scaled IF III–V MOSFETs induced by random discrete dopants in the δ–doping plane obtained using 3D drift–diffusion (D–D) device simulations. The D– D simulator is meticulously calibrated against results obtained from ensemble Monte Carlo device simulations. The simulated 30, 20 and 15 nm gate length In0.75Ga0.25As channel IF transistors exhibit threshold voltage standard deviations of 42, 58 and 61 mV, respectively, at a drain voltage of 0.1 V. At a drain voltage of 0.8 V, the threshold voltage standard deviations increase to 55, 71 and 81 mV, respectively. While the standard deviations of VTin the 30 and 20 nm IF MOSFETs are close to those observed in bulk Si MOSFETs with equivalent gate lengths, the threshold voltage standard deviation in the 15 nm gate length IF MOSFET is lower. PACS numbers: 81.05.Ea, 85.30.De Submitted to: Semicond. Sci. Technol. Impact of intrinsic parameter fluctuations on the performance of IF MOSFETs 2 1. Introduction With the scaling of the CMOS technology towards the 22 nm generation, silicon channel conventional and novel MOSFET architectures face difficulties to meet the performance requirements [1]. Therefore, intensive research is underway to replace the Si channel with other high mobility semiconductor which can deliver significant performance improvement. MOSFETs with Ge channels [2] for p–channel applications or compound semiconductors [3] for n–channel applications are now a widely accepted option for overcoming the performance limitations inherent to the low mobility of Si [4]. Recent developments such as the demonstration of a high–κgate dielectric stack for GaAs with an unpinned interface [5], and suitable epitaxial layer structures have substantially improved the prospect for the introduction of III–V MOSFETs for high performance low power CMOS applications. III–V n–channel MOSFETs in combination with high performance p–channel Ge transistors are becoming serious candidates for co– integration in dual channel CMOS platforms [1], which may have unique advantages in regard to RF, switching and power control functions. With the scaling of silicon MOSFETs to nanometre dimensions, the intrinsic parameter variation introduced mainly by discreteness of charge and matter has become a major bottleneck to scaling and integration [6]. One of the major sources of statistical variability are the random discrete dopants in the active region of the transistors. The IF MOSFETs may have superior robustness against dopants induced variability as dopants are separated from the mobile electrons in the channel. However, the proximity of the δ–doping plane may still significantly affect the electron population and transport in the channel. Therefore, the analysis of the potential intrinsic variations is vital for the proper assessment of the scaling potential of III–V IF MOSFETs. In this work, we study the threshold voltage variability due to the presence of random discrete dopants in the δ–doping layer of IF In0.75Ga0.25As MOSFETs. The devices, scaled to gate lengths of 30, 20 and 15 nm, have been simulated using a 3D parallel drift–diffusion (D–D) device simulator described in details elsewhere [7]. The parallelisation of the code has been carried out using the standard message passing interface (MPI) [8]. In section 2 we introduce the basic features of our 3D D–D device simulator and the adopted simulation methodology. The device structure and the calibration of the drift–diffusion simulator against Monte Carlo simulation data are presented in section 3. The simulated variability in the threshold voltage is presented in section 4. Finally, the last section summarises the main conclusions of this work. 2. Simulation methodology Figure 1 shows the flow chart of the 3D parallel finite element simulator for IF heterostructure MOSFETs illustrating the computational procedure used to solve the drift–diffusion transport model equations. In this model, the Poisson and the continuity Impact of intrinsic parameter fluctuations on the performance of IF MOSFETs 3 equation for electrons are solved consistently with mixed Dirichlet and Neumann boundary conditions. The discretisation of the Poisson equations has been carried out using the Ritz–Galerkin approximation with linear finite element basis functions [9]. On the other hand, the discretisation of the continuity equations requires a special approach. In particular, the Scharfetter–Gummel discretisation scheme has been used in this work [9]. The non–linear Poisson equation and the current continuity equation for electrons are decoupled using Gummel iterations and linearised using the Newton–Raphson method. The linear systems are then solved in parallel using domain decomposition methods [10]. To solve the local linear systems within each subdomain we have used Krylov subspace solvers, such as the FGMRES and the BiCGSTAB methods, preconditioned by Incomplete LU factorisations dependent on both a numerical threshold and a certain level of fill–in (standard ILUT preconditioner). More details about the simulator can be found in [7]. Quantum corrections like the density gradient method [11] have not been included into the D–D approach at this stage, although at such simulated dimensions the use of quantum corrections would be desirable. The quantum corrections would affect the description of the individual dopants in the δ–doping layer and the shape of carrier density in the channel. Electrostatically the dopants induce a deep Coulomb well resulting in an artificially high carrier density in the attractive potential case. The quantum corrections like density gradient method would restrict the high carrier density by approximating the quantum confinement effects. This artificial high carrier density created by the Coulomb potential of a point–like charge is reduced in our case by the use of a cloud–in–cell assigment wich spreads the charge over the tetrahedral element [12]. Besides, only the tails of the Coulomb potential of the discrete dopants in the δ–doping layer affect the potential distribution in the channel and the artificial carrier trapping in this case is less pronounced. Therefore, our classical simulations, which are computationally less expensive, still provide useful qualitative results. 3. Device structure and calibration The devices analysed here are In0.75Ga0.25As enhancement mode MOSFETs with implant free source/drain regions [13]. The MOSFET structure is grown on an InP substrate and consists of a 49 nm In0.52Ga0.48As buffer layer and a Si δ–doping layer with 3×1012 cm−2. The In0.75Ga0.25As channel layer is sandwiched between In0.53Ga0.47As embed layers. The high mobility channel forms a quantum well with energy barriers comparable to the supply voltages at and beyond the 22 nm node. In this way, the carriers are well confined to the channel, providing ultra–thin body like scaling performance. Finally, an amorphous Ga2O3/GdGaO dielectric stack is used to separate a metal gate as shown in figure 2. The devices have been scaled, in both vertical and horizontal dimensions in respect to gate lengths of 30, 20 and 15 nm. All dimensions used in the scaling process are collected in table 1. Impact of intrinsic parameter fluctuations on the performance of IF MOSFETs 4 The 3D D–D simulator is meticulously calibrated against ID–VGcharacteristics obtained from MC simulation results [14] at drain biases of 0.1 and 0.8 V as shown in figure 3 for gate lengths of 30, 20 and 15 nm, respectively. The workfunction of the metal gate was fixed to 4.0 eV. In the calibration, we have used a high field mobility model [15]. In the calibration process, the low field mobility and the saturation velocity are adjusted to match accurately the MC simulation data. The calibration process yields a low field mobility of 5000 cm2/Vs and a saturation velocity of 4 ×107cm/s in the channel of the 30 nm gate length implant free In0.75Ga0.25As MOSFET, and of 4000 cm2/Vs and 108cm/s for the 20 nm gate length and, finally, of 5000 cm2/Vs and 6.5×107cm/s for the 15 nm gate length. Figure 3 also show the data obtained from the D–D simulations on a logarithmic scale in the insets in order to illustrate the subthreshold slope. Table 2 collects the subthreshold slope at low and high drain voltages for the three scaled devices. The subthreshold slope worsen only slightly when the IF transistor is scaled from 30 to 20 nm gate length, but it deteriorates by 17% when scaled to the 15 nm gate length. The subthreshold slopes are similar to those measured in Si thin–body transistors [16]. Finally, we would like to stress the limitations of our simulation model. The D–D approach does not properly represent the non–equilibrium carrier dynamics and ballistic transport effects in sub–50 nm IF MOSFETs. However, when accurately calibrated against the results from ensemble Monte Carlo device simulations [14] the D–D approach gives a good indication of the expected intrinsic material parameters variations associated with device electrostatics like the threshold voltage fluctuations [17]. 4. Threshold voltage variability To investigate the threshold voltage variations in the IF MOSFETs introduced by the random discrete dopants in the δ–doped layer, a random distribution of dopants is generated from the continuous doping profile. The random placement of the dopants in the δ–doped layer is performed on an atomistic grid defined by the positions of the In, Al and As atoms, as can be seen in figure 4. The charge associated with this distribution is then mapped to the device simulation mesh using a cloud–in–cell algorithm [12]. For every dopant, its charge is split among the four nodes of the tetrahedron enclosing it. The fraction of the charge assigned to the particular node is a barycentric coordinate of the charge position with respect to that node. In this way, the point–like charge is smoothed on the nearest neighbour mesh nodes. Figure 5 depicts electron density and conduction band profile across the heterostructure at the position of a random dopant in the delta–doped layer. The ionised impurity affects the conduction band, producing a potential well which results in a very sharp peak of the electron density. The influence of this effect in a three–dimensional simulation can be seen in figure 6 which shows an example of the electron density at logarithmic scale inside the channel and the δ–doping layer. The position of the dopants influences the charge distribution in the channel although there is a physical separation between them. The tails of Coulomb potential Impact of intrinsic parameter fluctuations on the performance of IF MOSFETs 5 associated with the ionised donors produce a lowering of the conduction band level and an increase in the electron density in the channel. The tail of Coulomb potential above the discrete dopants creates islands of negative charge resulting in different favoured paths for the electrons and consequently different I–V characteristics. We have generated statistical samples of 100 microscopically different transistors with different random positions of dopants in the δ–doping layer to analyse the impact of random discrete dopants induced fluctuations on the threshold voltage. We have used a constant current criterion to extract the threshold voltage. At low drain bias, the electrostatic behaviour below the channel is very similar for the scaled devices because the dimensions of the channel and the layers below are kept constant during the scaling and the same constant current criterion has been used (ID= 10 nA·W/L). However, with an increasing the drain bias to 0.8 V the electrostatic behaviour of each scaled transistor becomes a very different. Therefore, at the high drain bias, we have used a different constant current criterion for each one of the three scaled devices (ID= 100 nA·W/L, ID= 50 nA·W/L and ID= 300 nA·W/L for the 30, 20 and 15 nm gate length devices, respectively). The criterion has been chosen considering the results from simulations with a continuous doping profile where ID–VGcharacteristics on a log scale exhibits a linear behaviour in the sub–threshold region. The distributions of threshold voltage at drain biases of 0.1 V and 0.8 V are presented in figures 7 and 8 respectively, for each gate length device. The statistical mean of the threshold voltage obtained from the sample of devices with different dopant distributions in the δ–doping layer is always larger that the nominal value from the continuous simulations, at both low and high drain biases. This behaviour is opposite to the general trends of average threshold voltage lowering observed in sub–100 nm gate length bulk Si MOSFETs simulated with random discrete dopants in the channel region only [18]. This is not totally surprising because the fluctuations in these two device architectures are coming from two different sources: acceptors in the channel in the bulk Si MOSFET and donors in the δ–doping in the IF MOSFET. The discrete dopants from the δ–doping layer induce the localisation of electrons into Coulomb wells. This localisation, on average, reduces the current flow along the channel when compared to the continuous δ–doping simulations and the gate has to lower, on average, the potential barrier much more. The average threshold voltage increase at a low drain voltage is more pronounced when the devices are scaled down to 15 nm. However, this behaviour is not seen at high drain voltage, when the average increase is most important for the 20 nm gate length device. Figure 9 shows the conduction band profile and electron density in a plane from source to drain along the middle of the channel for the 15 nm gate length device, at VD=0.1 V and VG=0.5 V. The effect of the position and number of random dopants on the channel is shown for three different random dopant configurations and compared to a device with continuous doping (smooth). The configuration that produces a highest current has a large number of dopants, 29, compared to the nominal value of 21. In this case, the potential barrier is lower than in the other cases and the the electron density is higher, which leads to a higher drain current. The other two random Impact of intrinsic parameter fluctuations on the performance of IF MOSFETs 6 dopant configurations have 18 and 16 dopants providing currents of 20 A/m and 10 A/m respectively (since we simulate devices with particular width and no translation symmetry it is not appropriate to provide current density but the exact simulated current). The effect of the position of the dopants is also noticeable in the figure. For instance, for the lowest current device, the potential barrier below the gate is lower on one side of the channel, which favours the current flow here. However, for the device with a current of 20 A/m the potential barrier below the gate is higher in the middle of the device, so the current flow will be through the lateral regions of the device. Table 3 shows the standard deviation of the threshold voltages obtained from this variability study as a function of the transistor gate length and the applied drain voltage. The standard deviation values for scaled bulk Si MOSFETs are provided in the same figure for comparison [17]. The impact of fluctuations becomes more pronounced with the applied drain bias since the standard deviation increases. The standard deviation of the threshold voltage also increases with reducing gate length, following approximately an aerial dependence for the random dopant induced threshold voltage variation which magnitude is proportional to the first order to 1 √W L . Results show that the standard deviation of In0.75Ga0.25As IF MOSFET is close to that of bulk silicon MOSFETs with comparable gate length as can be seen in table 3. The magnitude of the threshold voltage fluctuations indicates that the random dopant induced variability from the δ– doping layer in IF MOSFETs has a similar impact on their scaling and integration as in the same gate length implanted Si transistors [17]. 5. Conclusion In this work, a calibrated parallel finite element 3D D–D device simulator [7] has been adopted for the simulation of IF III–V MOSFETs. The simulator has been meticulously calibrated against ID–VGcharacteristics at low and high drain voltages obtained from comprehensive Monte Carlo device simulations [14]. The simulator has been used to investigate the influence of random discrete dopants in the δ–doping layer on the threshold voltage in 30 nm, 20 nm and 15 nm gate length IF In0.75Ga0.25As MOSFETs. The subthreshold slopes of the IF MOSFETs in the range of 100 mV/dec, extracted from the drift–diffusion simulations, are comparable with those observed in novel Si thin–body transistors [16]. The subthreshold slope slightly increases when the device is scaled from 30 nm to 20 nm gate length. When the IF transistor is scaled in respect to a gate length of 15 nm, the subthreshold slope deteriorates by 17%. Results show that the impact of fluctuations becomes more pronounced with the increase in the applied drain bias and with the reduction of the gate length. The magnitude of the threshold voltage standard deviation is similar to that observed in equivalent bulk Si MOSFETs. Therefore, the intrinsic parameter induced variations in the threshold voltage may present a similar problem for integration and circuit design using IF MOSFETs as for the equivalent gate length Si MOSFETs. Impact of intrinsic parameter fluctuations on the performance of IF MOSFETs 7 Acknowledgements This work was supported by Spanish Government (TIN2007–67537–C03–01) and by Xunta de Galicia (DXIDI07TIC01CT and INCITE08PXIB206094PR). NS and MA thank Xunta de Galicia and Ministerio de Educaci´on y Ciencia de Espa˜na for their awarded fellowships (A. Alvari˜no and FPU respectively). NS also thanks Xunta de Galicia for providing financial support for her position as a visiting researcher at the University of Glasgow. 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Gate length [nm] Thickness of [nm] 30 20 15 Source-to-gate separation 30 20 15 Gate-to-drain separation 30 20 15 High-κdielectric 3 2 1.5 In0.52Al0.48As top spacer 2 1 1 In0.53Ga0.47As top embed 1 0.5 0.5 In0.75Ga0.25As channel 5 5 5 In0.53Ga0.47As bottom embed 1 1 1 In0.52Al0.48As bottom spacer 2 2 2 δ-doping 3 ×1012cm−2 In0.52Al0.48As buffer 49 49 49 Table 2. The subthreshold slope at low (VD= 0.1 V) and high (VD= 0.8 V) drain voltages for the IF In0.75Ga0.25As MOSFETs scaled in respect of indicated gate lengths. Gate length Subthreshold slope [mV/dec] [nm] VD= 0.1 V VD= 0.8 V 30 87.5 94.7 20 88.1 106.2 15 105.6 131.7 Table 3. Standard deviation of the threshold voltage as a function of the gate length and the drain voltage for scaled In 0.75Ga0.25As IF MOSFETs compared with the standard deviation observed in scaled bulk Si MOSFETs. In0.75Ga0.25As IF MOSFETs Bulk Si MOSFETs [17] VDGate length [nm] Gate length [nm] [V] 30 20 15 35 25 18 13 Standard deviation, σVT[mV] 0.1 42 58 61 33 46 61 100 0.8 55 71 81 – – – – Impact of intrinsic parameter fluctuations on the performance of IF MOSFETs 16 (a) (b) Figure 9. Conduction band profile (a) and electron density (b) in a plane from source to drain along the middle of the channel for the 15 nm gate length IF MOSFET device. Four situations are represented: a device with continuous doping (smooth) and three devices with different random dopant configurations. The obtained drain current for each case is also indicated. The source and drain regions are on the right and left, respectively.