Development of tools for the simulation of nanometric transistors using advanced computational architectures

UNIVERSIDADE DE SANTIAGO DE COMPOSTELA Centro Singular de Investigaci´ on en Tecnolox´ ıas da Informaci´ on (CiTIUS) Tesis doctoral DEVELOPMENT OF TOOLS FOR THE SIMULATION OF NANOMETRIC TRANSISTORS USING ADVANCED COMPUTATIONAL ARCHITECTURES Presentada por: Guillermo Indalecio Fern´ andez Dirigida por: Antonio Jes´ us Garc´ ıa Loureiro Natalia Seoane Iglesias Santiago de Compostela, junio de 2016 Antonio Jes´ us Garc´ ıa Loureiro, Profesor Titular del ´ Area de Electr´ onica de la Universidad de Santiago de Compostela Natalia Seoane Iglesias, Investigadora Postdoctoral del Centro Singular de Investigaci´ on en Tecnolox´ ıas da Informaci´ on de la Universidad de Santiago de Compostela HACEN CONSTAR: Que la memoria titulada Development of tools for the simulation of nanometric transistors using advanced computational architectures ha sido realizada por Guillermo Indalecio Fern´ andez bajo nuestra direcci´ on en el Centro Singular de Investigaci´ on en Tecnolox´ ıas da Informaci´ on de la Universidade de Santiago de Compostela, y constituye la Tesis que presenta para optar al t´ ıtulo de Doctor. Santiago de Compostela, junio de 2016 Antonio Jes´ us Garc´ ıa Loureiro Director/a de la tesis Natalia Seoane Iglesias Director/a de la tesis Guillermo Indalecio Fern´ andez Autor de la tesis Antonio Jes´ us Garc´ ıa Loureiro, Profesor Titular del ´ Area de Electr´ onica de la Universidad de Santiago de Compostela Natalia Seoane Iglesias, Investigadora Postdoctoral del Centro Singular de Investigaci´ on en Tecnolox´ ıas da Informaci´ on de la Universidad de Santiago de Compostela como directores de la tesis titulada: Development of tools for the simulation of nanometric transistors using advanced computational architectures Por la presente DECLARAN: Que la tesis presentada por Don Guillermo Indalecio Fern´ andez es id´ onea para ser presentada, de acuerdo con el art´ ıculo 41 del Regulamento de Estudos de Doutoramento, por la modalidad de compendio de ART´ ICULOS, en los que el doctorando ha tenido participaci´ on en el peso de la investigaci´ on y su contribuci´ on fue decisiva para llevar a cabo este trabajo. Y que est´ a en conocimiento de los coautores, tanto doctores como no doctores, participantes en los art´ ıculos, que ninguno de los trabajos reunidos en esta tesis ser´ an presentados por ninguno de ellos en otras tesis de Doctorado, lo que firmamos bajo nuestra responsabilidad. Santiago de Compostela, junio de 2016 Antonio Jes´ us Garc´ ıa Loureiro Director/a de la tesis Natalia Seoane Iglesias Director/a de la tesis A mind needs books like a sword needs a whetstone. Tyrion Lannister Agradecimientos Jam´ as habr´ ıa llegado a ser doctor si no fuese por mi madre, porque ella me ense˜ n´ o a leer y a sumar. A partir de ah´ ı ya es f´ acil. Santiago de Compostela, junio de 2016 x y la fuente de variabilidad, de tal manera que comparando el FSM de varios dispositivos obtenemos una relaci´ on entre los propios dispositivos. Finalmente, es posible utilizar el FSM para realizar predicciones sobre el comportamiento del dispositivo ante un conjunto de perfiles de perturbaci´ on. Esto permite obtener una estimaci´ on de los par´ ametros del dispositivo sin tener que llegar a simularlo, lo que la convierte en una primera aproximaci´ on de muy bajo coste computacional y con una precisi´ on adecuada. Cuando se estudia la variabilidad de dispositivos semiconductores a trav´ es de la simulaci´ on num´ erica, nos introducimos en el campo de los estudios estad´ ısticos, en el sentido de que tendremos una mayor precisi´ on en los resultados a medida que aumentemos el n´ umero de simulaciones , es decir la carga computacional de trabajo que estamos utilizando. Esta situaci´ on se da en otros campos de investigaci´ on, como oceanograf´ ıa, biolog´ ıa, ingenier´ ıa civil, y normalmente se resuelve creando una infraestructura adaptada al problema concreto, lo que conlleva que la soluci´ on est´ e ligada al problema resuelto, no siendo as´ ı aplicable en otros campos, y generalmente tampoco se puede adaptar a recursos computacionales distintos. Se han desarrollado tambi´ en soluciones gen´ ericas que act´ uan como un middleware o como una plataforma cient´ ıfica, pero igualmente presentan dificultades para abordar problemas nuevos, o para ser adaptadas a recursos computaciones distintos de los inicialmente previstos. Nuestro objetivo es reducir el tiempo de simulaci´ on, con el fin de obtener los resultados tan pronto como sea posible, pudiendo as´ ı realizar m´ as simulaciones. En nuestro caso de an´ alisis de variabilidad, aumentar el n´ umero de simulaciones nos va a permitir caracterizar m´ as adecuadamente el efecto de la misma en el dispositivo. La principal dificultad es que, normalmente, los recursos computacionales disponibles son incompatibles entre s´ ı, y por tan- to no se pueden lanzar simulaciones en todos ellos de una forma totalmente inmediata. Para resolver este problema, hemos creado cuatro herramientas que permiten procesar eficientemente cientos o miles de simulaciones: el TaskManager as a Service, el General Workload Manager, el Auto-calibrador, y la reescritura del n´ ucleo del simulador para utilizar OpenCL. Para caracterizar el TaskManager as a Service, hemos utilizado el enfoque que se adopta en computaci´ on en la nube, es decir, una taxonom´ ıa de modelos de computaci´ on que com´ unmente consiste en la Infraestructura como Servicio (IaaS), Plataforma como servicio (PaaS) y Software como Servicio (SaaS). En todos estos modelos de computaci´ on en la nube se presenta una interfaz al usuario, y se abstrae el contenido de las capas inferiores, definiendo as´ ı un servicio nuevo. Por ejemplo, el IaaS abstrae el hardware de varios equipos a trav´ es de las m´ aquinas virtuales, y le ofrece al usuario la posibilidad de poner en marcha y administrar xi m´ aquinas virtuales. Hemos presentado por tanto un modelo de computaci´ on que se adapta a esta taxonom´ ıa para mantener un lenguaje com´ un con otros investigadores. La idea detr´ as de la TMaaS es aislar el acceso a los recursos inform´ aticos, y ofrecer al usuario la posibilidad de definir y gestionar tareas computacionales. En cada tarea computacional hay que definir un conjunto de componentes: el entorno de ejecuci´ on, la aplicaci´ on que se desea lanzar y el conjunto de recursos de entrada y de salida. Estos componentes deben ser proporcionados por el usuario para que el TMaaS pueda gestionar la tarea de manera transparente en los recursos computacionales disponibles, sean estos o no homog´ eneos. Por un lado el TMaaS se encarga de la comunicaci´ on con el sistema de colas o sistema operativo que est´ e instalado en cada recurso computacional, al igual que del despliegue de m´ aquinas si se trata de un recurso de computaci´ on en la nube, y de la gesti´ on y monitorizaci´ on de la tarea concreta. Por otro lado, el TMaaS ofrece al usuario el control de las tareas, para que pueda gestionarlas, independientemente de la naturaleza de las mismas. De esta manera resolvemos el problema de que la soluci´ on quede ligada a un campo concreto. Para implementar y probar el TMaaS hemos desarrollado el General Workload Manager (GWM). Esta herramienta cumple con los requisitos antes mencionados, y permite al usuario utilizar los recursos inform´ aticos heterog´ eneos de una manera transparente. El GWM tiene una arquitectura cliente-servidor, y utiliza REST para comunicar ambos actores, lo cual permite descubrir las caracter´ ısticas de la herramienta con facilidad. Como cliente, hemos desarrollado dos versiones: un cliente de l´ ınea de comandos que permite gestionar el sistema completo desde un terminal UNIX, y un cliente habilitado para web que permite al usuario controlar el comportamiento del servidor desde un navegador web. Esta aplicaci´ on web se ha construido con tecnolog´ ıas modernas para que la comunicaci´ on con el servidor sea m´ ınima, proporcionando una experiencia s´ olida y r´ apida para el usuario. La estructura del GWM ha sido dise˜ nada para que sea expansible, de tal modo que pueda proporcionar soporte a distintos recursos computacionales de manera transparente. Mediante esta estructura, se han implementado m´ odulos para el GWM de comunicaci´ on con varios shells, como bash, sh o ksh, y para comunicarse con varios sistemas de colas, como PBS/Torque o SGE. Para aprovechar las soluciones modernas de cloud computing de IaaS, tambi´ en hemos implementado el soporte con varios proveedores de cloud computing, incluyendo CloudStack, OpenStack, y Amazon EC2, de tal manera que un usuario puede solicitar la instanciaci´ on de nuevos recursos computacionales en cualquiera de estas plataformas, y el GWM los muestra de manera transparente para la ejecuci´ on de las tareas definidas. xii Utilizando el GWM hemos sido capaces de realizar la mayor´ ıa de las simulaciones que se presentan en esta tesis en tres cl´ usteres de HPC, que tienen tanto el hardware como el sistema de colas incompatible entre si. En cualquier caso, el usuario s´ olo tuvo que definir la tarea que quer´ ıa que se ejecutase, y el GWM se encarg´ o del lanzamiento y monitorizaci´ on de la tarea en los recursos computacionales disponibles. Otra de las soluciones desarrolladas para abordar el problema de c´ alculo es un autocalibrador. Todas las simulaciones de dispositivos electr´ onicos presentados en esta tesis necesitan ser calibradas con alguna fuente externa. Por lo general, se utilizan datos experimentales cuando est´ an disponibles, pero tambi´ en se puede calibrar contra datos de simulaciones m´ as precisas, como NEGF o Monte Carlo. En ambos casos, la calibraci´ on requiere que el usuario averig¨ ue los par´ ametros de entrada del simulador mediante ensayo y error. Este proceso es costoso y lento. Para mejorarlo hemos desarrollado un auto-calibrador que utiliza un algoritmo gen´ etico para encontrar los valores de los par´ ametros que ajustan el comportamiento del dispositivo a la curva de calibraci´ on deseada. Esta herramienta utiliza el GWM como infraestructura para desplegar los cientos o miles de tareas que ser´ an necesarios hasta alcanzar un calibrado suficientemente preciso. Los resultados obtenidos con este auto-calibrador han sido muy satisfactorios, con curvas de calibraci´ on m´ as ajustadas que cuando se calibra manualmente, y sin interacci´ on del usuario alguna, m´ as all´ a de definir el dispositivo, la curva de calibraci´ on deseada y los valores iniciales de los par´ ametros. El simulador que estamos utilizando est´ a implementado en C, utilizando MPI para comunicar los nodos de computaci´ on de memoria distribuida que se quieren utilizar. Esta implementaci´ on est´ a muy bien probada y optimizada, as´ ı que no hay mucho margen de mejora posible. No obstante, nuevas arquitecturas como unidades de procesamiento gr´ afico de prop´ osito general (GPGPU) o aceleradores como el Intel Xeon Phi, est´ an surgiendo como una buena alternativa para alcanzar rendimientos muy elevados. Estas arquitecturas est´ an m´ as orientadas a sistemas con matrices densas, puesto que el modelo de computaci´ on de hilos que presentan favorece una carga de trabajo homog´ enea entre ellos. En nuestro caso, dado que utilizamos elementos finitos en los simuladores que ejecutamos, nuestras matrices son dispersas, lo que da lugar a un problema m´ as complicado y no tan explorado. Para utilizar estas nuevas arquitecturas, hemos implementado las operaciones del n´ ucleo de los simuladores, que es la parte m´ as costosa computacionalmente, en OpenCL, un lenguaje que permite ejecutar c´ odigo en paralelo en arquitecturas GPGPU o Xeon Phi, entre otras. Este trabajo es preliminar, pero ya hemos realizado algunas publicaciones con los resultados obtenidos y se presentan en la xiii bibliograf´ ıa. En conclusi´ on, el autor empez´ o esta tesis con el objetivo de avanzar el conocimiento existente en dispositivos semiconductores nanom´ etricos. Concretamente seleccion´ o el an´ alisis de variabilidad como un problema que exige una combinaci´ on interesante de diversas habilidades. Por una parte, requiere conocimiento de los mecanismos f´ ısicos que afectan al comportamiento de los semiconductores, y tambi´ en de los procesos de fabricaci´ on, debido a su impacto en la variabilidad bajo estudio. Por otra parte, requiere herramientas potentes para simular miles de simulaciones y as´ ı comprender el efecto de las fuentes de variabilidad. Durante el desarrollo de esta tesis se han estudiado dos fuentes de variabilidad distintas, utilizando un simulador de arrastre-difusi´ on y otro de tipo Monte Carlo. Estas fuentes de variabilidad se han estudiado en distintos tipos de dispositivos electr´ onicos, con distintas aleaciones y con varios tama˜ nos de puerta diferentes. Finalmente, se han desarrollado herramientas novedosas con las que poder desplegar las simulaciones en recursos computacionales heterog´ eneos y optimizar el tiempo de simulaci´ on. Contents 1 Introduction 1 1.1 Motivation.................................... 1 1.2 Variabilitysources ............................... 3 1.3 Computationalproblem............................. 9 1.4 Outline ..................................... 13 1.5 Listofpublications ............................... 14 2 3D Simulation Study of Work-Function Variability in a 25 nm Metal-Gate Fin- FET with Curved Geometry using Voronoi Grains 19 3 Study of Metal-Gate Work-Function Variation using Voronoi cells: comparison of Rayleigh and Gamma distributions 21 4 Statistical study of the influence of LER and MGG in SOI MOSFET 23 5 Comparison of Fin Edge Roughness and Metal Grain Work Function Variability in InGaAs and Si FinFETs 25 6 General Workload Manager: a Task Manager as a Service 27 7 Conclusion 29 7.1 Futurework................................... 32 Bibliography 33 List of Figures 41 ii Contents List of Tables 43 CHAPTER 1 INTRODUCTION 1.1 Motivation Electronic technology has a deep impact in today’s society, as well as in science. Society has introduced new several solutions in both personal and professional environments. Similarly, scientific research of all kinds take advantage of the possibilities that technology provides. Modern improvements had provided science the tools it needs to advance at a faster pace. A representation of how important this factor is in modern society and science, is the high economical impact that several technological corporations have in the worldwide market. Most of these improvements are backed up by transistors, which are the main component of any digital electronic device, specifically of central processing units (CPUs), graphic processing units (GPUs), and volatile memory (RAM). Foundries design, manufacture and sell transistors as a component for digital devices. These foundries rely on cutting edge knowledge to provide faster, less power consuming, smaller or cheaper solutions. To achieve these improvements, there has to be advance in the many steps of the fabrication process [1]. In order to foresee the evolution of transistors, hence technology, a group of semiconductor industry experts publish the ITRS [2, 3], a road map that characterizes the evolution that transistors have to follow in order to maintain the desired rhythm of advance. Problems that may arise due to the continuous miniaturization of the transistors are also explained in this document. Using the ITRS, researchers can try to tackle the foreseen problems before they actually occur, so they do not hinder the advance of technology. Semiconductor device simulations are a powerful tool that allow scientists to save time and money, by being able to predict how a device will behave without the need to create 2Chapter 1. Introduction the manufacturing pipeline [4–6]. In order to understand the behavior of the real device, the simulation process has to be as precise as possible. The drift-diffusion approach, which calculates only the current and moment conservation of the carriers, is a simple but fast solution. When coupled with corrections for the quantum confinement like density gradient [7], this method, once calibrated, is able to accurately simulate the subthreshold characteristics of state-of-the-art semiconductor devices in the nanometre regime. The next step in complexity could be the hydrodynamic approximation. This model is similar to the previous one, but includes out of equilibrium effects that improve the simulation in certain situations. A more complex simulation methodology is to use Monte Carlo, which considers the particles individually or as meta-particles, and the scattering processes along the device, to obtain a very good precision, specially in the on regime [8–10]. The downside of this approach is that each simulation is very costly in comparison with drift-diffusion. An even more precise simulation method is based on Non-Equilibrium Green Functions and it solves the quantum transport with the Schr¨ odinger equation [11]. As expected, this simulator is the most costly of the ones presented. One of the problems that we want to simulate, and hence give information back to the scientific community and foundries, is the variability sources that appear in the process of manufacturing the nanodevice [12]. This has a very big impact on the devices behavior, decreasing their performance or some times generating operational failures [12–15]. In order to characterize the variability as well as possible, we have to run thousands of simulations, to obtain a more reliable statistical insight on the nature and effect of the variability sources [16]. Therefore, the selected simulation technique has to be simple enough to allow us to deploy as many simulations as possible while keeping an accuracy level that grants us meaningful information. In our case that will be the drift-diffusion simulator with quantum corrections, calibrated against experimental data when possible. Another problem that we also want to tackle is the lack of general solutions that allow a scientist to easily manipulate the computing capabilities needed in order to launch thousands of simulations, or any other large workload. The existing solutions are too complex, or tailored to certain problems and limited by their infrastructure. In summary, we want to focus our work in two different fronts: i) to study the variability sources that arise in modern nanodevice architectures, characterizing them and their effect on the devices, and ii) to develop the computational tools that we need in order to be able to manage thousands of simulations and post process the results. 1.2. Variability sources 3 1.2 Variability sources Once the semiconductor nanodevice is defined and ready to be produced, certain deviations from the blueprints are to be expected. These deviations are random, and can be of two types: related to different stages of the building process, or inherent to the semiconductor material and physics. The effect of these deviations on the behavior of the device is called variability, and the nature of the deviation is the variability source. These intrinsic fluctuations [17], increase when the device is scaled down, which aggravates its importance. We want to study different variability sources, and how are they related to the scaling of the device. Each variability source under study will have an impact on the device characteristics, that will depend on the parameters that characterize the variability source. Studying the relation between those parameters and the impact on the device characteristics, we can conclude which steps had to be taken in order to minimize the negative effect of the variability source on the device behavior. Similarly, this allows us to compare the variability sources between themselves. To apply the variability source, considering that their nature is the deviation from the ideal device, we modified the source code of the numerical simulator to account for the difference. Our approach has to be as much realistic as possible, without modifying the simulator more than necessary. All the modifications in the code have to be possible to deactivate, in order to restore the original behavior. Also, because the variability is a statistical process, we need more than one simulation to account for the effect of the variability source. More concretely, considering that some parameters that characterize the variability are not fixed but also are variables, we may want to deploy hundreds or thousands of simulations to have good statistics and a proper characterization of the variability source. The methodology chosen is common to all the variability sources under study: we analyze the effect of the variability via a perturbation process. This perturbation methodology is composed of: 1. The perturbation profile is any kind of file or set of files that represent how the device has to be perturbed. This allows to take the actual variability source out of the simulator, so a single compilation of the simulation can deal with different instances of perturbations. This perturbation profile is generated offset, and deployed with the simulator and the corresponding device characteristics, like the mesh, in order to have a full simulation of the source under variability. 10 Chapter 1. Introduction capabilities available will return a better solution to their problem. Similar problems raised in other fields like oceanography or biology, has been solved via creating solutions tailored to a particular problem [44–46]. Because of this, the solutions are only valid for the correspondent field of study. Another solution based on science gateways is close to solving that problem [47], but it only provides a community-specific set of tools, and does not allow a scientist to deploy his code independently. Our objective is the optimization of the simulation time, in order to have the results as soon as possible or to have more simulations that allows for a better result. The problem is having to use computational resources that are incompatible between themselves. In our case, deploying a big amount of simulations is a key point in order to properly analyze the effect of the variability source on the device behavior. Therefore, we have developed four tools to efficiently process hundreds or thousands of simulations, and we briefly describe them in the following subsections: the Task Manage as a Service, the General Workload Manager, the Self-Calibrator, and the OpenCL implementation of the simulator engine. 1.3.1 Task Manager as a Service The cloud computing environment has defined an approach that we can adopt in order to tackle the presented computational problem. The taxonomy of cloud computing services [48] is commonly represented via the Infrastructure as a Service (IaaS), Platform as a Service (PaaS), and Software as a Service (SaaS). In all these cloud computing models, there is an abstraction of certain layers of computation, and an interface is offered to the user so he can deal with them without knowing their internal details. For example, the IaaS abstracts the hardware of several machines via virtual machines, that can be launched and managed by the user. We present the Task Manager as a Service, which solves the aforementioned computational problem. This computing model has also been implemented in the form of the General Workload Manager, explained in the next subsection. The idea behind the TMaaS is to isolate the access to the computing resources, and to present the user with the ability to define and manage tasks. We define a computational task as a set of components: the environment, the executable that is to be launched, the possible set of input and output resources. The TMaaS is a layer that allows a user to define and manage the life cycle of tasks using the available computing resources transparently. 1.3. Computational problem 11 Once the TMaaS is up and running, the only interaction of the user with the computational resources is the task. With this unit, it is very easy to monitor the tasks in several ways. It also allows to schedule the tasks following different scheduling mechanisms that will adapt to the time deadlines, the status of the computing resources, or the scientist needs. This computing model does not depend on the field that the scientist is working on, so its applicable to the aforementioned cases, and of course to our nanodevice simulator. 1.3.2 General Workload Manager To implement and test the TMaaS we have developed the General Workload Manager (GWM). This tool complies with the requirements mentioned before, and allows the user to use heterogeneous computing resources in a transparent way. The tool was developed following a client-server architecture. A server is installed that monitors some ports for REST petitions. By using REST, the application is easy to extend and to discover from the user point of view. The client that communicates with the server via the REST architecture is controlled by the user. We have implemented two different clients with the same capabilities: one command line client which allows to manage the full system from a UNIX terminal, and one web enabled client that allows the user to control the behavior of the server from a web browser. This web browser application is developed using modern technologies for communicating with the server, and displaying the state, to provide a easy, fast and modern experience to the user. Using a Model View Controller paradigm, with AJAX in order to maintain the state of the application in the client, and REST to communicate with the server, the result is that the management of thousands of tasks is not more difficult for the user than that of an online mail client. The GWM is expansible because it has been conceived as a plugin-based architecture. This allowed up to implement modules for the GWM to communicate with several shells, like bash, sh, or ksh. The same plugin-based architecture is used to facilitate the access to queuing engines, like PBS/Torque or SGE, so the user does not have to deal with the differences between them. Also, the GWM is capable of communicating with several cloud computing providers, like CloudStack, OpenStack, Amazon EC2, and more. So the instantiation of new computing resources is done transparently. One of the developed schedulers, called intelligent scheduler, allows the user to define a stopping metric that can be calculated from the simulation results, and the GWM will deploy only the required simulations to obtain that metric. This is done by calculating the value of the metric after each simulation and using that 12 Chapter 1. Introduction information as feedback. Using the GWM we were able to deploy most of the simulations that are presented in this thesis. In most cases, the simulations were run in three different high performance clusters, with incompatible hardware and different task management enqueuing. In any case, the user only had to define the computing task and the GWM would take care of the task management. 1.3.3 Self-calibrator Another of the solutions developed to tackle the computational problem is a self-calibrator. All the nanodevice simulations presented in this thesis need to be calibrated to some external source. Usually the source is either experimental data, when available, or results from more precise simulations, like NEGF or Monte Carlo. In both cases, the calibration requires the user to guess the right values for the parameters that characterize our drift-diffusion simulator and that fit the behavior of the device as close as possible. To find these parameters, the original procedure is to change their values, simulate the device, compare the behavior and repeat. We developed a self-calibrator that uses the device specifications and the desired behavior to obtain the values for the parameters that closely match that desired behavior. This selfcalibrator uses a genetic algorithm to decide the values of the parameters for each iteration, and the GWM to manage the tasks. 1.3.4 OpenCL implementation The simulator that we are using is implemented in C with MPI to take account of the communication between nodes. This implementation is very well tested and optimized, so no much margin of improvement is possible. New architectures like General Purpose Graphics Processing Units (GPGPUs) or accelerators, like the Intel Xeon Phi, are being used nowadays to obtain faster running times [49], even if they are tailored to dense systems instead of the sparse we are working with. We have implemented the required operations to transfer the engine of our simulator from the MPI-enabled to a OpenCL implementation, which can be run in several different architectures without changing the source code. This is still a work in progress, but the preliminary articles already published in the topic are listed in section 1.5. 1.4. Outline 13 1.4 Outline In the following chapters we provide the key articles that represent the main body of work for this thesis. In all these articles, the author of the thesis has been the main contributor, or a coauthor that highly contributed to the paper. These articles have been either published in JCR journals or in high quality international conferences: IEEE Transactions on Electron Devices, Semiconductor Science and Technology, International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), and IEEE International Conference on Communication (CORE A). This selection of articles has been made to delve into the main points mentioned in the introduction, and to have a more complete representation of the work carried out doing this thesis, the full reference list in section 1.5 should be considered. In that section we list a full compendium of the journal publications and conference presentations related to this thesis, which include journals like IEEE Electron Device Letters and IEEE Internet Computing. In chapter 2, we explain the Voronoi method introduced in section 1.2.2, to model the Metal Gate Granularity. We also analyze the effect of changing the device body shape from a complete square to a rounded corner shape. The first measures of MGG variability were presented for a 25 nm gate length Silicon SOI FinFET device. This presentation of the Voronoi method was well received by the scientific community and the findings of this article where cited several times. The Voronoi method is being used today by several researchers to model the MGG variability. Following a recently published approach to calculate the MGG variability via the Rayleigh distribution [39], in chapter 3, we compare our Voronoi model with the Rayleigh approach, using the equivalent Gamma distribution that arises naturally from the grain area distribution of a Voronoi diagram. We also compare both algorithms with TEM images. We found that our approach is way more suitable to match the experimental results, and that the Rayleigh distribution overstates the value of the variability. The analysis was done with experimental data of different materials, provided by Dr. Kenji Ohmori, from the Nanotechnology Laboratory of Waseda University, Tokyo [30]. Using both the Line Edge Roughness, explained in section 1.2.1, and the Metal Gate Granularity, we present in chapter 4 an analysis of the effect of both these variability sources in a 25 nm Silicon SOI FinFET device, the same device that was used in chapter 2. This is the first article in which we present our methodology to generate LER profiles, as an application of the same perturbation pipeline. We have found that the MGG has a negative effect in the 14 Chapter 1. Introduction power consumption and the switching speed, decreasing the quality of the device, as the grain size grows. Similarly for LER, we have found that both the correlation length and the rms height have a negative effect in the variability of all figures of merit, but more pronounced in the case of the rms height for the studied parameters. In general, this device shows more sensitivity for LER than for MGG. In order to expand the knowledge of both variability sources and device fabrication, we simulated the same variability sources as in chapter 4, but for two state-of-the-art devices: a Silicon SOI FinFET, and an InGaAs III-V-OI FinFET with a similar shape. In both cases, we have also reduced the size of the device from 25 nm to 10.7 and 10.4 nm, respectively. We used data from Monte Carlo simulations to calibrate the simulator, because there was no experimental data available at the moment. The results of this comparison are shown in chapter 5, where we found that in the sub-threshold region, the InGaAs device is more resilient to MGG variability than the Silicon device, specially for the subthreshold swing, and produces similar results for the LER variability. Nevertheless, the results for on-current present the opposite trend. To obtain the previous results, we have to run several thousands of simulations, to account for the different devices, variability sources and parameters. The proposed Task Manager as a Service infrastructure was used to test its validity in real world situations. In chapter 6 we present the General Workload Manager, our implementation of the TMaaS computing model. We have applied the GWM to different scenarios to show how it can handle workloads independently of the nature of them, and we also present how it can deal with three incompatible clusters and a cloud provider in order to deploy and manage the computational tasks. Finally, in chapter 7, we present the conclusions of the thesis and of the articles reproduced in the following chapters, along with the future work that naturally arises from the articles written in this thesis. 1.5 List of publications This is the list of publications written by the author throughout the development of the thesis. Articles in peer reviewed journals: •G. Indalecio, A.J. Garcia-Loureiro, N. Seoane, and K. Kalna, Study of Metal-Gate Work-Function Variation Using Voronoi Cells: Comparison of Rayleigh and Gamma Distributions, IEEE Transactions on Electron Devices, 63, pp. 2625-2628, 2016 1.5. List of publications 15 •G. Indalecio, F. Gomez-Folgar, and A.J. Garcia-Loureiro, GWMEP: Task-Manager- as-a-Service in Apache CloudStack, IEEE Internet Computing, 20, pp. 42-49, 2016 •G. Indalecio, N. Seoane, M. Aldegunde, K. Kalna, and A. J. Garcia-Loureiro, Variability Characterisation of Nanoscale Si and InGaAs Fin Field-Effect-Transistors at Subthreshold., Journal of Low Power Electronics, 11, pp. 256-263, 2015 •G. Indalecio, M. Aldegunde, N. Seoane, K.Kalna and A. J. Garcia-Loureiro, Statistical study of the influence of LER and MGG in SOI MOSFET, Semiconductor Science and Technology, 29, 045005, 2014 •N. Seoane, M. Aldegunde, D. Nagy, M.A. Elmessary, G. Indalecio, A.J. Garcia-Loureiro and K. Kalna Simulation study of scaled In0.53Ga0.47As and Si FinFETs for sub-16 nm technology nodes, Semiconductor Science and Technology, 31, 075005, 2016 •N. Seoane, G. Indalecio, M. Aldegunde, D. Nagy, M.A. Elmessary, A.J. Garcia-Loureiro, K. Kalna, Comparison of Fin-Edge Roughness and Metal Grain Work Function Variability in InGaAs and Si FinFETs, IEEE Transactions on Electron Devices, 63, pp. 1209-1215, 2016 •E. Coronado-Barrientos, G. Indalecio and A. Garcia-Loureiro, Study of basic vector operations on Intel Xeon Phi and NVIDIA Tesla using OpenCL, Annals of Multicore and GPU Programming, 2, 15, 2015 •N. Seoane, G. Indalecio, E. Comesana, M. Aldegunde, A. J. Garcia-Loureiro and K. Kalna, Random Dopant, Line-Edge Roughness, and Gate Workfunction Variability in a Nano InGaAs FinFET, IEEE Transactions on Electron Devices, 61, pp. 466-472, 2014 •N. Seoane, G. Indalecio, E. Comesa˜ na, A. J. Garcia-Loureiro, M. Aldegunde, and K. Kalna, Three-Dimensional Simulations of Random Dopant and Metal-Gate Workfunction Variability in an In0.53Ga0.47As GAA MOSFET, IEEE Electron Device Letters, 34, pp. 205-207, 2013 Articles published in international conferences: •G. Indalecio, F. Gomez-Folgar and A.J. Garcia-Loureiro, General Workload Manager: a Task Manager as a Service, IEEE International Conference on Communications, pp. 1859-1864, 2015 16 Chapter 1. Introduction •G. Indalecio, N. Seoane, M. Aldegunde, K. Kalna and A. J. Garcia-Loureiro, Variability characterisation of nanoscale Si and InGaAs FinFETs at subthreshold, 5th European Workshop on CMOS Variability, 2014 •G. Indalecio, N. Seoane, M. Aldegunde, K. Kalna, A. J. Garcia-Loureiro, Scaling of Metal Gate Workfunction Variability in nanometer SOI-FinFETs, 15th International Conference on Ultimate Integration on Silicon, pp. 105-108, 2014 •G. Indalecio, M. Aldegunde, A.J. Garcia-Loureiro, Static Multipole Method Applied to Boundary Conditions for Semiconductor Device Simulations The 2012 International Conference on High Performance Computing & Simulation, pp. 654-659, 2012 •G. Indalecio, A.J. Garcia-Loureiro, M. Aldegunde, and K. Kalna, 3D Simulation Study of Work-Function Variability in a 25 nm Metal-Gate FinFET with Curved Geometry using Voronoi Grains, 2012 International Conference on Simulation of Semiconductor Processes and Devices, pp. 149-152, 2012 •M.A. Elmessary, D. Nagy, M. Aldegunde, N. Seoane, G. Indalecio, J. Lindberg, W. Dettmer, D. Peri, A.J. Garcia-Loureiro and K. Kalna, Scaling/LER Study of Si GAA Nanowire FET using 3D Finite Element Monte Carlo Simulations, International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, pp. 52-55, 2016 •F. Gomez-Folgar, G. Indalecio, N. Seoane, A. J. Garcia-Loureiro, and T. F. Pena, Study of Point-to-Point Communication Latency for MPI Implementations in Cloud, The 22nd International Conference on Parallel and Distributed Processing Techniques and Applications, ACCEPTED, 2016 •F. Gomez-Folgar, G. Indalecio, A.J. Garcia-Loureiro and T.F. Pena, A Flexible Cluster System for the Management of Virtual Clusters in the Cloud, IEEE 17th International Conference on High Performance Computing and Communications, pp. 1693-1698, 2015 •M. Fortes, E. Comesa˜ na, G. Indalecio, J. Rodriguez, P. Otero, A. Garcia-Loureiro, M. Vetter, Design and Monte Carlo Simulation of a LED-based Optic Coupler, 17th International Conference on Computer Modelling and Simulation, pp. 577-581, 2015 1.5. List of publications 17 •A. Abdikarimov, G. Indalecio, E. Comesa˜ na, N. Seoane, K. Kalna, A.J. Garcia-Loureiro, A.E. Atamuratov, Influence of device geometry on electrical characteristics of a 10.7 nm SOI-FinFET, 17th International Workshop on Computational Electronics, pp. 247- 248, 2014 •N. Seoane, G. Indalecio and A.J. Garc´ ıa-Loureiro, K. Kalna, Impact of cross-section of 10.4 nm gate length In0.53Ga0.47As FinFETs on metal grain variability, 2016 International Conference on Simulation of Semiconductor Processes and Devices, ACCEPTED, 2016 •N. Seoane, G. Indalecio, E. Comesa˜ na, M. Aldegunde, A. J. Garcia-Loureiro and K. Kalna, WN and TiN metal gate workfunction variability in a 10.4 nm gate length In- GaAs FinFET, 17th International Workshop on Computational Electronics, pp. 239- 240, 2014 •N. Seoane, A. Garcia–Loureiro, E. Comesa˜ na, R. Valin, G. Indalecio, M. Aldegunde and K. Kalna, 3D simulations of random dopant induced threshold voltage variability in inversion–mode In0.53Ga0.47As GAA MOSFETs, 2012 International Conference on Simulation of Semiconductor Processes and Devices, pp. 392-395, 2012 Articles published in national conferences: •G. Indalecio, F. Gomez-Folgar and A. J. Garcia-Loureiro, Comparison of state-of-the- art distributed computing frameworks with the GWM, 10th Spanish Conference on Electron Devices, 2015 •G. Indalecio, M. Aldegunde, K. Kalna, A. Garcia-Loureiro, Study of statistical variability in nanoscale transistors introduced by LER, RDF and MGG, 2013 Spanish Conference on Electron Devices, pp. 95-98, 2013 •E. Coronado-Barrientos, G. Indalecio and A.J Garcia-Loureiro, Implementation and performance analysis of the AXPY, DOT, and SpMV functions on Intel Xeon Phi and NVIDIA Tesla using OpenCL, Segundas Jornadas de Programacion Paralela Multicore y GPU, 2015 •E. Coronado-Barrientos, A. Garcia-Loureiro, G. Indalecio N. Seoane, Implementation of numerical methods for nanoscaled semiconductor device simulation using OpenCL, 10th Spanish Conference on Electron Devices, 2015 18 Chapter 1. Introduction •F. Gomez-Folgar, G. Indalecio, E. Comesana, A. J. Garcia-Loureiro, T. F. Pena, A tool to deploy nanodevice simulations on Cloud, 10th Spanish Conference on Electron Devices, 2015 CHAPTER 2 3D SIMULATION STUDY OF WORK-FUNCTION VARIABILITY IN A 25 NM METAL-GATE FINFET WITH CURVED GEOMETRY USING VORONOI GRAINS Following is a reproduction of an article of which the author of this thesis is a main contributor. This is a verbatim reproduction, and the original can be found online at the URL http://in4.iue.tuwien.ac.at/pdfs/sispad2012/8-3.pdf, or with the following information: International Conference on Simulation of Semiconductor Processes and Devices, 2012, pp. 149-152 G. Indalecio, A.J. Garc´ ıa-Loureiro, M. Aldegunde and K.Kalna CHAPTER 6 GENERAL WORKLOAD MANAGER:ATASK MANAGER AS A SERVICE Following is a reproduction of an article of which the author of this thesis is a main contributor. This is a verbatim reproduction, and the original can be found online at the following URL http://dx.doi.org/10.1109/ICCW.2015.7247451, or with this information: IEEE International Conference on Communications - Workshop on Cloud Computing Systems, Networks, and Applications, pp. 1859-1864, 2015 G. Indalecio, F. G´ omez-Folgar and A.J. Garc´ ıa-Loureiro CHAPTER 7 CONCLUSION The author started this thesis with the objective of advancing the existing knowledge of semiconductor devices in the nanoscale regime. In order to do that, the analysis of variability sources was selected as an interesting combination that involves several abilities. On the one hand, it requires knowledge of the physical mechanisms that affect the semiconductors behavior, and also of the manufacturing process, because of its impact on the variability to be studied. On the other hand, it requires powerful tools to be able to simulate thousands of devices to understand the effect of small changes on the device characteristics. As a starting point we developed a pipeline based in a perturbation model that allows to modify the simulation to account for different variability sources, without many changes in the simulator code. Using this pipeline, we have implemented two variability sources: the Metal Gate Granularity (MGG) and the Line Edge Roughness (LER). These variability sources have been applied to several devices: Silicon and InGaAs FinFETs and gate-all-around Nanowires. These tools are currently being used by other authors in the Universities of Santiago de Compostela and in Swansea University, to further study the effect of that variability sources. The simulator that was used and modified is a drift-diffusion 3D simulator. It uses density gradient corrections to account for the quantum effects that arise when shrinking the device under certain sizes. The device is modeled with a tetrahedral mesh, because the simulator uses finite elements to discretize the problem. Several meshes where generated for this simulator, with different shape, size or density, to manage the associated convergence problems that can happen if the density is too low and to explore different architectures. The Metal Gate Granularity was studied using our own approach which is based on the 30 Chapter 7. Conclusion mathematical structure of the Voronoi diagram. To implement the Line Edge Roughness, we have developed a inverse Fourier transform of a spectra. To obtain comprehensive data of the effect of this variability sources in semiconductor devices, we need to change the parameters that define the sources of variability, and also use different devices. We deployed several thousands of simulations in several computing resources thanks to the General Workload Manager, which was also developed during all the period of this thesis. The following bullet list summarizes some of the findings presented in the previous chapters that were achieved throughout this thesis: •We have developed a pipeline based in a perturbation model, that allows to implement several variability sources in our semiconductor device simulators. This pipeline introduces the variability source as a perturbation, without many changes in the original source of the simulator. This is currently being used by several scientists from two different research institutions. •One of the most important applications of this pipeline, the Voronoi approach for the Metal Gate Granularity variability, was presented and validated against experimental data. These values have been provided by Dr. Kenji Ohmori [30], and consisted on TEM images of different materials: TiN and Ru. In both cases, our Voronoi approach generates a grain distribution that fits properly the experimental grain distribution, with p-values of 0.17 and 0.42, for TiN and Ru, respectively. We have also checked with the same experimental data an option developed by another authors: the Rayleigh approach, and concluded that is not adequate to account for the grain distribution of MGG simulations. The same fit to the same experimental data resulted in p-values of 3 ×10−14 and 0.0029 for TiN and Ru. We have also demonstrated that the variability calculated with Rayleigh overestimates the real variability by 11.9% and 7.14% for TiN and TaN materials, which our approach does not. •Using the presented pipeline, we have analyzed the impact of the MGG and LER sources of variability in the performance of several state-of-the-art semiconductor devices. This is a key point to understand the process of device fabrication and how it has an impact on the device characteristics. We have simulated 10.7 and 10.4 nm gate length Silicon and InGaAs devices modeled according to the ITRS predictions. Those simulations were calibrated using the data from a more precise but slower simulator, based on 3-D Non-Equilibrium Green’s Functions, because no experimental data was 31 available at the moment. From this comparison we have found that the InGaAs device is more resilient to the variability sources in the subthreshold regime. The behavior for the on-current variability is the opposite, having more sensitivity in the InGaAs device. •Independently of the device, for the MGG we have found and characterized a dependency of the variability on threshold voltage, off current and subthreshold swing with the inverse of the root square of the grain size. Also, we have found that the device power consumption and switching speed diminish when the grain size if large. This means that not only a variation of the parameters is to be expected, but also a net reduction of the quality of the device. •Regarding the LER, we have found that the effect of the correlation length is smaller than the effect of the root mean square of the height, for the parameters that are usually studied. This result is found to be applicable for both Silicon and InGaAs FinFETs. We have also studied the impact of correlated versus uncorrelated LER, and we have concluded that the uncorrelated LER has more impact on the variability because it changes the device width along the current flow direction. •In order to further understand the effect of the variability sources, we have implemented and presented a Fluctuation Sensitivity Map (FSM) to study the MGG variability. The FSM shows us that we can detect the position in the device where the oxide is wider, because it reduces the sensitivity of the device to the grain orientation. Also, we have found that a reduction of the width of the device body near the top of the Fin has a similar effect of a oxide buffer: it reduces the sensitivity. •Finally, regarding the infrastructure to manage tasks, the GWM, we have tested it using heterogeneous work loads, computing resources incompatible between themselves, different queuing engines for the tasks, and cloud infrastructures. We have also benchmarked the system with a 16 nodes cloud machine, and found that the GWM is capable of keeping a mean usage of 14.98 nodes during the simulations, leveraging the available resources. Almost all the simulations of this work have been carried with this tool, and the results are positive. 32 Chapter 7. Conclusion 7.1 Future work We present here a comprehensive list of future tasks that can be carried in order to continue the work started in this thesis. •The MGG variability can be further improved by taking into consideration the effect of the gate-first and gate-last techniques. Doing this, we could generate Voronoi grains that represent the gate in the two possible implantation techniques and compare them directly. •The LER variability source can be applied in different lines of the device. We have only used the most important, the FER, which is applied in the body of the device in the direction of the current flow. Applying this variability along the gate, transverse to the device, may prove useful. •The FSM can be applied to another variability source other than MGG, and also for more devices geometry in order to improve our knowledge of the sensitivity of the device. •GWM is being expanded right now to implement new mechanisms, like dependency between tasks that allows the user to define not only a task but a pipeline of data between tasks. This would allow complex interactions to be carried on automatically. Bibliography [1] Kelin J. Kuhn, Martin D. Giles, David Becher, Pramod Kolar, Avner Kornfeld, Roza Kotlyar, Sean T. Ma, Atul Maheshwari, and Sivakumar Mudanai. Process Technology Variation. IEEE Transactions on Electron Devices, 58(8):2197–2208, aug 2011. [2] The International Technology Roadmap for Semiconductors (ITRS), 2009, http://www.itrs2.net/. 2009. [3] The International Technology Roadmap for Semiconductors (ITRS), 2011, http://www.itrs2.net/. 2011. [4] T Matsukawa, S O, K Endo, Y Ishikawa, H Yamauchi, Y X Liu, J Tsukada, K Sakamoto, and M Masahara. Comprehensive Analysis of Variability Sources of FinFET Characteristics. In Symposium on VLSI Technology, pages 159–160, 2009. [5] R.E. Shannon. Introduction to the art and science of simulation. In 1998 Winter Simulation Conference. Proceedings (Cat. No.98CH36274), volume 1, pages 7–14. IEEE, 1998. [6] A.B. Fortes, J. Figueiredo, and M.S. Lundstrom. Virtual Computing Infrastructures for Nanoelectronics Simulation. Proceedings of the IEEE, 93(10):1839–1847, oct 2005. [7] Antonio Jesus Garcia-Loureiro, Natalia Seoane, Manuel Aldegunde, Ra´ ul Valin, Asen Asenov, Antonio Martinez, and Karol Kalna. Implementation of the Density Gradient Quantum Corrections for 3-D Simulations of Multigate Nanoscaled Transistors. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 30(6):841– 851, jun 2011. 34 Bibliography [8] Jari Lindberg, Manuel Aldegunde, Daniel Nagy, Wulf G Dettmer, Karol Kalna, Antonio Jesus Garcia-Loureiro, and Djordje Peric. Quantum Corrections Based on the 2-D Schr¨ odinger Equation for 3-D Finite Element Monte Carlo Simulations of Nanoscaled FinFETs. IEEE Transactions on Electron Devices, 61(2):423–429, feb 2014. [9] Manuel Aldegunde, Antonio Jesus Garcia-Loureiro, and Karol Kalna. 3D Finite Element Monte Carlo Simulations of Multigate Nanoscale Transistors. IEEE Transactions on Electron Devices, 60(5):1561–1567, may 2013. [10] Manuel Aldegunde and K. Kalna. Energy conserving, self-force free Monte Carlo simulations of semiconductor devices on unstructured meshes. Computer Physics Communications, 189:31–36, apr 2015. [11] Antonio Martinez, Manuel Aldegunde, Natalia Seoane, Andrew R. Brown, John R. Barker, and Asen Asenov. Quantum-Transport Study on the Impact of Channel Length and Cross Sections on Variability Induced by Random Discrete Dopants in Narrow Gate-All-Around Silicon Nanowire Transistors. IEEE Transactions on Electron Devices, 58(8):2209–2217, aug 2011. [12] Xiao Zhang, Jing Li, M Grubbs, M Deal, B Magyari-Kope, B M Clemens, and Y Nishi. Physical model of the impact of metal grain work function variability on emerging dual metal gate MOSFETs and its implication for SRAM reliability. In IEEE Electron Device Letters, pages 1–4, 2009. [13] K. Sivasankaran, P S Mallick, and T R K Kumar Chitroju. Impact of device geometry and doping concentration variation on electrical characteristics of 22nm FinFET. In 2013 IEEE International Conference ON Emerging Trends in Computing, Communication and Nanotechnology (ICECCN), number Iceccn, pages 528–531. IEEE, mar 2013. [14] Nattapol Damrongplasit, Sung Hwan Kim, Changhwan Shin, and Tsu-Jae King Liu. Impact of Gate Line-Edge Roughness (LER) Versus Random Dopant Fluctuations (RDF) on Germanium-Source Tunnel FET Performance. IEEE Transactions on Nanotechnology, 12(6):1061–1067, nov 2013. [15] E Baravelli, A Dixit, R Rooyackers, M Jurczak, N Speciale, and K De Meyer. Impact of Line-Edge Roughness on FinFET Matching Performance. IEEE Transactions on Electron Devices, 54(9):2466–2474, sep 2007. Bibliography 35 [16] D Reid, C Millar, G Roy, S Roy, and Asen Asenov. Analysis of threshold voltage distribution due to random dopants: A 100 000-sample 3-D simulation study. IEEE Transactions on Electron Devices, 56(10):2255–2263, 2009. [17] Natalia Seoane, Antonio Jesus Garcia-Loureiro, K. Kalna, and Asen Asenov. Impact of intrinsic parameter fluctuations on the performance of HEMTs studied with a 3D parallel drift-diffusion simulator. Solid-State Electronics, 51(3):481–488, mar 2007. [18] Muhammad A. Elmessary, Daniel Nagy, Manuel Aldegunde, Natalia Seoane, Guillermo Indalecio, Jari Lindberg, Wulf Dettmer, Djordje Peric, Antonio J. Garcia-Loureiro, and Karol Kalna. Scaling/LER study of Si GAA nanowire FET using 3D Finite Element Monte Carlo simulations. 2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), pages 52–55, 2016. [19] Natalia Seoane, Guillermo Indalecio, E. Comesana, Antonio Jesus Garcia-Loureiro, Manuel Aldegunde, and K. Kalna. Three-dimensional simulations of random dopant and metal-gate workfunction variability in an In0.53Ga0.47As GAA MOSFET. IEEE Electron Device Letters, 34(2):205–207, feb 2013. [20] Natalia Seoane, Guillermo Indalecio, Enrique Comesana, Manuel Aldegunde, Antonio Jesus Garcia-Loureiro, and Karol Kalna. Random Dopant, Line-Edge Roughness, and Gate Workfunction Variability in a Nano InGaAs FinFET. IEEE Transactions on Electron Devices, 61(2):466–472, feb 2014. [21] Guillermo Indalecio, Natalia Seoane, Manuel Aldegunde, K Kalna, and Antonio Jesus Garcia-Loureiro. Scaling of metal gate workfunction variability in nanometer SOI- FinFETs. In 2014 15th International Conference on Ultimate Integration on Silicon (ULIS), number Dd, pages 105–108. IEEE, apr 2014. [22] Natalia Seoane, Guillermo Indalecio, Manuel Aldegunde, Daniel Nagy, Muhammad A. Elmessary, Antonio J. Garc´ ıa-Loureiro, and Karol Kalna. Comparison of Fin-Edge Roughness and Metal Grain Work Function Variability in InGaAs and Si FinFETs. IEEE Transactions on Electron Devices, 63(3):1209–1216, 2016. [23] A Dixit, K. G. Anil, E Baravelli, P. Roussel, A. Mercha, C. Gustin, M. Bamal, E. Grossar, R. Rooyackers, E. Augendre, M. Jurczak, S. Biesemans, and K. De Meyer. Impact of List of Tables