Detecting Outliers Using Modified Recursive PCA Algorithm For Dynamic Streaming Data

MENDEL — Soft Computing Journal, Volume 29, No.gk, .2+2K#2` 2023, Brno, Czech RepublicX ISSN: 1803-3814 (Printed), 2571-3701 (Online) https://doi.org/10.13164/mendel.2023.k.245 Evolutionary Optimization Techniques in Analog Integrated Circuit Designs Trang Hoang  , Bao Quoc Bui, Hoang Trong Nguyen, Phuc That Bao Ton Department of Electronics Engineering, Ho Chi Minh City University of Technology (HCMUT), Vietnam National University Ho Chi Minh City (VNU-HCM), Vietnam [email protected]  Abstract The proposed genetic algorithm (GA) particle swarm optimization (PSO) and modified PSO applied for the optimal design of a one-stage operational amplifier circuit with a current mirror load are studied in this work. The sizes of transistors are optimized using the mentioned algorithms for improved areas and performance parameters of the circuit. A number of performance parameters are collected from the data set created by GA, PSO and modified PSO to optimize the size of transistors and other design parameters. The Spectre simulator is chosen for the simulation of circuit parameters to obtain necessary for the GA, PSO and modified PSO. Post-optimization results justify that the modified PSO yield better results compared to the remaining GA and PSO, and all these methods are competitive with differential evolution regarding convergence speed, design specifications, and the optimal CMOS one-stage operational amplifier circuit parameters. Our source code is available at: https: // github. com/ hoangtranghcmut/ AI-in-Analog-Circuit-Design . Keywords: Optimization, Analog Integrated Circuit Design, Genetic Algorithm, Particle Swarm Optimization, One-stage Operational Amplifier, Low-power Design. Received: 05 October 2023 Accepted: 27 November 2023 Online: 07 December 2023 Published: 20 December 2023 1 Introduction Analog circuits play an essential role in integrated circuits (ICs) because they serve as the interface to connect the real world and the digital world signals. In contrast to the digital IC design strategy, the analog IC design has not been extensively automated due to its remarkable complexity [19,38]. Moreover, analog circuit sizing is considered highly composite, iterative, monotonous, and time-consuming. Thus, analog design complexities in the IC design field might be immeasurable. To overcome these mentioned drawbacks, analog design automation has been attracting significant attention from researchers worldwide as a feasible solution [25]. The analog design process consists of three major steps: choice of topology, component sizing, and layout extraction [42]. In the second step, experienced designers can size analog components by their perception and skills [41,15]. Nevertheless, if the circuit complexity rises, the search space gains accordingly, and it becomes a highly time-consuming method for the average designers to achieve the optimal design parameters, which is the bottleneck of the analog design procedure. Hence, automatically optimizing the sizes of the analog components in the circuits plays a vital role in quickly designing high-performance circuits [46,47]. In order for this automation process to be efficient, effective optimization techniques are necessary. To ensure a smooth, reliable search space for the optimization process, the CMOS analog IC design regarding the relations among aspect ratios, which is related to the lengths and widths of MOS transistors, needs to be implemented first. Therefore, to obtain the bestperformed analog IC design automation, initial design of the analog circuit should be accomplished prior to the application of optimization techniques for components’ sizes. Several classical optimization techniques are investigated for the CMOS analog design and classified into two main types: deterministic methods and statistical methods. Deterministic methods such as the Simplex method [37], Automatic process [30], Goal Programming [18], Dynamic Programming [23], etc., are mostly applied to optimization problems of minor size. Regarding statistical methods, they usually start by finding a suitable direct current (DC) operating point created by a proficient analog designer. After that, a simulation-based process is performed. However, the statistical methods are time-consuming and do not guarantee convergence towards the global optimum solution [27]. Regarding several drawbacks of classical optimization methods, the procedures are susceptible to starting points when the number of solution variables and the size of the solution space increase. In addition, the optimization process has frequent convergence to the local optimum solution or divergence or revisiting the same sub-optimal solution. Moreover, the optimization process requires the continuous and differen245 MENDEL — Soft Computing Journal, Volume 29, No.gk, .2+2K#2` 2023, Brno, Czech RepublicX tiable objective cost function (gradient search methods) and the piece-wise linear cost approximation (linear programming). Furthermore, classical methods usually encounter the problem of convergence and algorithm complexity (nonlinear programming). Thus, classical optimization methods are not primarily suitable for optimizing the whole large scale of the analog IC design process, which is highly complicated, constrained, and nonlinear. Heuristics-based approaches are essential studies to solve large-scale problems [59]. Previous studies used mathematical heuristic methods, such as local search (LS) [28], differential evolution [8], simulated annealing (SA) [45,50], tabu search (TS) [61,12], scatter search (SS) [31], genetic algorithm (GA) [33,62], etc. Among these mentioned algorithms, GA, based on the Darwinian principle of natural selection and concepts of natural genetics, has gained its popularity as an effective solution to large search spaces without being trapped in local minima. Circuit design optimization problems are formulated with various constraints, different variables, and multiobjective functions. Therefore, the optimization methods mentioned above usually require much more compile time when the problems become complex and involve a vast search space. Treating the drawbacks identified with these optimization methods by leveraging a new set of nature-inspired meta-heuristic optimization algorithms based on swarm intelligence [49] is proposed to investigate. The idea behind these algorithms was impressed by the collective behavior of decentralized, self-organized systems. Swarm intelligence-based approaches employ a population of particles combining locally with each other variables and globally with their environment spaces. Even though the particles relate to the conventions, there is no concentrated handle over the behavior of each particle. Hence, the complexity of global behavior arises when the particles frequently cooperate. In our literature review, some of the well-accepted optimization methods are ant colony optimization (ACO) [26], particle swarm optimization (PSO) [51,58,40], and artificial bee colony (ABC) [63]. Based on this review, PSO has been becoming an emerging popular optimization algorithm among researchers because it performs well in several application domains [13]. These optimization approaches are integrated into the analog computer-aided design (CAD) tools for the topology selection for the optimal sizing of complex ICs and the actual layout extraction of the circuits [6,29] among the different CAD tools available OPASYN [11] and DELIGHT.SPICE [24] employ classical optimization techniques, whereas IDAC [44], OASYS [35], and ASLIC [43] are heuristic-based system design techniques. The contributions in this work are the optimal sizing and design of the one-stage operational amplifier circuit with current mirror load with a view to high gain, low power dissipation, and less area. With particular technology parameters, GA and PSO algorithms are applied to the design specifications, which are the optimal size of each CMOS transistor to generate the minimum area of the total design. As a global optimization method, GA and PSO algorithms have a smaller number of primitive mathematical operators. In addition, the simulation results warrant that the proposed GA and PSO algorithms-based amplifier design yields less area, high gain, and dissipates small power, satisfying the other performance parameters best. The rest of the paper is organized as follows: Section 2presents the literature review of previous studies. Next, the application of optimization methods in analog IC design are discussed. Section 4briefly discusses the proposed GA and PSO algorithms and the steps involved in the analog IC design. In Section 5, comprehensive and demonstrative results are discussed and validated with the Spectre simulator. Finally, Section 6concludes this paper. 2 Literature Review There are two main types of approaches for analog circuit design automation. The first method is called equation-based, which is the reverse process of the circuit analysis technique. Because circuit sizing is being done mathematically, automation is faster because of the simplified device equations and approximations [43,57]. However, the designers have to trade off with accuracy. The second approach is the simulation-based method that initializes a set of performance constraints characterized by complex trade-offs. In addition, this approach uses a complete circuit simulator embedded in a core optimization program. The second method usually requires several iterations to adjust transistor sizes, and the core optimization program needs to assess the performance every iterations. Although the simulation-based technique is more accurate, its implementation in the IC design optimization process takes a considerable amount of time. Sizing rules are investigated for the analog integrated circuit designs synthesis in [14]. A GA-based CMOS operational amplifier synthesizer called DARWIN is studied in [10] regarding the topology selection and circuit sizing. An automated circuit design process for the CMOS amplifier’s evolution and subsequent design using the combination of genetic programming and current flow analysis has been published in [52]. In [60], the CMOS op-amp design can be approximated by applying geometric programming techniques as a convex optimization (CO) problem. To automatically size the high-performance analog IC design, an evolution-based approach called the memetic algorithm is developed [22]. Authors in [34] used HSPICE as the circuit simulator to optimize second-generation current conveyors and proposed the multi-objective evolutionary algorithm (EA) based on decomposition. In addition, a multi-objective heuristic [16,5] and PSO algorithm [1] are applied for optimal current conveyor design without a circuit evaluator such as HSPICE, Spectre, etc. In [4], PSO is conducted for dynamic reconfiguring field-programmable analog circuits. A one-stage op246 MENDEL — Soft Computing Journal, Volume 29, No.gk, .2+2K#2` 2023, Brno, Czech RepublicX Hoang-g2igHX,gE volutionary Optimization Techniques in Analog Integrated Circuit Designs Figure 1: Genetic algorithm flow. amp with initial constraints defined specifications for the PSO usage purpose is considered and evaluated by external parameters such as high temperature, fabrication faults, etc. Moreover, PSO is also used for reconfigurable sensor electronics [3]. Hierarchical particle swarm optimization (HPSO) has been studied for lowpower and low-voltage analog circuit designs [56]. In [7,64], a synthesis tool of a cascaded low noise amplifier (LNA) is developed and designed automatically based on simulated annealing (SA) algorithm, which has an adaptive tunneling mechanism and post-optimization sensitivity analysis in terms of process, design, and temperature. The studies about the application of EA for the synthesis and sizing of analog ICs are explicitly shown in [17]. Most of the aforementioned heuristic algorithms present the problems of fixing the control parameters of the algorithm, ill-consider convergence, stagnation, and revisiting the same solution repeatedly. The real-life applications of soft computing techniques in different fields are presented in [9]. The drawbacks of the conventional PSO are ill-consider convergence and stagnation problems [21,32,54]. The authors propose an alternative PSO to overcome these problems, combining the initial random search and PSO for the optimal one-stage op-amp with the current mirror load. Because the type of work is not done widely, this is the motivation for the work. The authors have adopted the one-stage op-amp circuit with the current mirror load. 3 Evolutionary Optimization in Analog IC Design This section presents the GA and PSO, whose process are shown in Figure 1and 2, respectively. 3.1 Genetic Algorithm Either evolutionary algorithms (EAs) or GAs are iterative optimization processes based on genetic factors of the population [53]. In EAs, each possible solution is encoded in a chromosome. Then, the execution begins with a random initial population generated from n chromosomes. At each iteration or generation, crossover and mutation operators evolve to generate a new population from the previous ones based on fitness functions. The crossover operator combines the population of parent chromosomes to generate offspring, while the mutation operator introduces random modifications to particular individuals to gain the design space exploration [36]. Although there are several kinds of EAs, non-dominated genetic algorithms are popular for procuring diversity on the Pareto front [53,36]. Regarding the non-dominated genetic algorithms, the non-dominated genetic algorithm II (NSGA-II) is an instance of EAs, which is proposed as an advanced version of NSGA [48]. NSGA-II computes fast and uses elitism and crowding distance calculations to provide diversity in the non-dominated Pareto front [48]. Moreover, this algorithm utilizes the 247 MENDEL — Soft Computing Journal, Volume 29, No.gk, .2+2K#2` 2023, Brno, Czech RepublicX GA as the search engine, simulated binary crossover (SBX), and polynomial mutation [48,2]. These operators determine how the generated children will be different from their parents. Therefore, they define space exploration, and then NSGA-II has been successfully applied for the optimization of circuits [2]. 3.2 Particle Swarm Optimization The PSO is a meta-heuristic approach that executes an iterative optimization based on the behavior of nature animals such as birds, ants, or fishes. PSO is based on the mathematical models given in [19] and [25], [55]. Its behavior is initialized by a random set of particles whose search space was defined and bounded. The PSO method is intended to achieve the favorable initial position and velocity of particles. Based on [19] and [25], the positions of particles are changed every iteration. Depending on the value of some random parameters, the velocity is adjusted. In this manner, the position pi and velocity vi are updated until at least one of the stopping criteria, such as design requirements, a maximum number of generations, a running time limit, etc., is met. The updating equations pbest and gbest provide information on the best position of the particle and the best global position that is measured among all particles. The parameter rand() returns a random and uniform real value between 0 and 1. The constant parameter c1 denotes the confidence of a particle, and c2 denotes its confidence in the swarm. In this paper, we set the constant parameters c1 and c2 equal to 2, as recommended in [20]. vi=vi+c1×rand()×(pbest−pi)+c2×rand()×(gbest−pi) (1) pi=pi+vi(2) 4 Proposed Analog Integrated Circuit Optimization Process In the analog IC design flow, the definition of transistor sizes, device values, bias voltages and currents is called the sizing procedure. It can be implemented, in general, by two approaches: knowledge-based sizing or optimization-based sizing. In the knowledge-based approach, the circuit sizing is performed based on the experience of the designers. This method uses analytic design equations that relate circuit performance to device characteristics. Although it is a good approach for older technologies, it is unsuitable for designs in modern fabrication technologies since modeling short-channel effects makes the design equations extremely complex. Simplification leads to inaccurate values far from the actual circuit response. Also, exploring transistor operation regions other than solid inversion is challenging. The optimization-based approach transforms the design procedure into a general optimization problem. Figure 2: Particle swarm optimization flow. The circuit performance is modeled by a cost function, and the design space is automatically explored by an optimization heuristic searching for optimized solutions. According to Barros et al., the optimization method depends on the design optimization model, which can be classified as equation-based, simulationbased, or learning-based. The equation-based method uses simplified equations originating from large-signal and small-signal analyses of the circuit topology. It allows a fast estimation of circuit performance but lacks accuracy. The application of this method has been demonstrated in the literature review, mainly with geometric programming. The circuit performance is modeled by polynomial equations, which guarantee to find an optimal solution in a fast computational time. However, this modeling implies simplifications that compromise accuracy since performance equations are not posynomials. Simulation-based methods use electrical simulators such as SPICE to estimate circuit performance. This performance estimation method is purely numerical and tends to consume a sizeable computational time since several iterations are necessary to resolve the convergence algorithm implemented by SPICE. However, this method gives a very accurate performance estimation [39]. Electrical simulation allows the calculation of all design specifications in both time and frequency domains. Another advantage is that corner models or 248 MENDEL — Soft Computing Journal, Volume 29, No.gk, .2+2K#2` 2023, Brno, Czech RepublicX Hoang-g2igHX,gE volutionary Optimization Techniques in Analog Integrated Circuit Designs Figure 3: Input and output of the optimization. Figure 4: Proposed analog integrated circuit design flow. Monte Carlo simulations can estimate circuit variability and sensitivity. The tool proposed by Phelps et al. uses the simulated annealing heuristic approach to explore a multiobjective cost function using the Cadence Spectre simulator for performance estimation. The exploration of the design space using multi-objective genetic optimization is presented by De Smedt and Gielen, in which the calculation of the hypersurface of Paretooptimal design points explores the trade-off between competing objectives. Learning-based methods provide fast performance evaluation and good accuracy. It is obtained using support vector machines and fuzzy neural networks. The models are trained from electrical simulations. The drawbacks are the high effort necessary to prepare the models with the desired accuracy - a considerable amount of simulation data is needed - and the low reconfigurability since a simple modification in the circuit topology might make the trained model unsuitable for the application. Figure 3and 4shows the scheme for implementation of an analog optimization-based tool with simulationbased performance evaluation. The device takes the circuit topology, design specifications, and technology parameters as inputs. The optimization core generates solutions for the optimization problem according to the chosen technique. For each iteration, it is necessary to evaluate the quality of the developed solution, which is quantified by a cost function to indicate the performance of the generated key concerning the desired specifications. The performance is estimated by SPICE simulation of a set of test benches in which design specifications can be extracted. 249 MENDEL — Soft Computing Journal, Volume 29, No.gk, .2+2K#2` 2023, Brno, Czech RepublicX Figure 5: The one-stage operational amplifier schematic. Figure 6: Fitness function versus iterations. 5 An Optimal Design of One-stage Operational Amplifier with Current Mirror Load 5.1 Circuit Topology In this paper, the optimization process of the CMOS one-stage amplifier circuit with the current mirror load in Figure 5is carried out. Various design specifications are considered, including slew rate (SR), small-signal differential voltage gain (Av), maximum input standard mode range (ICMR) (VIC (max)), minimum ICMR (VIC (min)), all having specific minimum and maximum ranges. In addition, the design parameters are aspect ratio (W/L) values of different MOS transistors used in the circuits and load capacitance (CL). The design process is implemented with the help of the relationships that define the specifications. From the relationships, an objective function or fitness function is developed to obtain the optimal (W/L) values of all the MOS transistors used in the circuit and the DC bias currents to minimize the total area occupied by the MOS transistors as well as the total power dissipation in the circuits. 5.2 The Plot of Convergence of the GA, PSO, and the Proposed PSO Figure 6shows the plots of the convergence of the GA, PSO, and proposed PSO for the one-stage operational amplifier circuit. The MOS transistor has occupied a total area of 109.6 um2, and the whole time taken for the execution is one hour for 100 fitness evaluations (which is computed as the product of the number of cost function evaluations per generation cycle and the number of generation cycles). The convergence plots show that PSO achieves the near-global optimal minimum values of total MOS area in less than 100 fitness evaluations for each circuit design. Therefore, the proposed PSO algorithm optimizes the best for the present study. 5.3 Simulation Results for One-stage Operational Amplifier Figure 7shows the relationship between the circuit’s open loop gain versus iteration when applying each algorithm. Classical GA and PSO algorithms experience a more sensitive change in the simulated input value. With GA, the gain of the circuit increases from 39 dB to 41.5 dB and then remains constant at 40.8 dB as from the 60th iteration. Therefore, the gain of the circuit when performing the GA optimization is 40.8 dB. Contrary to the results from the GA algorithm, the circuit gain decreases from 41 dB to 40.1 dB and remains constant at 40.6 dB from the 30th iteration. Thus, the gain of the circuit is 40.1 dB when performing optimization using PSO. With the PSO algorithm proposed in this paper, the circuit’s gain only increases from 40.25 dB to 41 dB and then remains unchanged at 40.79 dB from the 30th iteration. Therefore, the proposed PSO algorithm optimized the circuit’s gain of 40.79 dB, which aligns with the desired value according to the specifications. Figure 7: Open loop gain versus iterations. Figure 8presents the graph of errors versus iteration of each type of algorithm. The error when applying each algorithm to optimize the one-stage amplifier 250 MENDEL — Soft Computing Journal, Volume 29, No.gk, .2+2K#2` 2023, Brno, Czech RepublicX Hoang-g2igHX,gE volutionary Optimization Techniques in Analog Integrated Circuit Designs Figure 8: Error versus iterations. circuit is generally deficient, approximately 0.6%. To achieve an error value of 0.6%, the evaluation iterations of each algorithm needs 10 iterations. Figure 9indicates the simulation results of slew rate versus iterations when implementing optimization algorithms. The slew rate is almost unchanged, convergence is achieved at five iterations. In subsequent iterations, the slew rate remains 15 V/µs and satisfies the specification. Figure 9: Slew rate versus iterations. Figure 10 introduces the simulation results of CMRR or VIC max and VIC min of the one-stage operational amplifier circuit. Based on the simulation results, VIC max reaches 0.4 V after the optimization process converges at ten iterations, while VIC min reaches -0.3 V after converging at five iterations. The values VIC max and VIC min both satisfy the initial requirement. 6 Conclusion In this work, particle swarm optimization (PSO) and genetic algorithm (GA) are proposed for the optimal design of the one-stage operational amplifier circuit Figure 10: VIC max and VIC min versus iterations. with current mirror load. The design specifications for the optimization process includes slew rate, gain, power dissipation, and CMRR. The equations of the one-stage operational amplifier design are used for the cost function regarding those several design specifications. The design parameters, such as widths of MOS transistors, DC bias current, capacitances, etc., are achieved by implementing the GA and PSO algorithms to the circuits in the Spectre simulator, which validates the exact values of design specifications and performance parameters. Moreover, the proposed GA and PSO approaches have superior performance for CMOS operational amplifiers with current mirror load, muchimproved gain, CMRR, and total power dissipation. The simulation study establishes that the proposed GA and PSO-based optimization technique adopted for analog IC optimization that efficiently finds the near global optimal solution in multi-objective optimization. Acknowledgement: This research is funded by Vietnam National University Ho Chi Minh City (VNUHCM) under grant number: DS2023-20-03. References [1] Afacan, E., Lourenc¸o, N., Martins, R., and D¨ undar, G. Review: Machine learning techniques in analog/rf integrated circuit design, synthesis, layout, and test. Integration 77 (2021), 113–130. [2] Ahmed, R., Mahadzir, S., Rozali, N. E. M., Biswas, K., Matovu, F., and Ahmed, K. Artificial intelligence techniques in refrigeration system modelling and optimization: A multidisciplinary review. Sustainable Energy Technologies and Assessments 47 (2021), 101488. [3] Alawieh, M., Wang, F., and Li, X. Efficient hierarchical performance modeling for integrated circuits via bayesian colearning. In Proceedings of the 54th Annu. Design Automat. Conf. (2017), p. 1–6. 251 MENDEL — Soft Computing Journal, Volume 29, No.gk, .2+2K#2` 2023, Brno, Czech RepublicX [4] Alawieh, M. B., Wang, F., and Li, X. Efficient hierarchical performance modeling for analog and mixed-signal circuits via bayesian colearning. IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. 37 (2018), 2986–2998. [5] Alawieh, M. B., Williamson, S. A., and Pan, D. Z. Rethinking sparsity in performance modeling for analog and mixed circuits using spike and slab models. In Proceedings of the 56th Annu. Design Automat. Conf. (DAC) (2019), p. 1–6. [6] Alpaydin, G., Balkir, S., and Dundar, G. An evolutionary approach to automatic synthesis of high-performance analog integrated circuits. IEEE Trans. Evol. Comput. 7 (2003), 240–252. [7] Bishop, C. M., Ed. Pattern Recognition and Machine Learning. 2006. [8] Bujok, P., Lacko, M., and Kolenovsk´ y, P. Differential evolution and engineering problems. MENDEL 29 (2023), 45–54. [9] Casella, G., and George, E. I. Explaining the gibbs sampler. Amer. Statistician 46 (1992), 167–174. [10] Chang, E., et al. Bag2: A process-portable framework for generatorbased ams circuit design. In Proceedings of the IEEE Custom Integr. Circuits Conf. (CICC) (2018), p. 1–8. [11] Cortes, C., Mohri, M., and Rostamizadeh, A. L2 regularization for learning kernels. In Proceedings of the Twenty-Fifth Conference on Uncertainty in Artificial Intelligence (UAI2009) (2012). [12] Gardner, J. R., Kusner, M. J., Xu, Z. E., Weinberger, K. Q., and Cunningham, J. P. Bayesian optimization with inequality constraints. In Proceedings of the ICML (2014), p. 937–945. [13] Glover, F. Tabu search — part ii. ORSA J. Comput. 2 (1990), 4–32. [14] Hakhamaneshi, K., Werblun, N., Abbeel, P., and c, V. S. Analog circuit generator based on deep neural network enhanced combinatorial optimization. In Proceedings of the 56th Annu. Design Automat. Conf. (2019), p. 1–2. [15] Hoang, T., Pham, H. X., and Tran, Q. H. A novel design of low-power, high-speed ota in 50nm-cmos technology. In 3rd Solid State Systems Symposium – VLSIs and Semiconductor Related Technologies (2014). [16] Hoerl, A. E., and Kennard, R. W. Ridge regression: Biased estimation for nonorthogonal problems. Technometrics 42 (2000), 80–86. [17] Ishwaran, H., and Rao, J. S. Spike and slab variable selection: Frequentist and bayesian strategies. Ann. Statist 33 (2005), 730–773. [18] Islamoglu, G., Cakici, T. O., Afacan, E., and Dundar, G. Artificial neural network assisted analog ic sizing tool. In Proceedings of the 16th Int. Conf. Synth., Modeling, Anal. Simulation Methods Appl. Circuit Design (SMACD) (2019), p. 9–12. [19] Jiao, F., and Doboli, A. A low-voltage, lowpower amplifier created by reasoning-based, systematic topology synthesis. In Proceedings of IEEE Int. Symp. Circuits Syst. (ISCAS) (2015), p. 2648–2651. [20] Kaveh, A., Ed. Advances in metaheuristic algorithms for optimal design of structures. 2014. [21] Kosari, A., Moosavifar, M., and Wentzloff, D. D. A 152 µw -99 dbm bpsk16-qam ofdm receiver for lpwan applications. In Proceedings of the IEEE Asian Solid-State Circuits Conf. (A-SSCC) (2018), p. 303–306. [22] Li, X., Zhang, W., and Wang, F. Large-scale statistical performance modeling of analog and mixed-signal circuits. In Proceedings of the IEEE Custom Integr. Circuits Conf. (2012), p. 1–8. [23] Li, Y., Wang, Y., Li, Y., Zhou, R., and Lin, Z. An artificial neural network assisted optimization system for analog design space exploration. IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. 39 (2020), 2640–2653. [24] Liashchynskyi, P. B., and Liashchynskyi, P. Grid search, random search, genetic algorithm: A big comparison for nas. ArXiv abs/1912.06059 (2019). [25] Lin, M. P.-H., Chang, Y.-W., and Hung, C.- M. Recent research development and new challenges in analog layout synthesis. In Proceedings of the 21st Asia South Pacific Design Automat. Conf. (ASP-DAC) (2016), p. 617–622. [26] Liu, B., Fernandez, F. V., and Gielen, G. G. E. Efficient and accurate statistical analog yield optimization and variation-aware circuit sizing based on computational intelligence techniques. IEEE Trans. Comput.- Aided Design Integr. Circuits Syst. 30 (2011), 793–805. [27] Liu, B., Zhao, D., Reynaert, P., and Gielen, G. G. E. Gaspad: A general and efficient mm-wave integrated circuit synthesis method based on surrogate model assisted evolutionary algorithm. IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. 33 (2014), 169–182. [28] Liua, B., and Nikolaeva, A. Efficient global optimization of mems based on surrogate model assisted evolutionary algorithm. In Proceedings of the Design, Automat. Test Eur. Conf. Exhib. (DATE) (2016), pp. 555–558. [29] Lourenco, N., et al. On the exploration of promising analog ic designs via artificial neural networks. In Proceedings of the 15th Int. Conf. Synth., Modeling, Anal. Simulation Methods Appl. Circuit Design (SMACD) (2018), p. 133–136. [30] Lyu, W., et al. An efficient bayesian optimization approach for automated optimization of analog circuits. IEEE Trans. Circuits Syst. I, Reg. Papers 65 (2018), 1954–1967. [31] Lyu, W., Yang, F., Yan, C., Zhou, D., and Zeng, X. Batch bayesian optimization via multiobjective acquisition ensemble for automated ana252 MENDEL — Soft Computing Journal, Volume 29, No.gk, .2+2K#2` 2023, Brno, Czech RepublicX Hoang-g2igHX,gE volutionary Optimization Techniques in Analog Integrated Circuit Designs log circuit design. In Proceedings of the Int. Conf. Mach. Learn. (2018), p. 3306–3314. [32] Mallick, and Soumen. Optimal sizing of cmos analog circuits using gravitational search algorithm with particle swarm optimization. International Journal of Machine Learning and Cybernetics 8 (2017), 309–331. [33] Marler, R. T., and Arora, J. S. Survey of multi-objective optimization methods for engineering. Struct. Multidisciplinary Optim. 26 (2004), 369–395. [34] McConaghy, T. High-dimensional statistical modeling and analysis of custom integrated circuits. In Proceedings of the IEEE Custom Integr. Circuits Conf. (CICC) (2011), p. 1–8. [35] Meng, K.-H., Pan, P.-C., and Chen, H.-M. Integrated hierarchical synthesis of analog/rf circuits with accurate performance mapping. In Proceedings of the 12th Int. Symp. Qual. Electron. Design (2011), pp. 1–8. [36] Muteba, M. Optimization of air gap length and capacitive auxiliary winding in three-phase induction motors based on a genetic algorithm. Energies 14 (2021), 4407. [37] Naumowicz, M., Melosik, M., and Katarzy’nski, P. Technology migration of analogue cmos circuits using hooke-jeeves algorithm and genetic algorithms in multi-core cpu systems. In Proceedings of the 20th Int. Conf. Mixed Design Integr. Circuits Syst. (MIXDES) (2013), p. 267–272. [38] Nguyen, H. M., Pham, L. D., and Hoang, T. A novel li-ion battery charger using multi-mode ldo configuration based on 350 nm hv-cmos. Analog Integr Circ Sig Process 88 (2016), 505–516. [39] Nguyen, H. T., and Hoang, T. A novel framework of genetic algorithm and spectre to optimize delay and power consumption in designing dynamic comparators. Electronics 12 (2023), 3392. [40] Nocedal, J., and Wright, S., Eds. Numerical Optimization. 2006. [41] Okobiah, O., Mohanty, S., and Kougianos, E. Fast design optimization through simple kriging metamodeling: A sense amplifier case study. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 22 (2014), 932–937. [42] Okobiah, O., Mohanty, S. P., and Kougianos, E. Exploring kriging for fast and accurate design optimization of nanoscale analog circuits. In Proceedings of the IEEE Comput. Soc. Annu. Symp. VLSI (2014), p. 244–247. [43] Pan, P.-C., Chen, H.-M., and Lin, C.-C. Page: Parallel agile genetic exploration towards utmost performance for analog circuit design. In Proceedings of the Design, Automat. Test Eur. Conf. Exhib. (DATE) (2013), p. 1849–1854. [44] Pan, P.-C., Huang, C.-C., and Chen, H.-M. An efficient learning-based approach for performance exploration on analog and rf circuit synthesis. In Proceedings of the 56th Annu. Design Automat. Conf. (2019), pp. 1–2. [45] Park, S. J., Bae, B., Kim, J., and Swaminathan, M. Application of machine learning for optimization of 3-d integrated circuits and systems. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 25 (2017), 1856–1865. [46] Peng, B., Yang, F., Yan, C., Zeng, X., and Zhou, D. Efficient multiple starting point optimization for automated analog circuit optimization via recycling simulation data. In Proceedings of the Design, Automat. Test Eur. Conf. Exhib. (DATE) (2016), p. 1417–1422. [47] Qian, L., Bi, Z., Zhou, D., and Zeng, X. Automated technology migration methodology for a mixed-signal circuit based on multistart optimization framework. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 23 (2015), 2595–2605. [48] Rojec, Z., Fajfar, I., and Burmen, A. Evolutionary synthesis of failure-resilient analog circuits. Mathematics 10 (2022), 156. [49] Shah, A., and Ghahramani, Z. Parallel predictive entropy search for batch global optimization of expensive objective functions. In Proceedings of the Adv. Neural Inf. Process. Syst. (2015), p. 3330–3338. [50] Shahriari, B., Swersky, K., Wang, Z., Adams, R. P., and de Freitas, N. Taking the human out of the loop: A review of bayesian optimization. In Proceedings of the IEEE (2016), p. 148–175. [51] Singhee, A., Singhal, S., and Rutenbar, R. A. Practical, fast monte carlo statistical static timing analysis: Why and how. In Proceedings of the IEEE/ACM Int. Conf. Computer-Aided Design (2008), p. 190–195. [52] Snoek, J., et al. Scalable bayesian optimization using deep neural networks. In Proceedings of the Int. Conf. Mach. Learn. (2015), p. 2171–2180. [53] Valencia-Ponce, M. A., Tlelo-Cuautle, E., and de la Fraga, L. G. On the sizing of cmos operational amplifiers by applying many-objective optimization algorithms. Electronics 10 (2021), 3148. [54] Vural, R. A., and Yildirim, T. Analog circuit sizing via swarm intelligence. AEU-International journal of electronics and communications 66 (2012), 732–740. [55] Wang, D., Tan, D., and Liu, L. Particle swarm optimization algorithm: an overview. Soft computing 22 (2018), 387–408. [56] Wang, F., et al. Bayesian model fusion: Large-scale performance modeling of analog and mixed-signal circuits by reusing early-stage data. IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. 35 (2016), 1255–1268. [57] Wang, H., Yang, J., Lee, H.-S., and Han, S., Eds. Learning to design circuits. 2018. 253